CSCI E-93, Fall 2017: Computer Architecture Agendasites.fas.harvard.edu/~cscie287/fall2017/Class...

CSCI E-93, Fall 2017:Computer Architecture

AgendaProf. James L. Frankel

Harvard University

Version of 7:28 PM 5-Dec-2017Copyright © 2017 James L. Frankel. All rights reserved.

First Class Meeting on 8/29/2017

• Syllabus• Including books

• Order books• Contemporary Logic Design, 2nd Ed. by Katz & Borriello• Computer Organization and Design: The Hardware/Software Interface, 5th Ed. by

Patterson & Hennessy• The Designer's Guide to VHDL, 3rd Ed. by Ashenden

• Students outside New England who will not be coming to class for the midterm exam should make arrangements now for a proctor

Section

• Section meets immediately before class• 6:35-7:35 PM in 1 Story Street, Room 307

• Very important• Discusses concepts & issues that are not covered in class

• Great forum for a more interactive dialog

• Is live streamed and also recorded

Altera/Terasic DE2-70/DE2-115 Hardware

• Show class the hardware• Distance students should order the hardware now

• Terasic DE2-115 FPGA kit• Available from Terasic (http://www.terasic.com.tw/en/)• Academic pricing is available ($595 usual; $309 academic)

• In addition to Terasic FPGA board, order USB to serial adapter & serial cable• Possible static dissipative devices: mat, strap, ground point

• For local students, on September 26, 2017 during class, we will lend you the hardware for the semester• No static dissipative devices are included

http://www.terasic.com.tw/en/

Say Hello!, Using nice, Problem Set 0

• Submit a video using Say Hello! in Canvas

• Ensure that your Harvard Key is established• Login to nice.harvard.edu using SFTP/SSH (SecureCRT)

• Ensure that you have a g.harvard.edu e-mail address

• Ensure that you have an account on the nice computers

• Complete Problem Set 0• Install git as described on the section web site• Modify the course questionnaire with your personal answers• Fix warnings and errors in fix-this-program on the nice computers• Write the word count program• Push a branch named “ps0-submit“, create a merge request, add the appropriate comment

Using Piazza and OS Overview Slides

• Ask questions in Piazza so the whole class can benefit from the answers• Personal questions should be sent to the course staff via e-mail

• If appropriate, include all three course staff members in e-mail to allow a fastest reply

• Cover Binary Logic Levels & Boolean Logic slides

Pre-Class 9/5/2017

• Photos of class members, course staff, AV staff

Second Class Meeting on 9/5/2017

• Questions?• From last class?

• From PS0?

• From section?

• Anything else?

• Reminder: Students outside New England who will not be coming to class for the midterm exam should make arrangements now for a proctor• Midterm will be three hours long

• Must start the exam from 7:40 PM ET on Tuesday, October 10, 2017 to 7:40 PM ET on Wednesday, October 11, 2017

Reminder about Section





Problem Sets

• Problem Set 0 was due this past Sunday night

• Go over Problem Set 1• Due on midnight Sunday, September 17, 2017


• Distance students should order the hardware now• Terasic DE2-115 FPGA kit• Available from Terasic (http://www.terasic.com.tw/en/)

• In addition to the Terasic FPGA board, order USB to serial adapter & serial cable

• Possible static dissipative devices: mat, strap, ground point

• Academic pricing is available ($595 usual; $309 academic)

• For local students, on September 26, 2017 during class, we will lend you the hardware for the semester• No static dissipative devices are included• You must be present in the last class meeting to return the hardware

• Please respond to the PollEv survey (sent through Piazza) about picking up FPGA hardware in person


Say Hello! in Canvas

• Please submit a Say Hello! video in Canvas

Enroll in Piazza

• Enroll in Piazza• Important questions are answered in that forum


• If appropriate, include all three course staff members in e-mail to allow the fastest reply

New Material for this Week

• Finish covering Boolean Logic slides• Start with the Flip Flop slide

• Cover new slides• Boolean Logic Continued

• Advanced Boolean Logic

• Laws and Theorems of Boolean Logic

• Computer Logic

• Place Values

Pre-Class 9/12/2017

• Photos of class members

Third Class Meeting on 9/12/2017

• Questions?• From prior classes?

• From PS0?

• From PS1?

• From section?

• Anything else?

Reminder about Proctored Midterm Exam

• Reminder: Students outside New England who will not be coming to class for the midterm exam should make arrangements now for a proctor• Midterm will be three hours long

• Must start the exam from 7:40 PM ET on Tuesday, October 10, 2017 to 7:40 PM ET on Wednesday, October 11, 2017

Reminder about Section Meetings





Reminder about Say Hello! in Canvas


Reminder about Enrolling in Piazza





• Please respond to the Piazza survey about picking up FPGA hardware in person so we know how many hardware kits we need to have





• For local students, on September 26, 2017 during class, we will lend you the hardware for the semester• No static dissipative devices are included• You must be present in the last class meeting to return the hardware


Problem Sets

• Problem Set 1 is due this coming Sunday, September 17, 2017

• Go over Problem Set 2• Due on midnight Sunday, October 1, 2017


• Cover new slides• Numeric Encodings

• Gray Codes & Karnaugh Maps

• Canonical Form, Minterms & Maxterms

• Dealing with Time in Combinational Circuits

• MIPS Instruction Set• Covered through the Stack slide

Pre-Class 9/19/2017


Fourth Class Meeting on 9/19/2017


• About Karnaugh Maps? Minterms & Maxterms? Timing Waveform Diagrams?

• About CPUs?

• From PS0?

• From PS1?

• From PS2?

• From section?

• Anything else?

Reminder about Midterm Exam

• Our midterm exam will be held in our classroom – 53 Church Street, Room L01 – on Tuesday, October 10, 2017 from 7:40 PM ET to 10:40 PM ET• The exam allows open-book access to only the three required textbooks

• But, the midterm exam will not cover VHDL• Therefore, the VHDL book (The Designer's Guide to VHDL, Third Edition; Peter J. Ashenden;

Morgan Kaufmann/Elsevier) is not required for the midterm exam.• No electronic devices are allowed• No notes are allowed

• Reminder: Students outside New England who will not be coming to class for the midterm exam should make arrangements now for a proctor• Midterm will be three hours long• Must start the exam from 7:40 PM ET on Tuesday, October 10, 2017 to 7:40 PM ET

on Wednesday, October 11, 2017

http://www.elsevier.com/wps/find/bookdescription.cws_home/714711/description

http://www.elsevier.com/

Piazza Hardware Poll

• Not everyone has completed the Piazza hardware poll about purchasing your own hardware vs. borrowing for the semester

• Please complete the poll at Borrowing Hardware

• Please make sure that the poll has registered your response

• We will be bringing only the required hardware to class NEXT WEEK

https://piazza.com/class/j6zb37sslwl29u?cid=25


• Please respond to the Piazza survey about picking up FPGA hardware in person so we know how many hardware kits we need to have





• For local students, NEXT WEEK (on September 26, 2017) during class, we will lend you the hardware for the semester

• No static dissipative devices are included• You must be present in the last class meeting to return the hardware


Problem Sets

• Problem Set 1 was due on Sunday, September 17, 2017

• Problem Set 2 will be due on midnight Sunday, October 1, 2017• You may find it helpful to look at the document Criteria for Final Project

Proposal on the class web site under Slides used in class

http://sites.fas.harvard.edu/~cscie287/fall2017/slides/Criteria for Final Project Proposal.txt

Possible Sailing Trips

• We may be able to take some students sailing over the upcoming weekends• If you’re interested, please check your schedule and I’ll let you know what’s

happening in class before each upcoming weekend

• Saturday this weekend is possible, but we’ll have to see what Hurricane Jose does

• Sunday this weekend is *not* possible

• I’ll send e-mail if we will be able to go sailing on Saturday


• Continue covering the MIPS Instruction Set slides• Start with the CPU Instruction Formats slide

• Cover new slides• MIPS Datapath - Single Memory - No Pipelining

• MIPS Coding Snippets

• MIPS Assembly Language

Pre-Class 9/26/2017


Fifth Class Meeting on 9/26/2017



• About CPUs?

• About MIPS?

• From PS0?

• From PS1?

• From PS2?

• From section?

• Anything else?


• Our midterm exam will be held in our classroom – 53 Church Street, Room L01 – on Tuesday, October 10, 2017 from 7:40 PM ET to 10:40 PM ET• The exam allows open-book access to only the three required textbooks

• But, the midterm exam will not cover VHDL• Therefore, the VHDL book (The Designer's Guide to VHDL, Third Edition; Peter J. Ashenden;

Morgan Kaufmann/Elsevier) is not required for the midterm exam.• No electronic devices are allowed• No notes are allowed

• Reminder: Students outside New England who will not be coming to class for the midterm exam should make arrangements now for a proctor• Midterm will be three hours long• Must start the exam from 7:40 PM ET on Tuesday, October 10, 2017 to 7:40 PM ET

on Wednesday, October 11, 2017




• Distance students should have already ordered the hardware• Terasic DE2-115 FPGA kit• Available from Terasic (http://www.terasic.com.tw/en/)




• For local students, TODAY during a break in our class meeting, we will lend you the hardware for the semester• No static dissipative devices are included• You must be present in the last class meeting to return the hardware


Problem Sets

• Problem Set 1 was due on Sunday, September 17, 2017

• Problem Set 2 will be due at midnight on Sunday, October 1, 2017• You may find it helpful to look at the document Criteria for Final Project

Proposal on the class web site under Slides used in class

• Problem Set 3 will be due at midnight on Sunday, October 15, 2017

http://sites.fas.harvard.edu/~cscie287/fall2017/slides/Criteria for Final Project Proposal.txt




• This coming weekend is *not* possible


• Cover new slides• MIPS Coding Snippets

• MIPS Assembly Language

• PDP-8 Introduction to Programming, pp. 2-4 to 2-27

• PDP-11 Handbook, pp. 6-10

• PDP-11 Architecture Handbook, pp. 26-123

Pre-Class 10/3/2017


Sixth Class Meeting on 10/3/2017



• About CPUs?

• About MIPS, PDP-8, or PDP-11?

• From PS0?

• From PS1?

• From PS2?

• From section?

• Anything else?


• Our midterm exam will be held in our classroom – 53 Church Street, Room L01 –NEXT WEEK on Tuesday, October 10, 2017 from 7:40 PM ET to 10:40 PM ET• The exam allows open-book access to only the three required textbooks

• But, the midterm exam will not cover VHDL

• Therefore, the VHDL book (The Designer's Guide to VHDL, Third Edition; Peter J. Ashenden; Morgan Kaufmann/Elsevier) is not required for the midterm exam.

• No electronic devices are allowed• No notes are allowed

• Reminder: Students outside New England who will not be coming to class for the midterm exam should have already made arrangements for a proctor• Midterm will be three hours long• Must start the exam from 7:40 PM ET on Tuesday, October 10, 2017 to 7:40 PM ET on

Wednesday, October 11, 2017



Material Covered in the Midterm Exam

• Problem Sets 0 through 2 (and note about 3)• Material doesn’t have to be in a Problem Set to be eligible for the midterm

• Working through Problem Set 3, Questions 2-7 may be helpful

• Readings from the Syllabus• Chapters 1 through 8 in Katz and Borriello

• Chapters 1 through 4 and 5.6 through 5.18, and Appendix B in Patterson and Hennessy

• Material Covered in Class• All class meetings including today’s class meeting

• Clarifications on Piazza

Problem Sets

• Problem Set 2 was due at midnight on Sunday, October 1, 2017


• Present Problem Set 3




• This coming weekend is a possibility

• I’ll send e-mail with more information if we are able to go


• Continue with Use of the PC as a General Register in the PDP-11 Architecture Handbook after the basic treatment of Addressing Modes on page 62• Cover the instruction set including subroutines and condition codes

• Cover new slides• Hazards and Glitches

• Endianness

• Finite State Machines

• VHDL

Pre-Class 10/17/2017


Eighth Class Meeting on 10/17/2017

• Questions?• From midterm exam? If so, please ask them when we review the exam.

• We will be reviewing it in class today

• From prior classes?• About Karnaugh Maps? Minterms & Maxterms? Timing Waveform Diagrams?

• About CPUs?

• About MIPS, PDP-8, or PDP-11?

• FSMs?

• From Problem Sets: PS0? PS1? PS2? PS3?

• From section?

• Anything else?


• Unfortunately, because of my back issues, we will not be able to take sailing trips this semester

• Because we’re at the end of the sailing season, the boat is being taken out of the water this coming weekend

Problem Sets

• Problem Set 3 will be due at midnight on this coming Sunday, October 22, 2017

• Please use the attribute chip_pin method of performing pin assignment

Problem Set 4


• Present PS4

• Cover Altera Memory Initialization File (.mif) format

• Suggest re-reading Assembler Concepts (a.k.a. Some Assembly Is Required)

• Cover the specification for the interface to terminal I/O

Review the Midterm Exam

• Return midterm exams

• Present statistics on each problem of the midterm exam

• Discuss and solve each midterm exam problem


• Cover new slides• VHDL

• Sample VHDL code from course website

Ninth Class Meeting Agenda – 10/24/2017

• Recap of Section Meeting from Today

• Questions

• Problem Set 3

• Problem Set 4

• Preliminary Final Project Problem Set

• Problem Set 5

• Midterm Exam Review

• More VHDL

• Serial Communication

Questions

• Questions?• From midterm exam? If so, please ask them when we review the exam.

• We will be reviewing it in class today• From prior classes?

• About Karnaugh Maps? Minterms & Maxterms? Timing Waveform Diagrams?• About CPUs?• About MIPS, PDP-8, or PDP-11?• FSMs?

• From Problem Sets: PS3? PS4?• MIF file format?• Memory-mapped I/O?• From section?• VHDL?• Anything else?

Problem Set 3

• Problem Set 3 was due at midnight last Sunday, October 22, 2017

• Please use the attribute chip_pin method of performing pin assignment in all VHDL code

• Please use std_ulogic and std_ulogic_vector (instead of using bit, bit_vector, std_logic, or std_logic_vector)

Problem Set 4

• Assembler for your CPU and programs written in assembly language

• Problem Set 4 will be due at midnight on this coming Sunday, October 29, 2017

Preliminary Final Project Problem Set

• ALU for your CPU

• Preliminary Final Project Problem Set will be due at midnight on Sunday, November 5, 2017

• Present Preliminary Final Project Problem Set

Problem Set 5

• Emulator for your CPU

• Problem Set 5 will be due at midnight on Sunday, November 12, 2017

• Present Problem Set 5

Continue to Review the Midterm Exam

• Return remaining in-person graded midterm exams

• All distance graded midterm exams have been sent to the e-mail address on file with the registrar

• Discuss and solve each midterm exam problem• Last week we went over the ad hoc solution to ALU design problem

(problem 6)


• Continue to discuss VHDL • Signals other than the system clock can be used as a clock for an entity• The top-level entity should have all ports that interface with the outside world

• Any of those signals can then be mapped to lower-level entities as necessary

• One approach on how to write VHDL• Approach a VHDL design problem by first thinking of how to implement the solution in gates

• Map out how to hierarchically decompose the solution into VHDL entities

• As with any other language, choose appropriate names for ports, signals, variables, constants, and generics• Clarity in design is paramount

• Cover new slides• VHDL Looping

• Run sample VHDL code from course website as interest compels

• Cover new slides• Serial Communication

Tenth Class Meeting Agenda – 10/31/2017


• Questions

• More VHDL

• Serial Communication

• Caching

• Virtual Memory

Questions

• Questions?• From midterm exam?• From prior classes?


• From Problem Sets: PS3? PS4? Preliminary Final Project PS? PS5?• MIF file format?• Memory-mapped I/O?• From section?• VHDL?• Anything else?

Problem Set 3

• Problem Set 3 was due at midnight Sunday, October 22, 2017

• Please use the attribute chip_pin method of performing pin assignment in all VHDL code

• Please use std_ulogic and std_ulogic_vector (instead of using bit, bit_vector, std_logic, or std_logic_vector)

Problem Set 4

• Assembler for your CPU and programs written in assembly language

• Problem Set 4 was due at midnight this past Sunday, October 29, 2017



• The Preliminary Final Project Problem Set will be due at midnight on this coming Sunday, November 5, 2017

Problem Set 5


• Problem Set 5 will be due at midnight on Sunday, November 12, 2017


• Continue to discuss VHDL • Signals other than the system clock can be used as a clock for an entity• The top-level entity should have all ports that interface with the outside world

• Any of those signals can then be mapped to lower-level entities as necessary

• One approach on how to write VHDL• Approach a VHDL design problem by first thinking of how to implement the solution in gates

• Map out how to hierarchically decompose the solution into VHDL entities

• As with any other language, choose appropriate names for ports, signals, variables, constants, and generics• Clarity in design is paramount

• Cover new slides• VHDL Looping

• Run sample VHDL code from course website as interest compels

• Cover new slides• Serial Communication• Caching• Virtual Memory

Eleventh Class Meeting Agenda – 11/7/2017


• Questions

• Clocking

• VHDL Issues

• Shifters

• Virtual Memory

• Pipelining

Questions

• Questions?• From midterm exam?• From prior classes?


• From Problem Sets: Preliminary Final Project PS? PS5?• MIF file format?• Memory-mapped I/O?• From section?• VHDL?• Anything else?



• The Preliminary Final Project Problem Set was due at midnight this past Sunday, November 5, 2017

Problem Set 5


• Problem Set 5 will be due at midnight on this coming Sunday, November 12, 2017

Clocking for CPUs

• Present the Clocking slides

Problem Set 6

• Detailed description of the sequencer for your CPU• Actions on each edge of each clock cycle

• VHDL to interface to the memory subsystem

• Problem Set 6 will be due at midnight on Sunday, December 3, 2017

• Present PS6

Hardware Interface to the Memory Subsystem• Present the hardware interface to the memory subsystem

• processor-to-memory interface

• documentation for the memory subsystem


• VHDL Issues?

• Cover new slides• Shifters

• Virtual Memory

• Pipelining

Twelfth Class Meeting Agenda – 11/14/2017


• Questions

• MIF File Format Clarifications

• Structuring VHDL code for the memory interface FSM

• Application Notes

• Pipelining

Questions

• Questions?• From midterm exam?

• From prior classes?

• From Problem Sets: Preliminary Final Project PS? PS5?

• MIF file format?

• Memory-mapped I/O?

• From section?

• VHDL? FSM in VHDL?

• Clocking?

• Anything else?

Problem Set 5


• Problem Set 5 was due this past Sunday, November 12, 2017

Problem Set 6




MIF File Format Clarifications

• Address and data should both be in hex

• The address field in the MIF file is in terms of MIF words – the addresses in the MIF file are *not* byte addresses• That is, address 0 is for the first 16-bit word• Address 1 is for the second 16-bit word• etc.

• More than one 16-bit data word can appear on a single line

• Ranges of addresses can be specified

• See the documentation (Altera Memory Initialization File (.mif) format)

http://sites.fas.harvard.edu/~cscie287/fall2017/def_mif.htm

Structuring VHDL Code for the Memory Interface FSM (1 of 2)• Follow the example on the course web site for the FSM

• See debounceSwitch.vhd

• Use an enumerated type for the FSM states

• Either write two FSMs…• One to interface to the memory subsystem

• And, one to act as the CPU’s sequencer

• Or, embed the memory subsystem interface in the CPU’s sequencer FSM• Interfacing with the memory subsystem will have to occur in several instances

http://sites.fas.harvard.edu/~cscie287/fall2017/Altera/debounceSwitch.vhd

Structuring VHDL Code for the Memory Interface FSM (2 of 2)• Use combinational logic to assert control lines when appropriate

• The combinational logic should be outside the VHDL process• The combinational logic will assert signals when the FSM is in a particular state; for

example:

-- Signal for a memory interface FSMmem_addressready <= '1' when (currentState = BeginMemoryAccess) or

(currentState = WaitForMemDataReadyInvLow) or(currentState = ReadData) else

'0';

-- Handshake signal to a memory interface FSMmemioOperation <= memWrite when (opcode = OPCODE_SW) and

((currentState = WriteData) or(currentState = WriteDataWaiting)) else

memRead;

Application Notes

• AN1: Dealing with DE2-115 Current Strength and Slew Rate

• AN2: DE2-70 Can't place multiple pins assigned to pin location Pin_AD25

• AN3: How to load a MIF file into Quartus

• AN4: How to view and alter memory in Quartus

• AN5: How to run a serial port emulator

• AN6: How to build a Quartus project that uses the memory subsystem

• AN7: Notes on Using Serial Port I/O

http://sites.fas.harvard.edu/~cscie287/fall2017/AN1 DE2-115 Current Strength and Slew Rate.txt

http://sites.fas.harvard.edu/~cscie287/fall2017/AN2 DE2-70 Can't place multiple pins assigned to pin location Pin_AD25.txt

http://sites.fas.harvard.edu/~cscie287/fall2017/AN3 How to load a MIF file into Quartus.txt

http://sites.fas.harvard.edu/~cscie287/fall2017/AN4 How to view and alter memory in Quartus.txt

http://sites.fas.harvard.edu/~cscie287/fall2017/AN5 How to run a serial port emulator.txt

http://sites.fas.harvard.edu/~cscie287/fall2017/AN6 How to build a Quartus project that uses the memory subsystem.txt

http://sites.fas.harvard.edu/~cscie287/fall2017/AN7 Notes on Using Serial Port IO.txt


• Cover new slides• Pipelining

Thirteenth Class Meeting Agenda –11/21/2017• Happy Upcoming Thanksgiving!

• Recap of Section Meeting from Today• Questions

• Basic Electronics• Photo Micrographs of processor chips• Another Architecture: Intel Zilog Z80• Custom VLSI Design• Dataflow Graphs and Architectures

Questions

• Questions?• From midterm exam?• From prior classes?• From Problem Sets: Preliminary Final Project PS? PS5?• MIF file format?• Memory-mapped I/O?• From section?• VHDL? FSM in VHDL?• Clocking?• Pipelining?• Anything else?

Problem Set 6




• This is a great time to catch up on all the Problem Sets!

Upcoming Extension School Deadline

• November 24th is the last day to withdraw with no tuition refund and with course on record with WD/WN (withdrawal) grade

• Check with the course staff if you are concerned about your status in the class


• Cover new slides• Basic Electronics

• Photo Micrographs of processor chips

• Another Architecture: Intel Zilog Z80

• Custom VLSI Design

• Dataflow Graphs and Architectures

Fourteenth Class Meeting Agenda –11/28/2017• Hope you had a great Thanksgiving


• Questions

• Administrivia

• MIF file endian order

• Show and Tell: Core Memory, Silicon Wafer, Chip, Bonded Chip in DIP Carrier

• Custom VLSI Design


• Massively Parallel Processors (incl. GPUs)

Questions

• Questions?• From midterm exam?• From prior classes?• From Problem Sets: Preliminary Final Project PS? PS5?• MIF file format?• Memory-mapped I/O?• From section?• VHDL? FSM in VHDL?• Clocking?• Pipelining?• Basic electronics? VLSI design?• Anything else?

Problem Set 6



• Problem Set 6 will be due this coming Sunday, December 3, 2017 at midnight

• This is a great time to catch up on all the Problem Sets!

Final Project Presentation

• Only TWO WEEKS until our final project presentation class meeting

• December 12th is the last class meeting

• We will start class on December 12th at 6:30 PM ET in 53 Church Street, Room L01

• Each student needs to create a ten minute video with audio narration that presents their architecture; demonstrates their assembler, emulator, and assembly programs; shows their hardware working with all interesting programs (including the required program); shows their special feature

MIF File Endian Order

• The order of bytes in the MIF File is little endian

• This is the same byte ordering that our memory subsystem presents

• That is, given a MIF file that contains the following line:0000: 0102

the byte at address 0x0000 will be set to 0x02 and

the byte at address 0x0001 will be set to 0x01

Kinds of Memory

• Physical• Punch Cards• Printed

• Magnetic• Tape• Drum• Disk• Magnetic Core

• Optical• CD/DVD/Blu-Ray

• Semiconductor• Static• Dynamic

• Uses capacitive charge

• Flash

Details of Magnetic Core Memory

• Utilizes ferrite cores• A core is a toroid• Ferrite exhibits hysteresis

• Right-hand rule

• Hysteresis• ½ of the required current will not change magnetic state• Magnetic state is non-volatile

• Wiring of a single core: X wires, Y wires, Sense wire “S”,Inhibit wire “Z”• Sense wire is for reading• Inhibit wire is to inhibit action in some planes

• Reading is Destructive• Read data must be written back after reading

Show and Tell

• Three planes of old core memory

• Un-patterned wafer

• Patterned wafer

• Diced chip

• Bonded chip in DIP carrier


• Cover new slides• Custom VLSI Design

• Continuing with PLA implementation


• Massively Parallel Processors (incl. GPUs)

Fifteenth Class Meeting Agenda – 12/5/2017


• Questions

• Administrivia

• New Material

Questions

• Questions?• Final Project

• VLSI

• Data Flow

• Anything else

Problem Set 6



• Problem Set 6 was due this past Sunday, December 3, 2017

Final Project Presentation (1 of 3)

• Only ONE WEEK until our final project presentation class meeting

• Next week on December 12th is the last class meeting

• We will start class on December 12th at 6:30 PM ET in 53 Church Street, Room L01

• Presentation and demonstration

• Each student needs to create an at most ten minute pre-recorded video with audio narration that presents their architecture


• Include slides that describe your processor including• Block diagram• Overview (register configuration, PSW, etc.)• Clocking scheme• Sequencing logic• Interesting design aspects of your logic• Your instruction set• Assembler directives/pseudo-instructions• Emulator features

• Demonstrate your assembler, emulator, and assembly programs

• Demonstrate your hardware working with all interesting programs (including the required program)

• Demonstrate your special feature

• Additional programs that your have running on your processor


• Send the URL for your at most ten minute pre-recorded video to the course staff by 4 PM ET on the day of the presentations

• If you are not attending the final presentation class in person, please send the course staff your Google Hangouts and Skype contact information

• Please remember to be available for a five minute Q&A session after your ten minute video

Final Project Submission

• You have some extra time after your final project presentation to make your final submission/check-in

• Be sure to clean up your code, finalize your documents, add comments to your code, and fix any last minute bugs

• Use git tag term-project

• Your final submission must be made by 2 PM on Friday, December 15th Eastern Time

Contents of Final Project Submission

• Slides used during your presentation

• Overview of the processor

• Up-to-date copy of the processor block diagram

• Up-to-date copy of your processor’s instruction set (i.e., your Principles of Operation manual)

• VHDL code for the complete design

• Current copy of the source code for your assembler

• Current copy of the source code for your emulator

• Documented sample programs for your processor

Return of Hardware

• All borrowed hardware (including the box, static bag, etc.) should be returned in the last class meeting next week

• If you want to keep your hardware for the final code due date, then you must return your hardware in the Harvard Science Center, Room 101e on Friday, December 15th between 6 PM and 8 PM ET or make arrangements in advance of December 15th

Final Presentation Slot Sign-Up List (1 of 2)

• Slot 1, 6:30 PM ET-6:45 PM ET:

• Slot 2, 6:45 PM ET-7:00 PM ET:

• Slot 3, 7:00 PM ET-7:15 PM ET:

• Slot 4, 7:15 PM ET-7:30 PM ET:

• Slot 5, 7:30 PM ET-7:45 PM ET:

• Slot 6, 7:45 PM ET-8:00 PM ET:

• Slot 7, 8:00 PM ET-8:15 PM ET:

• Slot 8, 8:15 PM ET-8:30 PM ET:

Final Presentation Slot Sign-Up List (2 of 2)

• Slot 9, 8:30 PM ET-8:45 PM ET:

• Slot 10, 8:45 PM ET-9:00 PM ET:

• Slot 11, 9:00 PM ET-9:15 PM ET:

• Slot 12, 9:15 PM ET-9:30 PM ET:

• Slot 13, 9:30 PM ET-9:45 PM ET:

• Slot 14, 9:45 PM ET-10:00 PM ET:

• Slot 15, 10:00 PM ET-10:15 PM ET:

• Slot 16, 10:15 PM ET-10:30 PM ET:

Dinner at the Border Café after Presentations

• A significant other is invited to join us after class next week

Ski Trip in January (1 of 2)

• We will go to Killington Resort in Vermont

• Meet in Lexington, MA to depart at 7 AM ET (or at Alewife at 6:30 AM ET)

• Meet on the mountain for lunch

• Stop for dinner on the way home

• Return to Lexington at about 10 PM ET

• A significant other is invited to join us

• Proposed date is Sunday, January 21, 2017

• There is a special Learn-To-Ski/Ride promotion in January (not available 1/1 & 1/13-14)

• See http://www.killington.com/site/to-do/snow-sports-school/special_offers

• $49, but only five per day; if interested, reserve now!

http://www.killington.com/site/to-do/snow-sports-school/special_offers

Ski Trip in January (2 of 2)

• I will follow-up with an e-mail to make arrangements for cars, etc.

CSCI E-95: Compiler Design and Implementation• Spring 2018

• First class meeting is on January 23, 2018

• Class overview


• Flynn’s Taxonomy of Processors

• Networks• Point-to-Point Connection• Bus• Token Ring• Hypercube• Fat Tree

• VLIW Processors

• Superscalar Processors

• RISC vs. CISC

• Mapping a high-level language onto an instruction set

CSCI E-93, Fall 2017: Computer Architecture Agendasites.fas.harvard.edu/~cscie287/fall2017/Class...

Documents

Transcript of CSCI E-93, Fall 2017: Computer Architecture Agendasites.fas.harvard.edu/~cscie287/fall2017/Class...