23.03.20 13:52CSCI 150 Introduction to Digital and Computer

System Design Lecture 5: Registers I

Jetic Gū2020 Winter Semester (S1)

Overview• Focus: Fundamentals of Complex Digital Circuit Design

• Architecture: von Neumann

• Textbook v4: Ch7 7.1 7.2; v5: Ch6 6.1 6.2

• Core Ideas:

1. What are Registers

2. Register Transferring Operations and Circuit

Sequential Circuits

Review

P0 Review

• Synchronous Sequential Circuit Signals arrive at discrete instants of time, outputs at next time step

• Has Clock

• Asynchronous Sequential Circuit Signals arrive at any instant of time, outputs when ready

• May not have Clock

Your Favourite Combinational

Circuit

n mInputs Outputs

Storage Unit

Statet + 1Statet

Clock

200 CHAPTER 4 / SEQUENTIAL CIRCUITS

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as inputs for storage elements are called clocked sequential circuits. These are the types of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design.

The storage elements used in the simplest form of clocked sequential circuits are called flip- flops. For simplicity, assume circuits with a single clock signal. A flip- flop is a binary storage device capable of storing one bit of information and hav-ing timing characteristics to be defined in Section 4-9. The block diagram of a syn-chronous clocked sequential circuit is shown in Figure 4-3. The flip- flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram. The flip- flops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the flip- flop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the figure between the combinational logic and the flip- flops are broken. As a result, a transition from one state to the other occurs only at fixed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the flip- flop outputs. In this case, the combinational circuit part between the flip- flop outputs and the sequential circuit outputs consists of connections only.

A flip- flop has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary informa-tion can enter a flip- flop in a variety of ways, a fact that gives rise to different types of flip- flops. Our focus will be on the most prevalent type used today, the D flip- flop. Other flip- flop types, such as the JK and T flip- flops, are described in the online mate-rial available at the Companion Website. In preparation for studying flip- flops and their operation, necessary groundwork is presented in the next section on latches, from which the flip- flops are constructed.

(b) Timing diagram of clock pulses

(a) Block diagram

Inputs Combinationalcircuit

Clock pulses

Outputs

Flip-flops

FIGURE 4-3Synchronous Clocked Sequential Circuit

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM

What are Registers?

Summary

P1 Registers

Definitions;Register Loading; Parallel Loading

CPU

Computer

Review

P1 Registers

1. Von Neumann Architecture

Input/Output devices

Control Unit

Datapath

Memory

also called arithmetic unit, logical unit, etc.

Clock

200 CHAPTER 4 / SEQUENTIAL CIRCUITS

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as inputs for storage elements are called clocked sequential circuits. These are the types of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design.

The storage elements used in the simplest form of clocked sequential circuits are called flip- flops. For simplicity, assume circuits with a single clock signal. A flip- flop is a binary storage device capable of storing one bit of information and hav-ing timing characteristics to be defined in Section 4-9. The block diagram of a syn-chronous clocked sequential circuit is shown in Figure 4-3. The flip- flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram. The flip- flops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the flip- flop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the figure between the combinational logic and the flip- flops are broken. As a result, a transition from one state to the other occurs only at fixed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the flip- flop outputs. In this case, the combinational circuit part between the flip- flop outputs and the sequential circuit outputs consists of connections only.

A flip- flop has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary informa-tion can enter a flip- flop in a variety of ways, a fact that gives rise to different types of flip- flops. Our focus will be on the most prevalent type used today, the D flip- flop. Other flip- flop types, such as the JK and T flip- flops, are described in the online mate-rial available at the Companion Website. In preparation for studying flip- flops and their operation, necessary groundwork is presented in the next section on latches, from which the flip- flops are constructed.

(b) Timing diagram of clock pulses

(a) Block diagram

Inputs Combinationalcircuit

Clock pulses

Outputs

Flip-flops

FIGURE 4-3Synchronous Clocked Sequential Circuit

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM

CPU

Computer

Review

P1 Registers

1. Von Neumann Architecture

Input/Output devices

Control Unit

Datapath

Memory

also called arithmetic unit, logical unit, etc.

A very rough example

Clock

200 CHAPTER 4 / SEQUENTIAL CIRCUITS

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as inputs for storage elements are called clocked sequential circuits. These are the types of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design.

The storage elements used in the simplest form of clocked sequential circuits are called flip- flops. For simplicity, assume circuits with a single clock signal. A flip- flop is a binary storage device capable of storing one bit of information and hav-ing timing characteristics to be defined in Section 4-9. The block diagram of a syn-chronous clocked sequential circuit is shown in Figure 4-3. The flip- flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram. The flip- flops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the flip- flop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the figure between the combinational logic and the flip- flops are broken. As a result, a transition from one state to the other occurs only at fixed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the flip- flop outputs. In this case, the combinational circuit part between the flip- flop outputs and the sequential circuit outputs consists of connections only.

A flip- flop has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary informa-tion can enter a flip- flop in a variety of ways, a fact that gives rise to different types of flip- flops. Our focus will be on the most prevalent type used today, the D flip- flop. Other flip- flop types, such as the JK and T flip- flops, are described in the online mate-rial available at the Companion Website. In preparation for studying flip- flops and their operation, necessary groundwork is presented in the next section on latches, from which the flip- flops are constructed.

(b) Timing diagram of clock pulses

(a) Block diagram

Inputs Combinationalcircuit

Clock pulses

Outputs

Flip-flops

FIGURE 4-3Synchronous Clocked Sequential Circuit

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM

CPU

Computer

Review

P1 Registers

1. Von Neumann Architecture

Input/Output devices

Control Unit

Datapath

Memory

also called arithmetic unit, logical unit, etc.

Calculate 1+1: X1: 1 (00010001) X2: 1 (00100001) X3: X1+X2 (01110110)

A very rough example

Clock

200 CHAPTER 4 / SEQUENTIAL CIRCUITS

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as inputs for storage elements are called clocked sequential circuits. These are the types of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design.

The storage elements used in the simplest form of clocked sequential circuits are called flip- flops. For simplicity, assume circuits with a single clock signal. A flip- flop is a binary storage device capable of storing one bit of information and hav-ing timing characteristics to be defined in Section 4-9. The block diagram of a syn-chronous clocked sequential circuit is shown in Figure 4-3. The flip- flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram. The flip- flops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the flip- flop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the figure between the combinational logic and the flip- flops are broken. As a result, a transition from one state to the other occurs only at fixed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the flip- flop outputs. In this case, the combinational circuit part between the flip- flop outputs and the sequential circuit outputs consists of connections only.

A flip- flop has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary informa-tion can enter a flip- flop in a variety of ways, a fact that gives rise to different types of flip- flops. Our focus will be on the most prevalent type used today, the D flip- flop. Other flip- flop types, such as the JK and T flip- flops, are described in the online mate-rial available at the Companion Website. In preparation for studying flip- flops and their operation, necessary groundwork is presented in the next section on latches, from which the flip- flops are constructed.

(b) Timing diagram of clock pulses

(a) Block diagram

Inputs Combinationalcircuit

Clock pulses

Outputs

Flip-flops

FIGURE 4-3Synchronous Clocked Sequential Circuit

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM

CPU

Computer

Review

P1 Registers

1. Von Neumann Architecture

Input/Output devices

Control Unit

Datapath

Memory

also called arithmetic unit, logical unit, etc.

Calculate 1+1: X1: 1 (00010001) X2: 1 (00100001) X3: X1+X2 (01110110)

M1: 1 (00000001)

CPU exe.

A very rough example

Clock

200 CHAPTER 4 / SEQUENTIAL CIRCUITS

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as inputs for storage elements are called clocked sequential circuits. These are the types of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design.

The storage elements used in the simplest form of clocked sequential circuits are called flip- flops. For simplicity, assume circuits with a single clock signal. A flip- flop is a binary storage device capable of storing one bit of information and hav-ing timing characteristics to be defined in Section 4-9. The block diagram of a syn-chronous clocked sequential circuit is shown in Figure 4-3. The flip- flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram. The flip- flops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the flip- flop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the figure between the combinational logic and the flip- flops are broken. As a result, a transition from one state to the other occurs only at fixed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the flip- flop outputs. In this case, the combinational circuit part between the flip- flop outputs and the sequential circuit outputs consists of connections only.

A flip- flop has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary informa-tion can enter a flip- flop in a variety of ways, a fact that gives rise to different types of flip- flops. Our focus will be on the most prevalent type used today, the D flip- flop. Other flip- flop types, such as the JK and T flip- flops, are described in the online mate-rial available at the Companion Website. In preparation for studying flip- flops and their operation, necessary groundwork is presented in the next section on latches, from which the flip- flops are constructed.

(b) Timing diagram of clock pulses

(a) Block diagram

Inputs Combinationalcircuit

Clock pulses

Outputs

Flip-flops

FIGURE 4-3Synchronous Clocked Sequential Circuit

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM

T1

T1

CPU

Computer

Review

P1 Registers

1. Von Neumann Architecture

Input/Output devices

Control Unit

Datapath

Memory

also called arithmetic unit, logical unit, etc.

Calculate 1+1: X1: 1 (00010001) X2: 1 (00100001) X3: X1+X2 (01110110)

M1: 1 (00000001)

CPU exe.M2: 1 (00000001)

A very rough example

Clock

200 CHAPTER 4 / SEQUENTIAL CIRCUITS

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as inputs for storage elements are called clocked sequential circuits. These are the types of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design.

The storage elements used in the simplest form of clocked sequential circuits are called flip- flops. For simplicity, assume circuits with a single clock signal. A flip- flop is a binary storage device capable of storing one bit of information and hav-ing timing characteristics to be defined in Section 4-9. The block diagram of a syn-chronous clocked sequential circuit is shown in Figure 4-3. The flip- flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram. The flip- flops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the flip- flop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the figure between the combinational logic and the flip- flops are broken. As a result, a transition from one state to the other occurs only at fixed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the flip- flop outputs. In this case, the combinational circuit part between the flip- flop outputs and the sequential circuit outputs consists of connections only.

A flip- flop has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary informa-tion can enter a flip- flop in a variety of ways, a fact that gives rise to different types of flip- flops. Our focus will be on the most prevalent type used today, the D flip- flop. Other flip- flop types, such as the JK and T flip- flops, are described in the online mate-rial available at the Companion Website. In preparation for studying flip- flops and their operation, necessary groundwork is presented in the next section on latches, from which the flip- flops are constructed.

(b) Timing diagram of clock pulses

(a) Block diagram

Inputs Combinationalcircuit

Clock pulses

Outputs

Flip-flops

FIGURE 4-3Synchronous Clocked Sequential Circuit

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM

T1T2

T1 T2

CPU

Computer

Review

P1 Registers

1. Von Neumann Architecture

Input/Output devices

Control Unit

Datapath

Memory

also called arithmetic unit, logical unit, etc.

Calculate 1+1: X1: 1 (00010001) X2: 1 (00100001) X3: X1+X2 (01110110)

M1: 1 (00000001)

1+1=2

CPU exe.

M2: 1 (00000001)

A very rough example

Clock

200 CHAPTER 4 / SEQUENTIAL CIRCUITS

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as inputs for storage elements are called clocked sequential circuits. These are the types of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design.

The storage elements used in the simplest form of clocked sequential circuits are called flip- flops. For simplicity, assume circuits with a single clock signal. A flip- flop is a binary storage device capable of storing one bit of information and hav-ing timing characteristics to be defined in Section 4-9. The block diagram of a syn-chronous clocked sequential circuit is shown in Figure 4-3. The flip- flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram. The flip- flops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the flip- flop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the figure between the combinational logic and the flip- flops are broken. As a result, a transition from one state to the other occurs only at fixed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the flip- flop outputs. In this case, the combinational circuit part between the flip- flop outputs and the sequential circuit outputs consists of connections only.

A flip- flop has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary informa-tion can enter a flip- flop in a variety of ways, a fact that gives rise to different types of flip- flops. Our focus will be on the most prevalent type used today, the D flip- flop. Other flip- flop types, such as the JK and T flip- flops, are described in the online mate-rial available at the Companion Website. In preparation for studying flip- flops and their operation, necessary groundwork is presented in the next section on latches, from which the flip- flops are constructed.

(b) Timing diagram of clock pulses

(a) Block diagram

Inputs Combinationalcircuit

Clock pulses

Outputs

Flip-flops

FIGURE 4-3Synchronous Clocked Sequential Circuit

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM

T1T2T3

T1 T2 T3

CPU

Computer

Review

P1 Registers

1. Von Neumann Architecture

Input/Output devices

Control Unit

Datapath

Memory

also called arithmetic unit, logical unit, etc.

Calculate 1+1: X1: 1 (00010001) X2: 1 (00100001) X3: X1+X2 (01110110)

M1: 1 (00000001)

1+1=2

M3: 2 (00000010)CPU exe.

M2: 1 (00000001)

A very rough example

Clock

200 CHAPTER 4 / SEQUENTIAL CIRCUITS

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as inputs for storage elements are called clocked sequential circuits. These are the types of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design.

The storage elements used in the simplest form of clocked sequential circuits are called flip- flops. For simplicity, assume circuits with a single clock signal. A flip- flop is a binary storage device capable of storing one bit of information and hav-ing timing characteristics to be defined in Section 4-9. The block diagram of a syn-chronous clocked sequential circuit is shown in Figure 4-3. The flip- flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram. The flip- flops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the flip- flop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the figure between the combinational logic and the flip- flops are broken. As a result, a transition from one state to the other occurs only at fixed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the flip- flop outputs. In this case, the combinational circuit part between the flip- flop outputs and the sequential circuit outputs consists of connections only.

A flip- flop has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary informa-tion can enter a flip- flop in a variety of ways, a fact that gives rise to different types of flip- flops. Our focus will be on the most prevalent type used today, the D flip- flop. Other flip- flop types, such as the JK and T flip- flops, are described in the online mate-rial available at the Companion Website. In preparation for studying flip- flops and their operation, necessary groundwork is presented in the next section on latches, from which the flip- flops are constructed.

(b) Timing diagram of clock pulses

(a) Block diagram

Inputs Combinationalcircuit

Clock pulses

Outputs

Flip-flops

FIGURE 4-3Synchronous Clocked Sequential Circuit

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM

T1T2T3

T1 T2 T3

von Neumann CPU• Control Unit

• Determine sequence of data-processing operations performed by the datapath

• Datapath

• Processing logic units: Adder, Subtractor, Shifter, Counter, etc.

• Registers: Storage of temporary information, basic components of the digital system

Concep

t

P1 Registers

• � -bit register: uses � flip-flopsstores � bits of informationn n

n

Register

Concep

t

P1 Registers

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

Register

Concep

t

P1 Registers

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

• An array of � flip-flops withreset

D

• � -bit register: uses � flip-flopsstores � bits of informationn n

n

Register

Concep

t

P1 Registers

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

• An array of � flip-flops withreset

D

• � -bit register: uses � flip-flopsstores � bits of informationn n

n

• Clear: set register to all � s0

Register

Concep

t

P1 Registers

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

• An array of � flip-flops withreset

D

• � -bit register: uses � flip-flopsstores � bits of informationn n

n

• Clear: set register to all � s0

• Loading: set register to �D3:0

Clock

Register

Concep

t

P1 Registers

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

• An array of � flip-flops withreset

D

• � -bit register: uses � flip-flopsstores � bits of informationn n

n

• Clear: set register to all � s0

• Loading: set register to �D3:0Triggered by Load or Clock

Clock

Register Operations

• All registers are most likely wired to one Clock

• Loading a register: assigning new values to all � -bits of a register

• Clearing a register: change all � -bits of a register to � s

n

n 0

Concep

t

P1 Registers

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

Clock

What if we don’t want to change the value of a register?

Concep

t

P1 Registers

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

What if we don’t want to change the value of a register?

• Clock: generates a constant train of pulsestriggering the C of each registers

Concep

t

P1 Registers

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

What if we don’t want to change the value of a register?

• Clock: generates a constant train of pulsestriggering the C of each registers

• Clock gating (Bad Idea)

Concep

t

P1 Registers

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

What if we don’t want to change the value of a register?

• Clock: generates a constant train of pulsestriggering the C of each registers

• Clock gating (Bad Idea)

• Adding an Enabler to each C of each register

Concep

t

P1 Registers

En

CLK

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

What if we don’t want to change the value of a register?

• Clock: generates a constant train of pulsestriggering the C of each registers

• Clock gating (Bad Idea)

• Adding an Enabler to each C of each register

• Bad idea: leads to different propagation delay between the CLK and the Input D

Concep

t

P1 Registers

En

CLK

6-1 / Registers and Load Enable 325

Register with Parallel Load

Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all flip-flops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

(d) Timing diagram

Clock

Load

C inputs

(b) Symbol

REG

Clear

D0 Q0

D2 Q2

D3 Q3

D1 Q1

(c) Load control input

C inputs (clock inputsof flip-flops)

LoadClock

(a) Logic diagram

D

C

R

D

C

R

D

C

D

C

R

R

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

FIGURE 6-14-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM

What if we don’t want to change the value of a register?

• Clock: generates a constant train of pulsestriggering the C of each registers

• Use � flip-flops with built-in Enabler (Correct!)

• The CLK goes directly to C

• Input � combined with � signalEnsure same propagation delay design

D

D EN

Concep

t

P1 Registers

6-2 / Register Transfers 327

done simultaneously for all four bits during a single positive pulse transition. This method of transfer is traditionally preferred over clock gating, since it avoids clock skew and the potential for malfunctions of the circuit.

6-2 REGISTER TRANSFERS

A digital system is a sequential circuit made up of interconnected flip-flops and gates. In Chapter 4, we learned that sequential circuits can be specified by means of state tables. To specify a large digital system with state tables is very difficult, if not impos-sible, because the number of states is prohibitively large. To overcome this difficulty, digital systems are designed using a modular, hierarchical approach. The system is partitioned into subsystems or modules, each of which performs some functional task. The modules are constructed hierarchically from functional blocks such as reg-isters, counters, decoders, multiplexers, buses, arithmetic elements, flip-flops, and primitive gates. The various subsystems communicate with data and control signals to form a digital system.

In most digital system designs, we partition the system into two types of mod-ules: a datapath, which performs data-processing operations, and a control unit,

D

CEN

(b)(a)

D

CD Flip-flop with enable

ENDC

Q

(c)

D

CEN

D

CEN

D

CEN

D

CEN

Q0

Q1

Q2D2

D1

D0

Q3D3Load

Clock

FIGURE 6-24-Bit Register with Parallel Load

M06_MANO0637_05_SE_C06.indd 327 21/01/15 9:49 AM

What if we don’t want to change the value of a register?

• Clock: generates a constant train of pulsestriggering the C of each registers

• Use � flip-flops with built-in Enabler (Correct!)

• The CLK goes directly to C

• Input � combined with � signalEnsure same propagation delay design

D

D EN

Concep

t

P1 Registers

6-2 / Register Transfers 327

done simultaneously for all four bits during a single positive pulse transition. This method of transfer is traditionally preferred over clock gating, since it avoids clock skew and the potential for malfunctions of the circuit.

6-2 REGISTER TRANSFERS

A digital system is a sequential circuit made up of interconnected flip-flops and gates. In Chapter 4, we learned that sequential circuits can be specified by means of state tables. To specify a large digital system with state tables is very difficult, if not impos-sible, because the number of states is prohibitively large. To overcome this difficulty, digital systems are designed using a modular, hierarchical approach. The system is partitioned into subsystems or modules, each of which performs some functional task. The modules are constructed hierarchically from functional blocks such as reg-isters, counters, decoders, multiplexers, buses, arithmetic elements, flip-flops, and primitive gates. The various subsystems communicate with data and control signals to form a digital system.

In most digital system designs, we partition the system into two types of mod-ules: a datapath, which performs data-processing operations, and a control unit,

D

CEN

(b)(a)

D

CD Flip-flop with enable

ENDC

Q

(c)

D

CEN

D

CEN

D

CEN

D

CEN

Q0

Q1

Q2D2

D1

D0

Q3D3Load

Clock

FIGURE 6-24-Bit Register with Parallel Load

M06_MANO0637_05_SE_C06.indd 327 21/01/15 9:49 AM

6-2 / Register Transfers 327

done simultaneously for all four bits during a single positive pulse transition. This method of transfer is traditionally preferred over clock gating, since it avoids clock skew and the potential for malfunctions of the circuit.

6-2 REGISTER TRANSFERS

A digital system is a sequential circuit made up of interconnected flip-flops and gates. In Chapter 4, we learned that sequential circuits can be specified by means of state tables. To specify a large digital system with state tables is very difficult, if not impos-sible, because the number of states is prohibitively large. To overcome this difficulty, digital systems are designed using a modular, hierarchical approach. The system is partitioned into subsystems or modules, each of which performs some functional task. The modules are constructed hierarchically from functional blocks such as reg-isters, counters, decoders, multiplexers, buses, arithmetic elements, flip-flops, and primitive gates. The various subsystems communicate with data and control signals to form a digital system.

In most digital system designs, we partition the system into two types of mod-ules: a datapath, which performs data-processing operations, and a control unit,

D

CEN

(b)(a)

D

CD Flip-flop with enable

ENDC

Q

(c)

D

CEN

D

CEN

D

CEN

D

CEN

Q0

Q1

Q2D2

D1

D0

Q3D3Load

Clock

FIGURE 6-24-Bit Register with Parallel Load

M06_MANO0637_05_SE_C06.indd 327 21/01/15 9:49 AM

What if we don’t want to change the value of a register?

• Clock: generates a constant train of pulsestriggering the C of each registers

• Use � flip-flops with built-in Enabler (Correct!)

• The CLK goes directly to C

• Input � combined with � signalEnsure same propagation delay design

D

D EN

Concep

t

P1 Registers

6-2 / Register Transfers 327

done simultaneously for all four bits during a single positive pulse transition. This method of transfer is traditionally preferred over clock gating, since it avoids clock skew and the potential for malfunctions of the circuit.

6-2 REGISTER TRANSFERS

A digital system is a sequential circuit made up of interconnected flip-flops and gates. In Chapter 4, we learned that sequential circuits can be specified by means of state tables. To specify a large digital system with state tables is very difficult, if not impos-sible, because the number of states is prohibitively large. To overcome this difficulty, digital systems are designed using a modular, hierarchical approach. The system is partitioned into subsystems or modules, each of which performs some functional task. The modules are constructed hierarchically from functional blocks such as reg-isters, counters, decoders, multiplexers, buses, arithmetic elements, flip-flops, and primitive gates. The various subsystems communicate with data and control signals to form a digital system.

In most digital system designs, we partition the system into two types of mod-ules: a datapath, which performs data-processing operations, and a control unit,

D

CEN

(b)(a)

D

CD Flip-flop with enable

ENDC

Q

(c)

D

CEN

D

CEN

D

CEN

D

CEN

Q0

Q1

Q2D2

D1

D0

Q3D3Load

Clock

FIGURE 6-24-Bit Register with Parallel Load

M06_MANO0637_05_SE_C06.indd 327 21/01/15 9:49 AM

6-2 / Register Transfers 327

done simultaneously for all four bits during a single positive pulse transition. This method of transfer is traditionally preferred over clock gating, since it avoids clock skew and the potential for malfunctions of the circuit.

6-2 REGISTER TRANSFERS

A digital system is a sequential circuit made up of interconnected flip-flops and gates. In Chapter 4, we learned that sequential circuits can be specified by means of state tables. To specify a large digital system with state tables is very difficult, if not impos-sible, because the number of states is prohibitively large. To overcome this difficulty, digital systems are designed using a modular, hierarchical approach. The system is partitioned into subsystems or modules, each of which performs some functional task. The modules are constructed hierarchically from functional blocks such as reg-isters, counters, decoders, multiplexers, buses, arithmetic elements, flip-flops, and primitive gates. The various subsystems communicate with data and control signals to form a digital system.

In most digital system designs, we partition the system into two types of mod-ules: a datapath, which performs data-processing operations, and a control unit,

D

CEN

(b)(a)

D

CD Flip-flop with enable

ENDC

Q

(c)

D

CEN

D

CEN

D

CEN

D

CEN

Q0

Q1

Q2D2

D1

D0

Q3D3Load

Clock

FIGURE 6-24-Bit Register with Parallel Load

M06_MANO0637_05_SE_C06.indd 327 21/01/15 9:49 AM

Why can’t we use a regular enabler at � ?D

Registers

• What is a register?

• Basic Functions of a single Register

• Loading: set values to input

• Clearing: set values to �

• Enabling: preserving existing values

0

Review

P1 Registers

x86 Registers

Summary

P2 Example

And how addition is performed on your Computer CPU

Common CPU Processor Architectures

• These are all von Neumann architecture designs

• X86 architecture (Intel CPUs, AMD CPUs)

• X86-64 architecture (64bit version of X86)

• ARM (iPhone, iPad, most Android devices)

• MIPS (Others, including instructional)

Concep

t

P2 Example

Intel 8086 CPU

8 GPRs, 6 Seg Regs, 1 Flag Reg, 1 Instruc. Reg

X86 CPU Registers• These registers are located on the CPU chips (in Datapath)

• 8 General-Purpose Registers (GPRs)

• AX: Accumulator register. Used in arithmetic operations

• BX: Base register. Used as a pointer to data

• CX: Counter register. Used in shift/rotate instructions and loops.

• DX: Data register. Used in arithmetic operations and I/O operations.

• ……

Concep

t

P2 Example

REG AXQ

DREG BX

QD

REG CXQ

DREG DX

QD

……

• 12 + 35

• Uses AX, BX: Cleared to 0

1. Load AX with 12

2. Load BX with 35

3. Perform addition with Adder-Subtractor, store result in AX

X86 Addition

Demo

P2 Example

Assembly Language

REG AXQ

D

REG BXQ

D

0000h

Adder-Subtractor

0000h

Hardware

• 12 + 35

• Uses AX, BX: Cleared to 0

1. Load AX with 12

2. Load BX with 35

3. Perform addition with Adder-Subtractor, store result in AX

X86 Addition

Demo

P2 Example

Assembly Language

MOV AX, 000Ch

REG AXQ

D

REG BXQ

D

0000h000Ch

000Ch

Adder-Subtractor

0000h

1. Load AX with 12 (000Ch)

Hardware

• 12 + 35

• Uses AX, BX: Cleared to 0

1. Load AX with 12

2. Load BX with 35

3. Perform addition with Adder-Subtractor, store result in AX

X86 Addition

Demo

P2 Example

Assembly Language

MOV AX, 000Ch

MOV BX, 0023h

REG AXQ

D

REG BXQ

D

0000h000Ch

000Ch

Adder-Subtractor

0000h0023h

0023h

1. Load AX with 12 (000Ch)

2. Load BX with 35 (0023h)

Hardware

• 12 + 35

• Uses AX, BX: Cleared to 0

1. Load AX with 12

2. Load BX with 35

3. Perform addition with Adder-Subtractor, store result in AX

X86 Addition

Demo

P2 Example

Assembly Language

MOV AX, 000Ch

MOV BX, 0023h

ADD AX, BX

REG AXQ

D

REG BXQ

D

0000h000Ch

000Ch

Adder-Subtractor

002Fh

002Fh002Fh

0000h0023h

0023h

1. Load AX with 12 (000Ch)

2. Load BX with 35 (0023h)

3. Perform Add with Adder-Subtractor, Load result to AX

Hardware

Datapath and Control Unit

Concep

t

P2 Example

• Control Unit at each time step, provide

• Operation Codee.g. mov (66b8, etc.), add (6601, etc.)

• Parameterse.g. ax, bx, 12, 35

• Datapath

• Select Register for Input and Output (Multiplexer)

• Feed input into Register or Functional Blocks (Adder-Subtractor)

Datapath

Datapath and Control Unit

Concep

t

P2 Example

Adder-Subtractor

(ALU)

Control Unit (CU)

Register Array (Reg)

REG AXQ

DREG BX

QD

REG CXQ

DREG DX

QD

……

Red: AddressGreen: Mode

Datapath

Datapath and Control Unit1. ALU connected to Reg for 1st input

Concep

t

P2 Example

Adder-Subtractor

(ALU)

Control Unit (CU)

Register Array (Reg)

REG AXQ

DREG BX

QD

REG CXQ

DREG DX

QD

……

1

Red: AddressGreen: Mode

Datapath

Datapath and Control Unit1. ALU connected to Reg for 1st input

2. ALU connected to Reg for 2nd input

Concep

t

P2 Example

Adder-Subtractor

(ALU)

Control Unit (CU)

Register Array (Reg)

REG AXQ

DREG BX

QD

REG CXQ

DREG DX

QD

……

1

2

Red: AddressGreen: Mode

Datapath

Datapath and Control Unit1. ALU connected to Reg for 1st input

2. ALU connected to Reg for 2nd input

3. ALU connected to Reg to store result

Concep

t

P2 Example

Adder-Subtractor

(ALU)

Control Unit (CU)

Register Array (Reg)

REG AXQ

DREG BX

QD

REG CXQ

DREG DX

QD

……

1

2

3

Red: AddressGreen: Mode

Datapath

Datapath and Control Unit1. ALU connected to Reg for 1st input

2. ALU connected to Reg for 2nd input

3. ALU connected to Reg to store result

4. CU tells ALU which register to take as 1st input

Concep

t

P2 Example

Adder-Subtractor

(ALU)

Control Unit (CU)

Register Array (Reg)

REG AXQ

DREG BX

QD

REG CXQ

DREG DX

QD

……

1

2

4

3

Red: AddressGreen: Mode

Datapath

Datapath and Control Unit1. ALU connected to Reg for 1st input

2. ALU connected to Reg for 2nd input

3. ALU connected to Reg to store result

4. CU tells ALU which register to take as 1st input

5. CU tells ALU which register to take as 2st input

Concep

t

P2 Example

Adder-Subtractor

(ALU)

Control Unit (CU)

Register Array (Reg)

REG AXQ

DREG BX

QD

REG CXQ

DREG DX

QD

……

1

2

45

3

Red: AddressGreen: Mode

Datapath

Datapath and Control Unit1. ALU connected to Reg for 1st input

2. ALU connected to Reg for 2nd input

3. ALU connected to Reg to store result

4. CU tells ALU which register to take as 1st input

5. CU tells ALU which register to take as 2st input

6. CU tells ALU which operation to do

Concep

t

P2 Example

Adder-Subtractor

(ALU)

Control Unit (CU)

Register Array (Reg)

REG AXQ

DREG BX

QD

REG CXQ

DREG DX

QD

……

1

2

45

6

3

Red: AddressGreen: Mode

Datapath

Datapath and Control Unit1. ALU connected to Reg for 1st input

2. ALU connected to Reg for 2nd input

3. ALU connected to Reg to store result

4. CU tells ALU which register to take as 1st input

5. CU tells ALU which register to take as 2st input

6. CU tells ALU which operation to do

7. CU tells which Reg to store result inUsing decoder and EN on each Register

Concep

t

P2 Example

Adder-Subtractor

(ALU)

Control Unit (CU)

Register Array (Reg)

REG AXQ

DREG BX

QD

REG CXQ

DREG DX

QD

……

1

2

45

6

3

Red: AddressGreen: Mode

7Dec

Register Transferring

Summary

P3 Transferring

Microoperations; Transferring Operations

Register Operations

• Movement of data stored in registers and Processing performed on the data

• Components

• set of registers in the system

• operations performed on the data

• control that supervises the sequence of operations in the system

Concep

t

P3 Transferring

Microoperation

• Microoperation: An elementary operation performed on data stored in registers

• Single Register (Transfer Operations): load, clear, shift, count, etc.

• Multiple Registers: add, subtract, etc.

Concep

t

P3 Transferring

Register Transfer VHDLP3 Transferring

Concep

t

Operator Example

Assignment <= ax <= 12h

Reg. Transfer <= ax <= bx

Addition + ax + bx

Subtration - ax - bx

Shift Left sll ax sll 2

Shift Right srl ax srl 2

Operator Example

Bitwise AND and ax and bx

Bitwise OR or ax or bx

Bitwise NOT not not ax

Bitwise XOR xor ax xor bx

Vectors ax(3 down to 0) ax(3 down to 0)

Concatenate & ax(7 down to 4) &ax(3 down to 0)

Register Transfer VHDL

Example

P3 Transferring

1) ax <= 12 2) bx <= 18 3) cx <= ax + bx 4) dx <= bx - ax

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

Example

P3 Transferring

1) ax <= 12 2) bx <= 18 3) cx <= ax + bx 4) dx <= bx - ax

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

• Answer:ax: 0000 1100 bx: 0001 0010 cx: 0001 1110 dx: 0000 0110

Example

P3 Transferring

1) ax <= 12 2) bx <= 18 3) cx <= ax + bx 4) dx <= bx - ax

Register Transfer VHDL

Example

P3 Transferring

1) ax <= 12 2) bx <= ax sll 2 3) cx <= ax sll 3 4) dx <= ax srl 1

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

Example

P3 Transferring

1) ax <= 12 2) bx <= ax sll 2 3) cx <= ax sll 3 4) dx <= ax srl 1

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

• Answer:ax: 0000 1100 bx: 0011 0000 cx: 0110 0000 dx: 0000 0110

Example

P3 Transferring

1) ax <= 12 2) bx <= ax sll 2 3) cx <= ax sll 3 4) dx <= ax srl 1

Register Transfer VHDL

Example

P3 Transferring

1) ax <= 12 2) bx <= 20 3) cx <= ax and bx 4) dx <= ax or bx

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

Example

P3 Transferring

1) ax <= 12 2) bx <= 20 3) cx <= ax and bx 4) dx <= ax or bx

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

• Answer:ax: 0000 1100 bx: 0001 0100 cx: 0000 0100 dx: 0001 1100

Example

P3 Transferring

1) ax <= 12 2) bx <= 20 3) cx <= ax and bx 4) dx <= ax or bx

Register Transfer VHDL

Example

P3 Transferring

1) ax <= 12 2) bx <= 20 3) cx <= not ax 4) dx <= ax xor bx

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

Example

P3 Transferring

1) ax <= 12 2) bx <= 20 3) cx <= not ax 4) dx <= ax xor bx

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

• Answer:ax: 0000 1100 bx: 0001 0100 cx: 1111 0011 dx: 0001 1000

Example

P3 Transferring

1) ax <= 12 2) bx <= 20 3) cx <= not ax 4) dx <= ax xor bx

Register Transfer VHDL

Exerci

se

P3 Transferring

1) ax <= 12 2) bx <= 20 3) cx <= ax(5 down to 2) 4) dx <= bx(7 down to 4) 5) bx <= ax(5 down to 2) & bx(7 down to 4)

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

Exerci

se

P3 Transferring

1) ax <= 12 2) bx <= 20 3) cx <= ax(5 down to 2) 4) dx <= bx(7 down to 4) 5) bx <= ax(5 down to 2) & bx(7 down to 4)

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

• Answer:ax: 0000 1100 bx: 0001 0100 cx: 0000 0011 dx: 0000 0001 bx: 0011 0001

Exerci

se

P3 Transferring

1) ax <= 12 2) bx <= 20 3) cx <= ax(5 down to 2) 4) dx <= bx(7 down to 4) 5) bx <= ax(5 down to 2) & bx(7 down to 4)

Register Transfer VHDL

Exerci

se

P3 Transferring

1) ax <= 8 2) bx <= 23 3) cx <= bx(7 down to 4) & a(3 down to 0) 4) dx <= ax(4 down to 1) sll 4

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

Exerci

se

P3 Transferring

1) ax <= 8 2) bx <= 23 3) cx <= bx(7 down to 4) & a(3 down to 0) 4) dx <= ax(4 down to 1) sll 4

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

• Answer:ax: 0000 1000 bx: 0001 0111 cx: 0001 1000 dx: 0100 0000

Exerci

se

P3 Transferring

1) ax <= 8 2) bx <= 23 3) cx <= bx(7 down to 4) & a(3 down to 0) 4) dx <= ax(4 down to 1) sll 4

Register Transfer VHDL

Exerci

se

P3 Transferring

1) ax <= 13 2) bx <= 27 3) cx <= bx srl 2 4) dx <= (ax and bx) xor (not cx)

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

Exerci

se

P3 Transferring

1) ax <= 13 2) bx <= 27 3) cx <= bx srl 2 4) dx <= (ax and bx) xor (not cx)

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

• Answer:ax: 0000 1101 bx: 0001 1011 cx: 0000 0110 dx: 1111 0000

Exerci

se

P3 Transferring

1) ax <= 13 2) bx <= 27 3) cx <= bx srl 2 4) dx <= (ax and bx) xor (not cx)

Register Transfer VHDL

Exerci

se

P3 Transferring

1) ax <= 2Eh 2) bx <= ax(7 down to 4) xor ax(3 down to 0) 3) cx <= (ax slr 2) or (ax sll 1) 4) dx <= bx and cx

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

Exerci

se

P3 Transferring

1) ax <= 2Eh 2) bx <= ax(7 down to 4) xor ax(3 down to 0) 3) cx <= (ax slr 2) or (ax sll 1) 4) dx <= bx and cx

Register Transfer VHDL

• What are the binary values after these operations? (Assuming 8bit registers)

• Answer:ax: 0010 1110 bx: 0000 1100 cx: (0000 1011) or (0101 1100): (0101 1111)dx: 0000 1100

Exerci

se

P3 Transferring

1) ax <= 2Eh 2) bx <= ax(7 down to 4) xor ax(3 down to 0) 3) cx <= (ax slr 2) or (ax sll 1) 4) dx <= bx and cx

Register Transfer Operations

Review

P3 Transferring

Operator Example

Assignment <= ax <= 12h

Reg. Transfer <= ax <= bx

Addition + ax + bx

Subtration - ax - bx

Shift Left sll ax sll 2

Shift Right srl ax srl 2

Operator Example

Bitwise AND and ax and bx

Bitwise OR or ax or bx

Bitwise NOT not ax not bx

Bitwise XOR xor ax xor bx

Vectors ax(3 down to 0) ax(3 down to 0)

Concatenate & ax(7 down to 4) &ax(3 down to 0)