CS8803: Advanced Digital Design for Embedded...

CS8803: Advanced Digital Design for Embedded Hardware

Lecture 6: Behavioral Verilog

Instructor: Sung Kyu Lim ([email protected])

Website: http://users.ece.gatech.edu/limsk/course/cs8803

Copyright 2001, 2003 MD Ciletti 5

Behavioral Models

• Behavioral models are abstract descriptions of functionality.

• Widely used for quick development of model

• Follow by synthesis

• We'll consider two types:

o Continuous assignment (Boolean equations)

o Cyclic behavior (more general, e.g. algorithms)


Example: Abstract Models of Boolean Equations

• Continuous assignments (Keyword: assign) are the Verilog counterpart

of Boolean equations

• Hardware is implicit (i.e. combinational logic)

Example 5.1 (p 145): Revisit the AOI circuit in Figure 4.7

module AOI_5_CA0 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5); input x_in1, x_in2, x_in3, x_in4, x_in5; output y_out; assign y_out = ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5)); endmodule

• The LHS variable is monitored automatically and updates when the RHS

expression changes value


Example 5.2 (p 146)

module AOI_5_CA1 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5, enable); input x_in1, x_in2, x_in3, x_in4, x_in5, enable; output y_out; assign y_out = enable ? ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5)) : 1'bz; endmodule

• The conditional operator (? :) acts like a software if-then-else switch that

selects between two expressions.

• Must provide both expressions


Equivalent circuit:

x_in1x_in2

x_in3x_in4

y_out

x_in5

enable


Example 5.4 (p 148)

module Mux_2_ 32_CA ( mux_out, data_1, data_0, select); parameter word_size = 32; output [word_size -1: 0] mux_out; input [word_size-1: 0] data_1, data_0; input select; assign mux_out = select ? data_1 : data_0; endmodule


Propagation Delay for Continuous Assignments

Example 5.3 (Note: Three-state behavior)

module AOI_5 _CA2 (y_out, x_in1, x_in2, x_in3, x_in4); input x_in1, x_in2, x_in3, x_in4; output y_out; wire #1 y1 = x_in1 & x_in2; // Bitwise and operation wire #1 y2 = x_in3 & x_in_4; wire #1 y_out = ~ (y1 | y2); // Complement the result of bitwise OR operation endmodule


Multiple Continuous Assignments

• Multiple continuous assignments are active concurrently

module compare_2_CA0 (A_lt_B, A_gt_B, A_eq_B, A1, A0, B1, B0); input A1, A0, B1, B0; output A_lt_B, A_gt_B, A_eq_B; assign A_lt_B = (~A1) & B1 | (~A1) & (~A0) & B0 | (~A0) & B1 & B0; assign A_gt_B = A1 & (~B1) | A0 & (~B1) & (~B0) | A1 & A0 & (~B0); assign A_eq_B = (~A1) & (~A0) & (~B1) & (~B0) | (~A1) & A0 & (~B1) & B0

| A1 & A0 & B1 & B0 | A1 & (~A0) & B1 & (~B0); endmodule

• Note: this style can become unwieldy and error-prone


Example 5.13 (Clarity!)

module compare_2_CA1 (A_lt_B, A_gt_B, A_eq_B, A, B); input [1: 0] A, B; output A_lt_B, A_gt_B, A_eq_B; assign A_lt_B = (A < B); // The RHS expression is true (1) or false (0) assign A_gt_B = (A > B); assign A_eq_B = (A == B);

endmodule


Abstract Modeling with Cyclic Behaviors

• Cyclic behaviors assign values to register variables to describe the behavior

of hardware • Model level-sensitive and edge-sensitive behavior

• Synthesis tool selects the hardware

• Note: Cyclic behaviors re-execute after executing the last procedural

statement executes (subject to timing controls – more on this later)


Example 5.9: D-type Flip-Flop (p. 153)

module df_behav (q, q_bar, data, set, reset, clk); input data, set, clk, reset; output q, q_bar; reg q; assign q_bar = ~ q; always @ (posedge clk) // Flip-flop with synchronous set/reset begin if (reset == 0) q


Example: Transparent Latch (Cyclic Behavior)

module tr_latch (q_out, enable, data); output q_out; input enable, data; reg q_out; always @ (enable or data) begin if (enable) q_out = data; end endmodule


Algorithm-Based Models

Example 5.18

module compare_2_algo (A_lt_B, A_gt_B, A_eq_B, A, B); output A_lt_B, A_gt_B, A_eq_B; input [1: 0] A, B; reg A_lt_B, A_gt_B, A_eq_B; always @ (A or B) // Level-sensitive behavior begin A_lt_B = 0; A_gt_B = 0; A_eq_B = 0; if (A == B) A_eq_B = 1; // Note: parentheses are required else if (A > B) A_gt_B = 1; else A_lt_B = 1; end

endmodule


Result of synthesis:

A

A_lt_B

A_eq_B

A_gt_B

B B

B

A

A


Example 5.19: Four-Channel Mux with Three-State Output


module Mux_4_32_case (mux_out, data_3, data_2, data_1, data_0, select, enable); output [31: 0] mux_out; input [31: 0] data_3, data_2, data_1, data_0; input [1: 0] select; input enable; reg [31: 0] mux_int; assign mux_out = enable ? mux_int : 32'bz; always @ ( data_3 or data_2 or data_1 or data_0 or select) case (select) 0: mux_int = data_0; 1: mux_int = data_1; 2: mux_int = data_2; 3: mux_int = data_3; default: mux_int = 32'bx; // May execute in simulation endcase endmodule


Example 5.23: Priority Encoder

module priority (Code, valid_data, Data); output [2: 0] Code; output valid_data; input [7: 0] Data; reg [2: 0] Code; assign valid_data = |Data; // "reduction or" operator always @ (Data) begin if (Data[7]) Code = 7; else if (Data[6]) Code = 6; else if (Data[5]) Code = 5; else if (Data[4]) Code = 4; else if (Data[3]) Code = 3; else if (Data[2]) Code = 2; else if (Data[1]) Code = 1; else if (Data[0]) Code = 0; else Code = 3'bx; end

priority

38

Data[7:0]Code[2:0]

valid_data


/*// Alternative description is given below always @ (Data) casex (Data) 8'b1xxxxxxx : Code = 7; 8'b01xxxxxx : Code = 6; 8'b001xxxxx : Code = 5; 8'b0001xxxx : Code = 4; 8'b00001xxx : Code = 3; 8'b000001xx : Code = 2; 8'b0000001x : Code = 1; 8'b00000001 : Code = 0; default : Code = 3'bx; endcase */ endmodule


Synthesis Result:

valid_dataData[0]

Data[1]

Data[3]

Data[4]

Dat

a[5]

Dat

a[2]

Dat

a[7]

Data[6]

Code[2:0]Code[2]

Code[1]

Code[0]

Data[7:0]


Example 5.30: Majority Circuit

module Majority_4b (Y, A, B, C, D); input A, B, C, D; output Y; reg Y; always @ (A or B or C or D) begin case ({A, B,C, D}) 7, 11, 13, 14, 15: Y = 1; default Y = 0; endcase end endmodule module Majority (Y, Data); parameter size = 8; parameter max = 3; parameter majority = 5; input [size-1: 0] Data; output Y; reg Y; reg [max-1: 0] count; integer k;


always @ (Data) begin count = 0; for (k = 0; k < size; k = k + 1) begin if (Data[k] == 1) count = count + 1; end Y = (count >= majority); end endmodule

Mealy Machinemodule Mealy_mdl (x,y,CLK,RST);input x,CLK,RST;output y;reg y;reg [1:0] Prstate, Nxtstate;parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;always @ (posedge CLK or negedge RST)

if (~RST) Prstate = S0; //Initialize to state S0

else Prstate = Nxtstate; //Clock operations

Mealy Machine (cont)always @ (Prstate or x) //Determine next state

case (Prstate)S0: if (x) Nxtstate = S1;S1: if (x) Nxtstate = S3;

else Nxtstate = S0;S2: if (~x)Nxtstate = S0;S3: if (x) Nxtstate = S2;

else Nxtstate = S0;endcase

always @ (Prstate or x) //Evaluate outputcase (Prstate)

S0: y = 0;S1: if (x) y = 1'b0; else y = 1'b1;S2: if (x) y = 1'b0; else y = 1'b1;S3: if (x) y = 1'b0; else y = 1'b1;

endcaseendmodule

Moore Machinemodule Moore_mdl (x,AB,CLK,RST);

input x,CLK,RST;output [1:0]AB;reg [1:0] state;parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;

always @ (posedge CLK or negedge RST)if (~RST) state = S0; //Initialize to state S0

elsecase (state)

S0: if (~x) state = S1; S1: if (x) state = S2;

else state = S3; S2: if (~x) state = S3;S3: if (~x) state = S0;

endcaseassign AB = state;

//Output of flip-flopsendmodule

Universal Shift Register

Universal Shift Registermodule SHFTREG (I,select,lfin,rtin,A,CLK,Clr);

input [3:0] I; //Parallel inputinput [1:0] select; //Mode selectinput lfin,rtin,CLK,Clr; //Serial inputs,clock,clearoutput [3:0] A; //Parallel output

//Instantiate the four stagesstage ST0 (A[0],A[1],lfin,I[0],A[0],select,CLK,Clr);stage ST1 (A[1],A[2],A[0],I[1],A[1],select,CLK,Clr);stage ST2 (A[2],A[3],A[1],I[2],A[2],select,CLK,Clr);stage ST3 (A[3],rtin,A[2],I[3],A[3],select,CLK,Clr);

endmodule

//One stage of shift register module stage(i0,i1,i2,i3,Q,select,CLK,Clr);

input i0,i1,i2,i3,CLK,Clr;input [1:0] select;output Q;reg Q;reg D;

Universal Shift Register (cont)//4x1 multiplexer

always @ (i0 or i1 or i2 or i3 or select) case (select)

2'b00: D = i0;2'b01: D = i1;2'b10: D = i2;2'b11: D = i3;

endcase//D flip-flop

always @ (posedge CLK or negedge Clr)if (~Clr) Q = 1'b0;else Q = D;

endmodule

Ripple Countermodule ripplecounter (A0,A1,A2,A3,Count,Reset);

output A0,A1,A2,A3;input Count,Reset;

//Instantiate complementing flip-flopCF F0 (A0,Count,Reset);CF F1 (A1,A0,Reset);CF F2 (A2,A1,Reset);CF F3 (A3,A2,Reset);

endmodule

//Complementing flip-flop with delay//Input to D flip-flop = Q'module CF (Q,CLK,Reset);

output Q;input CLK,Reset;reg Q;always @ (negedge CLK or posedge Reset)

if (Reset) Q = 1'b0;else Q = #2 (~Q); // Delay of 2 time units

endmodule

Let’s draw the circuit and figure out why it counts up

Ripple Counter (cont)//Stimulus for testing ripple countermodule testcounter;

reg Count;reg Reset;wire A0,A1,A2,A3;

//Instantiate ripple counterripplecounter RC (A0,A1,A2,A3,Count,Reset);

always #5 Count = ~Count;

initial begin

Count = 1'b0;Reset = 1'b1;

#4 Reset = 1'b0;#165 $finish;

endendmodule

What is the expected Simulation result?


Example 5.42 3-Bit Up_Down Counter

module up_down_counter (Count, Data_in, load, count_up, counter_on, clk, reset); output [2: 0] Count; input load, count_up, counter_on, clk, reset; input [2: 0] Data_in; reg [2: 0] Count; always @ (posedge reset or posedge clk) if (reset == 1'b1) Count = 3'b0; else if (load == 1'b1) Count = Data_in; else if (counter_on == 1'b1) begin if (count_up == 1'b1) Count = Count +1; else Count = Count –1; end endmodule


D_inu/d

ld

rst

cnt

clk count

3

3

count_up

load

reset

counter_on

clk

Data_in

Count


counter_on

load

reset

Data_in[2:0]

count_up

clk

Count[2:0]mux2_a

mux2_a

mux2_a

dffrgpqb_a

dffrgpqb_a

dffrgpqb_a

inv_a

inv_a

inv_a

nor2_a

xor2_a

xor2_a xor2_a

xor2_aaoi22_a

See Appendix H for Flip-Flop types


Example 5.44 Parallel Load Shift Register

module Par_load_reg4 (Data_out, Data_in, load, clock, reset); input [3: 0] Data_in; input load, clock, reset; output [3: 0] Data_out; // Port size reg [3: 0] Data_out; // Data type always @ (posedge reset or posedge clock) begin if (reset == 1'b1) Data_out


Synthesis Result

clock

Data_in[3]

R

QD

R

QD

R

QD

R

QD

Data_in[2] Data_in[1] Data_in[0]

reset

Data_out[3] Data_out[2] Data_out[1] Data_out[0]

muxmuxmuxmux

load

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.CHAPTER IX-7

SHIFT REGISTERSCASCADING (1)

REGISTER BLOCKS

•SHIFT REGISTERS-LSR SAMPLE-ASR SAMPLE-4-BIT BIDIRECTIONAL

• Cascading of shift registers can also be done if the discarded bit is used to

shift into another shift register module.

• For instance, the 4-bit bidirectional shift register previously presented can

be easily cascaded using the

• (right shift data input) and

• (left shift data input)

xr

xl

z0z2 z1z3

4-bit bidirectionalshift register xr

xlc0

c1

x3 x2 x1 x0



SHIFT REGISTERSCASCADING (2)

REGISTER BLOCKS

•SHIFT REGISTERS-ASR SAMPLE-4-BIT BIDIRECTIONAL-CASCADING

• For example, an 8-bit bidirectional shift register with parallel load can be

formed as follows.

z0z2 z1z3


xlc0

c1

x3 x2 x1 x0

z0z2 z1z3


xlc0

c1

x3 x2 x1 x0

xr xlc0c1

z0z2 z1z3z4z6 z5z7

x0x2 x1x3x4x6 x5x7



ROTATE REGISTERSUSING SHIFT REGISTERS

REGISTER BLOCKS

•SHIFT REGISTERS•ROTATE REGISTERS

-INTRODUCTION

• Rotate registers can actually be implemented using shift registers that have

serial data inputs (such as the 4-bit bidirectional shift register discussed).

• For example, a 4-bit rotate register can be formed as follows.

z0z2 z1z3


xlc0

c1

x3 x2 x1 x0c0

c1

x0x2 x1x3

z0z2 z1z3



COUNTERSMORE ON MODULO-P

REGISTER BLOCKS

•COUNTERS-TOGGLE CELL-RIPPLE COUNTER-SYNCHRONOUS COUNT.

• Notice that the counters developed so far can count from to for n

toggle cells.

• Therefore, for module-p counting, the p is currently limited to .

• How about if we wish p to be a non-power of 2?

• Need to build what can be referred to as a divide by counter.

• Given the following counter block, a general modulo-p counter can be

constructed by clearing the counter after the desired maximum value.

0 2n 1–

2n

z0z2 z1z3CLEAR

CE 4-bit counterφ1

φ2



COUNTERSBCD COUNTER (MODULO-10)

REGISTER BLOCKS

•COUNTERS-RIPPLE COUNTER-SYNCHRONOUS COUNT.-MORE ON MODULO-P

• To illustrate general modulo-p counters, consider the following

implementation of a single digit decimal counter using BCD.

• Notice that the counter is cleared after a value of 9 (1001).

z0z2 z1z3CLEAR

CE 4-bit binaryCE

CLEAR

φ1

φ2

φ1

φ2counter

TCTerminal Count Output z0z2 z1z3



COUNTERSCASCADING COUNTERS

REGISTER BLOCKS

•COUNTERS-MORE ON MODULO-P-BCD COUNTER-TERMINAL COUNT

• With a terminal count output (TC), counters can be easily cascaded

together to form larger counters.

• For instance, an 8-bit binary counter can be formed as follows.

z0z2 z1z3

CLEAR

CE4-bit binary

φ1φ2

TC

counterz0z2 z1z3

CLEAR

CE4-bit binary

φ1φ2

TC

counter

CLEAR

CE

φ1φ2

φ1φ2

z0z2 z1z3z4z6 z5z7

lec6.pdfM. D. CilettiCopyright 2000, 2002, 2003, 2004. These notes are solely foCOURSE OVERVIEWData TypesBehavioral ModelsExample: Abstract Models of Boolean EquationsExample 5.2 (p 146)Implicit Continuous AssignmentExample 5.4 (p 148)Propagation Delay for Continuous Assignments

Example 5.3 (Note: Three-state behavior)Multiple Continuous AssignmentsReview of Modeling Styles for Combinational LogicLatched and Level-Sensitive BehaviorRecommended Style for Transparent Latch

Example 5.7Example: T-Latch with Active-Low ResetAbstract Modeling with Cyclic BehaviorsExample 5.9: D-type Flip-Flop (p. 153)Example 5.10 (p. 155) Asynchronous ResetExample: Transparent Latch (Cyclic Behavior)Alternative Behavioral ModelsDataflow – RTL ModelsModeling TrapNonblocking Assignment Operator and Concurrent AssignmentsExample: Shift RegisterAlgorithm-Based ModelsSimulation with Behavioral ModelsSee discussion in text – p 165

Example 5.19: Four-Channel Mux with Three-State OutputExample 5.20: Alternative ModelExample 5.21: Alternative ModelExample 5.22: EncoderExample 5.23: Priority EncoderExample 5.24: DecoderExample 5.25: Seven Segment DisplayExample 5.26: LFSR (RTL – Dataflow)Example 5.27: LFSR (RTL – Algorithm)Example 5.28: repeat LoopExample 5.29: for LoopExample 5.30: Majority CircuitExample 5.31 Parameterized Model of LFSRExample 5.32: Ones CounterExample 5.32: Clock GeneratorExample 5.34Example 5.35: Multi-Cycle Operations (4-Cycle Adder)Example 5.36: Task (Adder)Example 5.37: Function (Word Aligner)Example 5.38: Arithmetic UnitAlgorithmic State Machine (ASM) ChartASM Charts (Cont.)Example 5.39 Tail Light ControllerASMD ChartExample 5.39 Two-Stage PipelineDatapath Controller DesignExample 5.40 CountersExample 5.41 Ring CounterExample 5.42 3-Bit Up_Down CounterSee Appendix H for Flip-Flop types

Example 5.43: Shift RegisterExample 5.44 Parallel Load Shift RegisterExample 5.45: Barrel ShifterExample 5.46: Universal Shift RegisterExample 5.47: Register FileMetastability and SynchronizersDesign Example: Keypad Scanner and Encoder (p 216)

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