CPEN 315 - Digital System Design

Chapter 8 – Memory

C. Gerousis© Logic and Computer Design Fundamentals, 4rd Ed., Mano

Prentice Hall

Charles Kime & Thomas Kaminski

© 2008 Pearson Education, Inc.

Overview

Memory definitions Random Access Memory (RAM) Static RAM (SRAM) integrated circuits

– Cells and slices– Cell arrays and coincident selection

Arrays of SRAM integrated circuits Dynamic RAM (DRAM) integrated circuits DRAM Types

– Synchronous (SDRAM)– Double-Data Rate (DDR SRAM)– RAMBUS DRAM (RDRAM)

Memory Definitions

Memory ─ A collection of storage cells together with the necessary circuits to transfer information to and from them.

Random Access Memory (RAM) ─ RAM is called "random access" because any storage location can be accessed directly (independent of the physical location of the data.)

Memory Address ─ A vector of bits that identifies a particular memory element (or collection of elements).

Memory Definitions (Continued)

Typical data elements are:– bit ─ a single binary digit– byte ─ a collection of eight bits accessed together– word ─ a collection of binary bits whose size is a

typical unit of access for the memory. It is typically a power of two multiple of bytes (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.)

Memory Operations ─ operations on memory data supported by the memory unit. Typically, read and write operations over some data element (bit, byte, word, etc.).

Memory Organization

Organized as an indexed array of words. Value of the index for each word is the memory address.

Some historically significant computer architectures and their associated memory organization:– Digital Equipment Corporation PDP-8 – used a 12-bit address

to address 4096 12-bit words.

– IBM 360 – used a 24-bit address to address 16,777, 216 8-bit bytes.

– Intel 8080 – (8-bit predecessor to the 8086 and the current Intel processors) used a 16-bit address to address 65,536 8-bit bytes.

Intel 8080, 4,500 transistors

Historical Computers

IBM 360DEC PDP-8

Memory Organization Example

Example memory contents:

– A memory with 3 address bits & 8 data bits has:

– k = 3 and n = 8

23 = 8 addresses labeled 0 to 7.

– 23 = 8 words of 8-bit data (1-byte data)

Memory Address Binary Decimal

Memory Content

0 0 0 0 1 0 0 0 1 1 1 1

0 0 1 1 1 1 1 1 1 1 1 1

0 1 0 2 1 0 1 1 0 0 0 1

0 1 1 3 0 0 0 0 0 0 0 0

1 0 0 4 1 0 1 1 1 0 0 1

1 0 1 5 1 0 0 0 0 1 1 0

1 1 0 6 0 0 1 1 0 0 1 1

1 1 1 7 1 1 0 0 1 1 0 0

Static RAM Cell Array of storage cells used to implement static RAM Storage Cell

– SR Latch– Select input for

control– Dual Rail Data

Inputs B and B– Dual Rail Data

Outputs C and C

Select

B

RAM cell

C

C

B

S

R

Q

Q

SRAM is used in cache: temporary storage area where frequently accessed data can be stored for rapid access.

Static RAM Cell

2n-Word 1-Bit RAM IC

To build a RAM ICfrom a RAM slice,we need:

– Decoder decodesthe n address lines to2n word select lines

– A 3-state buffer

on the data output.

Dataoutput

A3

A2

A1

A0

Datainput

(a) Symbol

Read/Write

Memoryenable

16 x 1RAM

Read/

Word select

Read/Writelogic

Data inData out

WriteBitselect

(b) Block diagram

RAM cell

RAM cell

RAM cell

Data input

Chip select

Read/Write

Dataoutput

A3

A2

A1

A0

23

22

21

20

4-to-16Decoder 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Memory arrays can be very large– Large decoders– The decoder size and fanouts can be reduced by

approximately by using a coincident selection in a 2-dimensional array

– Uses two decoders, one for words and one for bits

– Word select becomes Row select– Bit select becomes Column select

Cell Arrays and Coincident Selection

n

Cell Arrays and Coincident Selection (continued)

Data input

Read/Write

X XX

A1 A0

RAM cell0

RAM cell4

RAM cell8

RAM cell12

Read/Writelogic

Data inData out

Read/Write

Bitselect

RAM cell1

RAM cell5

RAM cell9

RAM cell13

Read/Writelogic

Data inData out

Read/Write

Bitselect

RAM cell2

RAM cell6

RAM cell10

RAM cell14

Read/Writelogic

Data inData out

Read/Write

Bitselect

RAM cell3

RAM cell7

RAM cell11

RAM cell15

Read/Writelogic

Data inData out

Read/Write

Bitselect

Columndecoder

2-to-4 Decoderwith enable

21 20

0 1

Column select

2

Enable

3

Chip select

Dataoutput

Rowselect

Row decoder

A2

A3

X

2-to-4Decoder

20

21

1

2

3

0

ExampleFor address 1001:10 selects row 201 selects column 1Cell 9 is accessed.

Making Larger Memory

Capacity: 64K words of 8 bits each

256K X 8 RAM (2 MB)

- Three-state outputs are connectedtogether to form 8 data output lines.

- Just one chip select (CS) willbe active at any time.

- RAM requires 18-bit address: 16 LSB address are applied to the addressare applied to the inputs of each RAM.2 MSB are applied to 2-to-4 decoder.

- Address bits 16 and 17 determine the particular chips that is selected.

Dynamic RAM (DRAM)

Basic Principle: Storage of information on capacitors.

Charge and discharge of capacitor to change stored value

Use of transistor as “switch” to:– Store charge– Charge or discharge

Select

BT

C

DRAM cell

Data in

(a) Logic diagram

Select

Wordselect0

Wordselect2n- 1

Write logic

Bitselect

Data outRead logic

Senseamplifier

Read/Write

B T

C

DRAM cell

B T

C Read/Writelogic

Data inData out

Bitselect

DRAM cell

DRAM cell

DRAM cell

Wordselect0

Wordselect1

Wordselect2n - 1

Read/Write

C is driven by 3-state drivers

Sense amplifier is used to change the small voltage difference on C into H or L “to refresh the value of a bit stored in a DRAM cell.”

Dynamic RAM - Bit Slice

DRAM VS. SRAM

Cell size Complexity Cost/bit Usage in large memory Power considerations Speed

phys

ical

siz

e of

mem

ory

decr

ease

s

mem

ory

acce

ss ti

me

incr

ease

s

Memory Hierarchy

DRAM Types

Types to be discussed– Synchronous DRAM (SDRAM)– Double Data Rate SDRAM (DDR SDRAM)– RAMBUS® DRAM (RDRAM)

Synchronous DRAM Transfers to and from the DRAM are synchronize with a clock Comparison of byte rate for reading bytes from SDRAM to that of basic DRAM: Assume READ cycle time of basic DRAM = 60 ns

DRAM byte rate (Memory Bandwidth)

= 16.67 MB/sec

Clock period of SDRAM = 7.5 ns

SDRAM = 66.67 MB/sec

If the read burst = 8 bytes,

What is the read cycle? 90 ns

What is the byte rate for

the SDRAM? 88.89 MB/sec

SDRAM EXAMPLE

Double Data Rate Synchronous DRAM (DDR SDRAM)

Transfers data on both edges of the clock Example: Same as for synchronous DRAM

– Read cycle time = 60 ns, read burst = 8 bytes.

– for DDR ___ bytes can be transferred in 60 ns?

What is the Byte Rate/

Memory Bandwidth?

SDRAM EXAMPLE

16

RAMBUS DRAM (RDRAM) Uses a packet-based bus for interaction between the RDRAM ICs and the

memory bus to the processor The bus consists of:

– A 3-bit row address bus

– A 5-bit column address bus

– A 16 or 18-bit (for error correction) data bus

The electronic design is sophisticated permitting very fast clock speeds

Use clock period 1.875 nstime for accessing 16 byte datapacket = 32 clock cycles.What is the Memory Bandwidth ?If four packed are accessed, whatis the memory bandwidth?

RDRAM EXAMPLE