Counters
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Counters Discussion D5.3 Example 33
description
Counters. Discussion D5.3 Example 33. Counters. 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter. 3-Bit, Divide-by-8 Counter. Present state Next state. State q2 q1 q0 D2 D1 D0. s0 0 0 0 0 0 1 - PowerPoint PPT Presentation
Transcript of Counters
Counters
Discussion D5.3
Example 33
Counters
• 3-Bit, Divide-by-8 Counter
• 3-Bit Behavioral Counter in Verilog
• Modulo-5 Counter
• An N-Bit Counter
3-Bit, Divide-by-8 Counter
s0000
s1001
s2010
s3011
s7111
s6110
s5101
s4100
Divide-by-8 Counter
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State q2 q1 q0 D2 D1 D0Present state Next state
clk
D q
~q
clk
D q
~q
clk
D q
~q
q0D0
q1
q2
D1
D2
0 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 1 1 01 1 0 1 1 11 1 1 0 0 0
q2 q1 q0 D2 D1 D0State
s0s1s2s3s4s5s6s7
currentstate
nextstate
Divide-by-8 Counter
q2
q1 q000 01 11 10
0
1 1 11
1
D2
D2 = ~q2 & q1 & q0 | q2 & ~q1 | q2 & ~q0
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State q2 q1 q0 D2 D1 D0Present state Next state
Divide-by-8 Counter
q2
q1 q000 01 11 10
0
1
1
11
1
D1
D1 = ~q1 & q0 | q1 & ~q0
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State q2 q1 q0 D2 D1 D0Present state Next state
Divide-by-8 Counter
q2
q1 q000 01 11 10
0
1
1
11
1
D0
D0 = ~q0
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State q2 q1 q0 D2 D1 D0Present state Next state
Divide-by-8 Counter
A Divide by 8 countercircuit using D Flip-flops
D q
~qclk
D q
~qclk
D q
~qclk
Dff2
Dff1
Dff0
q2
q1
q0
clk
D2
D1
D0
clk
D q
~q
clk
D q
~q
clk
D q
~q
q0D0
q1
q2
D1
D2
0 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 1 1 01 1 0 1 1 11 1 1 0 0 0
q2 q1 q0 D2 D1 D0State
s0s1s2s3s4s5s6s7
currentstate
nextstate
-- Example 33a: 3-bit divide-by-8 counterlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity count3a is
port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(2 downto 0)
);end count3a;
architecture count3a of count3a issignal D, qs: STD_LOGIC_VECTOR(2 downto 0);begin
D(2) <= (not qs(2) and qs(1) and qs(0))or (qs(2) and not qs(1))or (qs(2) and not qs(0));
D(1) <= (not qs(1) and qs(0))or (qs(1) and not qs(0));
D(0) <= not qs(0);-- Three D flip-flopsprocess(clk, clr)begin
if clr = '1' thenqs <= "000";
elsif clk'event and clk = '1' then
qs <= D;end if;
end process;q <= qs;
end count3a;
clk
D q
~q
clk
D q
~q
clk
D q
~q
q0D0
q1
q2
D1
D2
0 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 1 1 01 1 0 1 1 11 1 1 0 0 0
q2 q1 q0 D2 D1 D0State
s0s1s2s3s4s5s6s7
currentstate
nextstate
count3a Simulation
Counters
• 3-Bit, Divide-by-8 Counter
• 3-Bit Behavioral Counter in VHDL
• Modulo-5 Counter
• An N-Bit Counter
3-Bit Counter
if clr = '1' then count <= "000";elsif rising_edge(clk) then count <= count + 1;end if;
Q <= count;
Behavior
signal count: STD_LOGIC_VECTOR (2 downto 0);
count3clr
clkq(2 downto 0)
library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_unsigned.all;
entity count3b is port(
clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(2 downto 0)
);end count3b;
architecture count3b of count3b issignal count: STD_LOGIC_VECTOR(2 downto 0);begin
process(clr,clk)begin if clr = '1' then
count <= "000"; elsif clk'event and clk = '1' then
count <= count + 1; end if;end process;q <= count;
end count3b;
count3.vhd
Asynchronous clear
Need signal becauseq can not be read
Signal count incrementson rising edge of clk
count3 Simulation
signal clk, cclk: std_logic;signal clkdiv: std_logic_vector(23 downto 0);begin
-- Divide the master clock (50Mhz) down to a lower frequency.-- clock divider
process(mclk, clr)begin
if clr = '1' then clkdiv <= X"000000";elsif mclk'event and mclk = '1' then clkdiv <= clkdiv + 1;end if;
end process;
clk <= clkdiv(0); -- mclk/2 = 25 MHz cclk <= clkdiv(17); -- mclk/218 = 190 Hz
Clock Dividermclk = 50 MHz master clock
(FPGA Pin T9)
Counters
• 3-Bit, Divide-by-8 Counter
• 3-Bit Behavioral Counter in Verilog
• Modulo-5 Counter
• An N-Bit Counter
-- Example 33c: modulo-5 counterlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_unsigned.all;entity mod5cnt is
port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(2 downto 0)
);end mod5cnt;
architecture mod5cnt of mod5cnt issignal count: STD_LOGIC_VECTOR(2 downto 0);begin
-- modul0-5 counterprocess(clk, clr)begin
if clr = '1' thencount <= "000";
elsif clk'event and clk = '1' then if count = "100" then
count <= "000";else
count <= count + 1;end if;
end if;end process;q <= count;
end mod5cnt;
mod5cnt Simulation
Counters
• 3-Bit, Divide-by-8 Counter
• 3-Bit Behavioral Counter in Verilog
• Modulo-5 Counter
• An N-Bit Counter
-- Example 33d: N-bit counterlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_unsigned.all;entity counter is
generic(N : integer := 8); port(
clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0)
);end counter;
architecture counter of counter issignal count: STD_LOGIC_VECTOR(N-1 downto 0);begin
-- N-bit counterprocess(clk, clr)begin
if clr = '1' thencount <= (others => '0');
elsif clk'event and clk = '1' thencount <= count + 1;
end if;
end process;
q <= count;end counter; cnt16: counter
generic map(N => 16) port map(clr => clr, clk => clk, q => q);
counter Simulation
N = 8
