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Counters

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Counters

Counters are a specific type ofsequential circuit.

Like registers, the state, or the flip-flop values themselves, serves as theoutput.

The output value increases by one oneach clock cycle.

After the largest value, the output

wraps around back to 0. Using two bits, wed get somethinglike this:

Present State Next State

A B A B

0 0 0 10 1 1 0

1 0 1 1

1 1 0 0

00 01

1011

1

11

1

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A slightly fancier counter

Lets try to design a slightly different two-bit counter: Again, the counter outputs will be 00, 01, 10 and 11.

Now, there is a single input, X. When X=0, the counter value shouldincrementon each clock cycle. But when X=1, the value shoulddecrementon successive cycles.

Well need two flip-flops again. Here are the four possible states:

00 01

1011

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The complete state diagram and table

00 01

1011

0

0

0

10 1

1

1

Present State Inputs Next State

Q1 Q0 X Q1 Q0

0 0 0 0 1

0 0 1 1 1

0 1 0 1 0

0 1 1 0 0

1 0 0 1 1

1 0 1 0 11 1 0 0 0

1 1 1 1 0

Heres the complete state diagram and state table for this circuit.

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D flip-flop inputs

If we use D flip-flops, then the D inputs will just be the same as thedesired next states.

Equations for the D flip-flop inputs are shown at the right. Why does D0 = Q0 make sense?

Present State Inputs Next State

Q1 Q0 X Q1 Q0

0 0 0 0 1

0 0 1 1 1

0 1 0 1 0

0 1 1 0 0

1 0 0 1 1

1 0 1 0 11 1 0 0 0

1 1 1 1 0

Q0

0 1 0 1

Q1 1 0 1 0

X

Q0

1 1 0 0

Q1 1 1 0 0

X

D1 = Q1 Q0 X

D0 = Q0

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The counter in LogicWorks

Here are some D Flip Flopdevices.

They have both normal andcomplemented outputs, so wecan access Q0 directly withoutusing an inverter. (Q1 is notneeded in this example.)

This circuit counts normallywhen Reset = 1. But when Resetis 0, the flip-flop outputs arecleared to 00 immediately.

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Asynchronous Counters

This counter is called asynchronousbecause not allflip flops are hooked to the same clock.

Look at the waveform of the output, Q, in the timingdiagram. It resembles a clock as well. If the period ofthe clock is T, then what is the period of Q, the outputof the flip flop? It's 2T! We have a way to create a clock that runs twice asslow. We feed the clock into a T flip flop, where T is

hardwired to 1. The output will be a clock who's periodis twice as long.

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3 bit asynchronous ripple counter using T flip flops

This is called as a

ripple counterdue tothe way the FFsrespond one afteranother in a kind of

rippling effect.

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Synchronous Counters

To eliminate the "ripple" effects, use a common clock foreach flip-flop and a combinational circuit to generate thenext state.

For an up-counter,use an incrementer =>

D3 Q3D2 Q2D1 Q1D0 Q0

Clock

Incre-menterA3

A2A1A0

S3S2S1S0

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Changing states

While going through a sequence of binary numbers, th elowerorder bit is complemented after every count and every other bit

is complemented from one count to the next count if and only ifall the lower order bits are equal to 1.

For eg. 0111 (7). .. 1000 (8) is obtained bya) complementing the LOBb) Complementing the second bit because the first bit of 0111 is 1c) Complementing the third bit coz first 2 bits are 11d) Complementing the fourth bit coz the first 3 bits are of 0111

are 1

Henry Hexmoor 12

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Another restricted counter

We can also make a circuit that counts up to only 1100, instead of 1111. Here, when the counter value reaches 1100, the NAND gate forces the

counter to load, so the next state becomes 0000.

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Synchronous BCD (continued)

Use K-Maps to two-level optimize the next state equations andmanipulate into forms containing XOR gates:

D1 = Q1 D2 = Q2 + Q1Q8

D4 = Q4 + Q1Q2D8 = Q8 + (Q1Q8 + Q1Q2Q4)

Y = Q1Q8

The logic diagram can be drawn from these equations

An asynchronous or synchronous reset should be added

What happens if the counter is perturbed by a power disturbance orother interference and it enters a state other than 0000 through

1001?

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Find the actual values of the six next states for the dont carecombinations from the equations Find the overall state diagram to assess behavior for the dont care

states (states in decimal)

Synchronous BCD (continued)

Present State Next State

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1

1 0 1 0 1 0 1 1

1 0 1 1 0 1 1 0

1 1 0 0 1 1 0 1

1 1 0 1 0 1 0 0

1 1 1 0 1 1 1 11 1 1 1 0 0 1 0

0

1

8

7

6

5

4

3

2

9

10

11

14

1512

13

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For the BCD counter design, if an invalid state is entered, return toa valid state occurs within two clock cycles

Is this adequate?!

Synchronous BCD (continued)

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Unused states can be dont cares

To get the simplestpossible circuit, you can fill in dont cares for thenext states. This will also result in dont cares for the flip-flop inputs,

which can simplify the hardware. If the circuit somehow ends up in one of the unused states (110 or 111),its behavior will depend on exactly what the dont cares were filled inwith.

Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 11 0 1 0 0 0

1 1 0 x x x

1 1 1 x x x

001

010

011

100

101

000

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