Counter n Shift Register
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Transcript of Counter n Shift Register
15/09/2015
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Teknik Mesin Unjani
MEKATRONIKAMeet 2 : Counter dan Shift Register
HBH Herman Budi Harja, S.T., M.T.
15 September 2015
DefinisiCounter aplikasi Flip flop sebagai penghitung maju/mundur.Register merupakan penerapan flip flop sebagai penyimpan memori (1 bit = 1 Flip flop)
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Case
• Common TTL Flip-Flops
– 7474 is a positive edge triggered D flip-flop• Active low Preset (PRN) and Clear (CLRN)
– 7473a is a negative edge triggered JK flop-flop• 7473 is the master-slave version
– positive edge triggered
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• Registers
– A flip-flop stores one bit of information
– When you want to store n bits register• n flip-flops used• Clock is shared by all so action is synchronous with clock edge
– Some common register types• Simple register• Shift register• Parallel access shift register• Lots of counters: up counter, down counter, BCD counter, ring counter,
Johnson counter
• Simple 4 Bit Register
– A standard 4 bit register using D flip flops
Q3 Q2 Q1 Q0
Clock
Parallel input
Parallel output
D Q
Q
D Q
Q
D Q
Q
D Q
Q
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• 4 Bit Register with Load Control
– Controlling the load capability
Q3 Q2 Q1 Q0
Clock
Parallel input
Parallel output
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Load
• Simple Shift Register
– Provide only serial in/out access
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
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• Action of Shift Register
– Can you use a level sensitive gated latch instead of a flip-flop?• No! The values would propagate during Clock = 1
t 0
t 1
t 2
t 3
t 4
t 5
t 6
t 7
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
Q 1 Q 2 Q 3 Q 4 Out = In
• Parallel Access Shift Register
– Provide parallel data load– Provide parallel data read– Provide serial shift
– Shift/Load = 0 Shift right
– Shift/Load = 1 Load
Q3 Q2 Q1 Q0
ClockParallel input
Parallel output
Shift/LoadSerialinput
D Q
Q
D Q
Q
D Q
Q
D Q
Q
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• Example Problem: General Shifter
– Design a parallel access (parallel data in / out) shift register that can load or shift either left or right – choice dictated by a control signal
• Then add the ability to "stay in memory"• Don't forget to connect serial in to both MSB and LSB
S1 S0 Function
0 0 memory
0 1 SHR
1 0 SHL
1 1 load
• Solution: General Shifter
Q3
ClockParallel input
Parallel output
D Q
Q
0 1 2 3s1s0
Q3
D Q
Q
0 1 2 3s1s0
Q3
D Q
Q
0 1 2 3s1s0
Q3
D Q
Q
0 1 2 3s1s0
SRSI SLSI
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• 74164 Shifter
– 8 bit serial in / parallel out shifter (used in modems)• Active low clear (CLRN)• Data-in provided by AND(A,B)• Positive edge triggered shift right register
• 74165 Shifter
– 8 bit parallel in / serial out shifter (also used in modems)• Active low asynchronous parallel load – output is H• CLKIH is an active high clock inhibit – memory state• Positive edge-triggered shift right register: SER is serial in
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• 74194 Bi-Directional Shifter
– 4 bit bi-directional shifter with parallel load• Active low asynchronous clear• Shift Left Serial In (SLSI)• Shift Right Serial In (SRSI)• Positive edge-triggered
• Asynchronous Counters
– Up counter using T flip-flops• Count clock pulses
– Q0 toggles on every 0 1 clock edge– Q1 toggles on every 1 0 transition of Q0– Q2 toggles on every 1 0 transition of Q1
T Q
Q Clock
T Q
Q
T Q
Q
1
Q 0 Q 1 Q 2
MSB of count
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• Delays in Asynchronous Counters
– Propagation delays slow this counting process!
T Q
Q Clock
T Q
Q
T Q
Q
1
Q 0 Q 1 Q 2
Clock
Q 0
Q 1
Q 2
Count 0 1 2 3 4 5 6 7 0
• Asynch Modulo 8 Up Counter
– This counter counts 000 001 … 111 000• Assumes output is in order Q2 Q1 Q0
• Modulo 8 up counter
– The lower order flip-flop is synchronized to the Clock• All other flip-flops are not – asynchronous• Also called ripple counter
T Q
Q Clock
T Q
Q
T Q
Q
1
Q 0 Q 1 Q 2
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• Asynch Modulo 8 Down Counter
– To count 111 110 … 001 000 111
T Q
Q Clock
T Q
Q
T Q
Q
1
Q 0 Q 1 Q 2
Clock
Q 0
Q 1
Q 2
Count 0 7 6 5 4 3 2 1 0
• Synchronous Counters
– Asynchronous counters are slow due to propagation delays• Synchronous counters share the clock among all flip-flops
clock cycle Q2 Q1 Q00 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 18 0 0 0
T0 = 1 always toggleT1 = Q0 toggle when Q0 = 1T2 = Q1Q0 toggle when Q1Q0 = 1T3 = Q2Q1Q0 toggle when Q2Q1Q0 = 1…
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• Mod 16 Synchronous Up Counter
T Q
Q Clock
T Q
Q
T Q
Q
1 Q 0 Q 1 Q 2
T Q
Q
Q 3
• Waveform for Mod 16 Up Counter
T Q
Q Clock
T Q
Q
T Q
Q
1 Q 0 Q 1 Q 2
T Q
Q
Q 3
Clock
Q 0
Q 1
Q 2
Count 0 1 2 3 5 9 12 14 0
Q 3
4 6 8 7 10 11 13 15 1
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• Adding Clear and Enable Signals
– Just use T flip-flop with asynchronous clear– Cascade the Enable via AND gates to the T inputs
• Recall: T toggle only when T input = 1
T Q
Q Clock
T Q
Q
Enable
Clear
T Q
Q
T Q
Q
• 4 Bit Up Counter Using D Flip-Flops
– How can you make an up counter using D flip-flops?
clock cycle Q2 Q1 Q0
0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 18 0 0 0
D0 = 1 Q0 always toggleD1 = Q1 Q0 toggle when Q0 = 1D2 = Q2 Q1Q0 toggle when Q1Q0 = 1D3 = Q3 Q2Q1Q0 toggle when Q2Q1Q0 = 1…
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• 4 Bit Up Counter
– Enable input permits control of counter
– Output carry permitschaining of countersto make larger ones
Clock
Enable D Q
Q
D Q
Q
D Q
Q
D Q
Q
Q0
Q1
Q2
Q3
Outputcarry
• Counter With Parallel Load
– Want a counter that can load any initial value that you desire in order to start the count
• Load = 1 load• Enable = 1 increment• Load = Enable = 0 memory
EnableD Q
Q Q 0
D Q Q
Q 1
D Q Q
Q 2
D Q Q
Q 3
D 0
D 1
D 2
D 3
LoadClock
Outputcarry
0 1
0 1
0 1
0 1
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• Mod n Counting for n 2k
– Most counters reset (cycle) to 0 when all k flip-flops are 1 value of count = 2k-1
• Mod 8 counter: k = 3– 000 001 010 … 111 000
– How to synchronously reset when value < 2k-1?• Want to allow something like:
– 000 001 … 101 000– This is a mod 6 counter
• Mod 6 Synchronous Up Counter
– When output = Q2Q1Q0 = 101, load 000 to force reset on next clock edge
• This provides a synchronous reset
Enable
Q 0 Q 1 Q 2
D 0 D 1 D 2 LoadClock
1 0 0 0
Clock
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• Another Mod 6 Up Counter
– This version provides an asynchronous reset• Look at the narrow width of the 101 output level!
T Q
Q Clock
T Q
Q
T Q
Q
1 Q 0 Q 1 Q 2
Clock
Q 0
Q 1
Q 2
Count 0 1 2 3 4 5 0 1 2
recognizes 1x1
• Other Counter Types
– BCD Counter• Count from 0 to 9 and back to 0• Cascade the counters to mimic decimal counting
– 00 01 … 09 10 11 … 19 20 …– Each position is a BCD digit
– Ring Counter• 4 bit ring count: 1000 0100 0010 0001 1000 …• One-hot output that cycles in a ring
– Johnson Counter• 4 bit count: 0000 1000 1100 1110 1111 0111 0011 0001 0000 …
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• 2 Digit BCD Counter
EnableQ0Q1Q2
D0D1D2
LoadClock
1000
Clock
Q30 D3
EnableQ0Q1Q2
D0D1D2
LoadClock
000
Q30 D3
BCD0
BCD1
Clear
Is 1 when 1xx1 is detected-- first time is for 1001 = 9
• 4 Bit Ring Counter Using a Decoder
– Counts 1000 0100 0010 0001 1000 …
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• Ring Counter Using D Flip-Flops
– A design that uses a minimum of combinational logic, but uses more flip-flops
D Q
Q
Clock
D Q
Q
D Q
Q
Q 0 Q 1 Q n 1 –Start
asynchronous preset
asynchronous clear
• Johnson Counter
– n-bit counter that generates a sequence of length 2n• 0000 1000 1100 1110 1111 0111 0011 0001 0000 ….
D Q
Q
Clock
D Q
Q
D Q
Q
Q 0 Q 1 Q n 1 –
Reset pushes the initial 1 into the count