COTS Based High Performance Radar and EW Development Platform HPEC September 2011 Mikael Taveniku,...

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COTS Based High Performance Radar and EW Development Platform HPEC September 2011 Mikael Taveniku, XCube Gunnar Hillerstrom, Swedish Defence Research Agency 06/24/22 Page 1 XCube 2011

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Other Demo Setup (LPI Radar Simulation & Detection) 1/17/2016XCubePage 3 Signal Generator Receiver ADC FPGA Frontend Stream Buffers Disk Scheduler Disk Manager Control PC PCI e GP-GPU Transmit DAC HRFT Standalone HRFT Internal disk Processor Array (future FMC) disk Disk writer Tight Timing High Throughput Disk writer DMA Decoupling Buffering and ProcessingExternal Interfaces Host Processing 2.4Gsps - 8 bit data 8 Channels 150MHz (I/Q-data) Window FFT waterfall 1200MByte/s throughput (and storage) Radar (FMCW) / Frequency Hop (FH) Interface Manager

Transcript of COTS Based High Performance Radar and EW Development Platform HPEC September 2011 Mikael Taveniku,...

Page 1: COTS Based High Performance Radar and EW Development Platform HPEC September 2011 Mikael Taveniku, XCube Gunnar Hillerstrom, Swedish Defence Research Agency.

COTS Based High Performance Radar and EW Development Platform

HPEC September 2011Mikael Taveniku, XCube

Gunnar Hillerstrom, Swedish Defence Research Agency

05/03/23 Page 1XCube 2011

Page 2: COTS Based High Performance Radar and EW Development Platform HPEC September 2011 Mikael Taveniku, XCube Gunnar Hillerstrom, Swedish Defence Research Agency.

COTS EW/Radar Development Platform

05/03/23XCube 2011 Page 2

Adarate FPGA Front end & analog interface (ADC/DAC)

NVIDIAFloating point DSP & HMI- GPGPU GTX590

Adapteva (future)Complex CPU/DSPintensive processing- ATDSP (future) / Others

Data Storage and ControlXCube Development Platform- Control / Record / Replay Software- Dual Xeon CPU- Up to 144GByte Memory- >4.4GByte/s Throughput- >8 GByte/s Burst- 96TB removable storage (shown)

- Virtex6 130LXT – 475SXT- 2x National ADC083000 (selectable)- 2x Analog devices AD9739- 2x 1Gbit Ethernet - PCI-express

Page 3: COTS Based High Performance Radar and EW Development Platform HPEC September 2011 Mikael Taveniku, XCube Gunnar Hillerstrom, Swedish Defence Research Agency.

Other

Demo Setup (LPI Radar Simulation & Detection)

05/03/23 XCube Page 3

Signal Generator

ReceiverADC

FPGAFrontend

StreamBuffers

Disk Scheduler

Disk Manager

Control PC

PCIe

GP-GPU

TransmitDAC

HRFT Standalone

HRFT Internaldisk

Processor Array (future FMC) disk

Diskwriter

Tight Timing High Throughput

Diskwriter

DMA

Decoupling

Buffering and ProcessingExternal Interfaces

Host Processing2.4Gsps - 8 bit data8 Channels 150MHz (I/Q-data)Window FFT waterfall1200MByte/s throughput (and storage)

Radar (FMCW) / Frequency Hop (FH)

InterfaceManager