Cost Analysis and Cost-Driven IP Reuse Methodology forSoC design Based on 2.5D/3D Integration

Invited Paper

Dylan Stow, Itir Akgun, Russell Barnes, Peng Gu, Yuan XieUniversity of California, Santa Barbara

1155 Phelps HallSanta Barbara, California

{dstow,yuanxie}@ece.ucsb.edu

ABSTRACTDue to the increasing fabrication and design complexity withnew process nodes, the cost per transistor trend originallyidentified in Moore’s Law is slowing when using traditionalintegration methods. However, emerging die-level integra-tion technologies may be viable alternatives that can scalethe number of transistors per integrated device while re-ducing the cost per transistor through yield improvementsacross multiple smaller dies. Additionally, the escalatingoverheads of non-recurring engineering costs like masks andverification can be curtailed through die integration-enabledreuse of intellectual property across heterogeneous processtechnologies. In this paper, we present an analytical costmodel for 3D and interposer-based 2.5D die integration andemploy it to demonstrate the potential cost reductions acrosssemiconductor markets. We also propose a methodology andplatform for IP reuse based on these integration technologiesand explore the available reductions in overall product costthrough reduction in non-recurring engineering effort.

1. INTRODUCTIONThe semiconductor industry has seen tremendous growth

because of the economic and performance scaling of increas-ing integration complexity, with each new process node de-livering more transistors per silicon area with better perfor-mance and lower cost per transistor. By following the ca-dence of this scaling trend, formally recorded by Moore [10],the industry has been able to scale integrated circuits fromseveral transistors to several billion, enabling the integra-tion of floating point units, cache memories, multiple cores,graphics processing units, and power management units. Inthe maturing System-on-Chip era, a single die may addi-tionally include modems, digital signal processors, heteroge-neous cores, and application-specific accelerators to providefurther system efficiency and market differentiation.

After several decades, however, these industry-defining

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DOI: http://dx.doi.org/10.1145/2966986.2980095

scaling trends may be reaching their conclusions. Powerscaling has slowed significantly, leading to the current ”darksilicon” era of power-efficiency driven design. While thenumber of transistors per die continues to increase withsmaller process nodes, many foundries have already failed toachieve the targeted area scaling per transistor and the ca-dence of new process technologies is expected to slow downfor future nodes. Perhaps most importantly, Moore’s fa-mous observation on the cost per transistor may no longerhold, as the fabrication of sub-20nm FinFET transistors issufficiently complex to require difficult and expensive fab-rication technologies that translate to yield challenges andadditional wafer cost. Thus, circuit designers and computerarchitects can no longer depend on the free availability ofadditional transistors and integration opportunity with eachnew process node. Additionally, non-recurring engineeringcosts have also increased quickly during the last several pro-cess nodes due to fabrication complexity issues, such as com-plex layout design rules and multiple masks per layer, anddue to the system complexity challenges of verifying billionsof logic gates.

Despite these major setbacks, alternate integration tech-nologies may be able to function in tandem with traditionalprocess node scaling to provide cost reductions and moretransistors per circuit. Through die-level integration tech-nologies, multiple circuit dies can be connected electricallyand physically to produce a larger integrated circuit. Thesetechnologies include 3D die stacking with connections througheither face-face micro-bumps or face-back Through-SiliconVias (TSVs), or through interposer-based 2.5D integrationthat uses a large passive routed die to provide interconnectbetween dies and the substrate. By partitioning a monolithicSoC across multiple small die, yield per die can be greatlyimproved and metal layer count can be lowered, reducingthe total IC cost if integration overheads are sufficiently low.Die-level integration also allows for new integration strate-gies, such as heterogeneous process integration with differentprocess technologies between dies, that can be used to re-duce costs or optimize performance. These technologies canalso act as a platform for the reuse of hard intellectual prop-erty, allowing for the reconfiguration of SoCs through theintegration of different die combinations while amortizingnon-recurring overheads of design, verification, and masks.1

1This project was supported by the DARPA DAHI pro-gram through ONR award N00014-16-1-2087. We thank Dr.Daniel Green for his help and guidance on this project.

Monolithic 2D IC

3D IC with 2 die

2.5D IC with 2 die and interposer

Figure 1: Die-level integration through TSV-based3D and interposer-based 2.5D technologies.

In this paper, we present a high-level, analytical cost modelfor 3D and 2.5D integrated circuits and apply the modelto current and future process technologies to demonstratethe feasible cost savings that are achievable through die-level integration. We also propose techniques for IP reusethat take advantage of these emerging integration technolo-gies and provide analysis of achievable cost reductions acrossmarkets.

2. METHODOLOGY FOR COST ANALYSISIn order to accurately study the relative costs of tradi-

tional 2D integrated circuits versus 3D or 2.5D die-level in-tegrated circuits, an analytical cost model was developedto determine the approximate manufacturing cost per inte-grated circuit. The methodology includes flexible estima-tion of die area, metal layer count, and die yield to deter-mine cost per individual die. The model extends to include3D processing and bonding overhead, additional TSV area,2.5D interposer cost, and packaging cost to estimate the finalmanufacturing cost of the packaged integrated circuit.

2.1 Die Cost MethodologyThe cost of an individual die, whether the monolithic die

in a traditional 2D circuit or one of several dies in a 3D or2.5D circuit, can be estimated from a few parameters, al-lowing for a wide range of design costs to be studied andcompared. The choice of process technology has a majorimpact on the die cost as it determines the cost per wafer,number of metal layers and cost per additional layer, theaverage area per transistor and gate, and the defect density.Once a process technology has been selected, the expectedarea can be calculated from the number of transistors orgates, with previous work assuming an average of four tran-sistors per gate. In this paper, the area is estimated with theequation Adie = Ng ∗ βλ2 where Ng is the number of gates,λ is the feature size, and β is an empirical scaling term suchthat βλ2 is the average area per gate. A value for β can bedetermined from a survey of previous market designs, withvalues ranging from 450 million for dense graphics proces-sors, 700 million for consumer CPUs, and up to 850 millionfor some SoCs. As some sub-28nm foundry process nodeshave scaled less than expected [11][12], the λ value shouldbe adjusted to the true effective feature size.

With the process technology, area, and number of gatesper die, it is then possible to estimate the required number

of metal layers. Rent’s rule, an observation on the numberof nets crossing a boundary between groups of gates [8], canbe extended to estimate the average metal length given thenumber of gates and routing efficiency [3], expressed as

L̄ =2

9

( 1− 4p−1

1−Np−1g

)(7Np−0.5g − 1

4p−0.5 − 1−

1−Np−1.5g

1− 4p−1.5

)(1)

where p is the Rent’s exponent value that expresses theamount of route optimization [1]. The number of metal lay-ers can then be approximated from the average wire lengthwith the equation

Nmetal =f.o.NgL̄ω

ηAdie(2)

where Nmetal is the number of required metal layers, f.o. isthe average fanout, ω is the wire pitch, and η is the averageinterconnect utilization rate minus the overheads of vias andpower and clock tracks. The formula employed in this modelassumes a uniform metal pitch across layers to maintain flex-ibility between processes, but layer-based assignment withvariable wire pitch and utilization can be employed if knownand specified [4][6].

Metal layer estimation is an important step in the costmodel because the maximum number of metal layers impactsthe cost per wafer. By partitioning a single large die intomultiple smaller die, the number of metal layers per die canbe reduced, helping to reduce the die cost. As shown inTable 1, multiple metal layers can be removed from a designwith sufficient die partitioning.

Area(mm2) Gate Count 1 die 2 dies 3 dies 4 dies5 21 7 7 6 610 41 8 7 7 725 103 9 8 8 750 207 9 9 8 8100 413 10 9 9 9250 1033 11 10 10 9500 2065 12 11 11 10

Table 1: Estimated metal layer counts of single andpartitioned die with 14nm process, β = 650M , andη = 0.3

After the determination of process technology, die area,and required metal layer count, the manufacturing cost ofthe die can be determined by calculating the number of dieper wafer and the resulting die yield. First, the cost perwafer can be defined as Cwafer = Cprocess+Nmetal ∗Cmetal,where Cwafer is the total wafer cost, Cprocess is the basewafer cost, and Cmetal is an additional cost per metal layer.From a given wafer, the number of rectangular die per cir-cular wafer is approximated by

Ndie =π × (φwafer/2)2

Adie− π × φwafer√

2×Adie(3)

where Ndie is the number of dies per wafer, φwafer is thewafer diameter, and Adie is the die area. The process tech-nology, and its maturity, also determines the defect density,or number of failure-causing defects per area. With the de-fect density D0, the yield per die is

Ydie = Ywafer ×(

1 +AdieD0

α

)−α(4)

where Ydie is the die yield and in this model α = 3 [2]. Ofimportant concern is the negative exponential trend of yield

with area, as shown in Figure 2, that causes the yield oflarge die to rapidly diminish. By having more small dies onor across wafers, each defect will cause a lower percentage ofthe wafer to fail and yield per die will be higher. Therefore,this trend suggests the possibility of reducing manufacturingcost through die-level integration by achieving higher dieyields. Finally, the cost per die can be calculated with

Cdie = (CwaferNdie

+ Ctest)/Ydie (5)

where Ctest is the cost to verify each die, which is depen-dent on the circuit complexity. An industry cost projectiontool was used to calculate the specific process costs for eachtechnology [5].

Figure 2: Yield versus Die Area with D0 = 0.3defects/cm2

2.2 Die-Integration Cost OverheadsThe manufacturing cost of a traditional 2D integrated cir-

cuit is the cost of the single silicon die. 3D and 2.5D inte-grated circuits, however, have additional fabrication over-heads, and therefore additional wafer costs, that need to beaccounted for in the analysis model. For 3D circuits withface-back integration and TSVs, it is necessary to first thinthe dies to achieve the proper aspect ratio and to then fab-ricate the TSVs. The bonding process between dies alsointroduces extra process costs and potential yield decreasefrom improper alignment. Additionally, for many current in-tegration techniques, TSVs will block off active device area,so a given partitioned die will need slightly more area forthe X number of TSVs: A3D = Adie + XTSVATSV . Thenumber of TSVs can be calculated by again using Rent’srule with the equation

XTSV =αk1,2(N1 +N2)(1− (N1 +N2)p1,2−1)−αk1N1(1−Np1−1

1 )− αk2N2(1−Np2−12 )

(6)

where N1 and N2 are the gate counts in each layer, k1, k2,p1, and p2 are the Rent’s Rule coefficients per layer, and k1,2and p1,2 are equivalent Rent coefficients between layers [15].Overall, the cost of a 3D integrated circuit can be estimatedas

C3D =

∑ni=1 (Ci+CO

yi) + (n− 1)Cbond

Y n−1bond

(7)

where Ybond is the bond yield, n is the number of die, Ciand yi are the silicon cost and yield of a given die, CO isthe additional overhead cost per die for 3D processing, andCbond is the cost of alignment and bonding between die.

Interposer-based 2.5D circuits must similarly include theoverheads of bonding dies, but thinning and TSV creationare not necessary if the dies are not 3D stacks, since they canbe connected with micro-bumps and copper pillars directlyfrom their top medal layer to the interposer. Of course,these designs must also pay for the cost of the interposers,which are currently produced using mature BEOL technolo-gies from standard foundry processes. The large interposersuffers from the same yield versus area trend as a CMOS die,but the passive nature of the interposer without active de-vices makes the yield and wafer costs of the interposer muchbetter. Figure 3 shows the relative costs of a 65nm CMOSdie and 65nm interposer at several different sizes, demon-strating the much lower interposer cost per area. Overall,the cost of the full 2.5D integrated circuit can be calculatedwith:

C2.5D =

Cintyint

+∑ni=1 (Ci

yi+ Cbondi)

Y n−1bond

(8)

where Cint and yint are the interposer silicon cost and yield,calculated just as an active silicon die but with lower wafercost and higher yields.

0

1

2

3

4

5

25 50 100

Co

st (

a.u

.)

Area (mm²)

Die Cost

Interposer Cost

Figure 3: Costs of 65nm interposer and CMOS dievs. area

3. DIE COST ANALYSISUsing the cost estimation methodology described in the

previous section, we can compare the relative manufacturingcosts of a given design across 2D, 2.5D, and 3D integrationconfigurations. Using the assumed values stated in Table 2,Figure 4 shows the cost impact of partitioning a single 2Ddesign into multiple equally-sized dies, either 2 or 4 dies, us-ing either interposer-enabled 2.5D integration or TSV-based3D integration. As evident in the figure, smaller designs withless area remain most cost effective as a single-die, due tothe overheads of additional processing, bonding, and test-ing with die-level integration, as well as the TSV area for3D and interposer cost for 2.5D. However, these overheadsbecome less significant as the design size increases and thecost becomes dominated by the decreasing yield.

Relative breakdowns of the cost contributions at two de-sign sizes can be seen in Figures 5 and 6. The points of equalcost between 2D and different die-level integration configu-rations are shown across process technologies in Table 3 andacross bond yield in Table 4.

Table 2: Assumed values for design exploration.Feature Size (λ) 14 nm Ywafer 98%Area Scaling (β) 650M Ybond 99%

Rent’s Coefficient (k) 4.0 DTSV 1 µmRent’s Exponent (p) 0.6 Dµbump 25 µmMetal Utilization (η) 30% Interposer Feature Size 65 nm

Gate Pitch 4.5 × λ Average Fan-out (f.o.) 4Wire Pitch 3.6 × λ Defect Density (D0) 0.2-0.3

0

5

10

15

20

25

30

35

40

45

25[106]

50[213]

100[426]

200[852]

Co

st (

a.u

.)

Area (mm²)[Gate Count (M)]

2D2.5D 2-die2.5D 4-die3D 2-layer3D 4-layer

Figure 4: 14nm cost vs. gate count for 2D, 2.5D,and 3D

0

2

4

6

8

10

2D 2.5D2-die

2.5D4-die

3D2-die

3D4-die

Co

st (

a.u

) Bond

TSV

Int

Test

Die

Figure 5: Cost contributions in 14nm with 250Mgates

0

5

10

15

20

2D 2.5D2-die

2.5D4-die

3D2-die

3D4-die

Co

st (

a.u

.) Bond

TSV

Int

Test

Die

Figure 6: Cost contributions in 14nm with 500Mgates

Table 3: 2.5D/3D cost enabling points vs. processGate Count (M) 2D Area (mm2)

16 nm 2.5D 262 75.13D 177 50.7

28 nm 2.5D 231 117.73D 133 67.8

40 nm 2.5D 107 111.33D 87 90.5

4. NON-RECURRING ENGINEERING COSTThe cost model and analysis presented in the previous sec-

tions cover the manufacturing cost of an integrated circuit,which can be examined without concern for specific prod-

Table 4: 14nm enabling points, in gate count, vs.bond yield

BondYield(%)

2.5D2-die

2.5D3-die

2.5D4-die

3D 2-layer

3D 3-layer

3D 4-layer

0.99 325 M 361 M 376 M 262 M 270 M 326 M0.95 481 M 536 M 615 M 288 M 394 M 487 M0.90 747 M 770 M 923 M 383 M 555 M 666 M

uct volume quantity. The total cost of an integrated circuitmust also include the contribution of non-recurring engi-neering (NRE) costs that are paid once and then amortizedacross the number of produced circuits. For sufficiently largevolumes, these non-recurring costs are distributed across alldevices for a small impact on cost per device. Unfortunately,increases in design complexity with smaller process nodesand higher levels of integration are resulting in growing NREcosts. This includes physical complexity from smaller fea-ture size, requiring multiple masks per layer and more dif-ficult design rules, as well as system complexity from moretransistors per integrated circuit, resulting in more difficultdesign and verification. Industry analysts have observed arise in the design cost of a standard SoC by 2.7x between28nm and 14nm designs, and anticipate a further increase to9x, over $270 million, from 28nm to 7nm [9]. Similarly, pro-jections from ARM suggest that because of non-recurringcosts, average sized designs will be prohibitively expensivewith volumes less than 10 million units and even at highvolumes there will be an increase in cost per constant area[14]. To demonstrate the relative impact of NRE costs, Fig-ure 7 uses the constant area die cost projections from [14] tobreak down the total die cost between silicon manufacturingcost and amortized NRE overhead for a sample 14nm chip atdifferent product volumes. Similar but less extreme trendsare seen for older process technologies with reduced processcomplexity, while future technology nodes will require evenlarger unit volumes to amortize the expensive non-recurringcosts.

0

20

40

60

80

100

120

140

160

1M 3M 10M 30M 100M

Co

st (

a.u

.)

Product Volume

NRE

Silicon

Figure 7: Total die cost breakdown between siliconfabrication and NRE overhead for sample 14nm chip

As demonstrated in the previous sections, die-level inte-gration may be a cost-driven design method towards thereduction of manufacturing costs and the improvement ofintegrated circuit yields, especially for larger designs likeSoCs. However, non-recurring engineering costs may stilldominate the overall product cost, especially at lower vol-umes, if a design is only partitioned across multiple dies.To further reduce costs and combat the trend of increasingNRE, die-level integration may also be employed as a plat-form for the reuse of intellectual property at the die level.The dies of non-critical logic can be used across SoC de-

signs to further amortize the initial non-recurring costs ofmask and design and to greatly reduce the verification ef-fort. Additionally, heterogeneous process technologies canbe employed, so any critical logic can move to the highestperforming node while reusable logic may remain in an olderprocess technology with mature yields.

5. FLEXIBLE INTERCONNECT ARCHITEC-TURE FOR IP-REUSE

In traditional SOC integration, various IP blocks are con-nected with standardized bus (such as AMBA bus) or cus-tomized point-to-point interconnects. Such interconnect ar-chitecture is typically fixed for one particular design, anddoes not provide flexibility to be reused for future chip inte-gration, because the interconnect fabrics and IP blocks areall fabricated on the same 2D chip. Such interconnect fabricis normally built for providing best average case performanceacross a generic set of applications. The reason being, nofixed on-chip network design efficiently supports all differ-ent types of communication requirements. Therefore it lacksflexibility and is unable to adapt to dynamically changingand special communication requirements at runtime. In ad-dition, in 2D as well as 3D designs the interconnect fabric istightly coupled with computing (core) and storage (cache)components. This pushes chip designers to adopt low com-plexity, structured and regular interconnect design to limitpre-fabrication and post-fabrication verification efforts andcosts.

We propose to leverage 2.5D/3D integration technologyto design flexible interconnect topology that can ensure ex-isting or future IP block can be easily swapped, so that eachdevice technology’s unique performance characteristic canbe preserved while enabling fast and compatible integration.

The reuse of intellectual property at the die-integrationlevel may be realized through both 3D and 2.5D technolo-gies. Reuse with TSV-based 3D integration would normallybe limited by the predetermined placement and connectiv-ity of the TSVs. In our work, the key concept is to adoptthe Network-on-Chip concept to replace the traditional businterconnect structure, and decouple the interconnect fabricfrom the IP blocks, and implement the interconnect architec-ture in a separate silicon layer called interconnect servicelayer (ISL) [13], either on the interposer (for 2.5D) or asan independent layer in 3D stacking. Such decoupling canprovide reduced manufacture cost and offer more reliableand flexible interconnect layer compared to its traditional2D counterparts. The decoupled ISL can contain multipleon-chip networks such as mesh, ring, hierarchical bus topolo-gies, etc. With ISL the constraints on the on-chip networkrouter area and link bandwidth can be relaxed, and it canalso support different manufacture volume for each die in3D to reduce the overall cost. For example, the proposedISL (either as 2.5D interposer or as a separate layer in true3D stacking) can be manufactured with much larger volumethan the IP blocks, then it can be integrated with variousIP blocks on various design, such as with different numberof CPU cores and various analog/mixed signal IP blocks.

The service layer is an additional die that provides a network-on-chip (NoC) with interconnect and routers to connect theTSVs between the integrated die above and below it, allow-ing for non-adjacent units within and across dies to com-municate efficiently. An example ISL system is shown in

8a. Because of the relative uniformity and sparseness of theservice layer, it can be produced at high yield and volumeto minimize the manufacturing cost. A catalog of severalISL designs of varying sizes could be used to address differ-ent product markets, but to minimize the number of masksets each ISL design can allow for physical slicing of the fulldie to match the area of a given product, reaching a largerproduct volume and amortizing design and mask costs.

Interconnect Service Layer

IP Die

IP Die Silicon Interposer Service Layer

IP Die

IP Die

IP Die

(a) (b)

IP Die

Figure 8: (a) Interconnect Service Layer (ISL)for TSV-based 3D (b) Silicon Interconnect ServiceLayer (SISL) for active interposer 2.5D

Similarly, interposers can be used as a platform to provideconnection between different die-based IPs. For example,Figure 9 shows the 2.5D interposer design with various IPcores sitting on top of an interposer. The ISL interconnectnetwork will be implemented on the interposer layer to pro-vide flexible and reusable interconnect architecture for IPcores which are sitting on top of the interposer.

Silicon Interposer Service Layer

IP DieIP Die

IP Die IP Die

Interposer

Micro-bump

TSV

C4 Bump

Interconnect

Routers moved to Active Interposer

Logic and Routers in IP Dies

Only Interconnect in Passive Interposer

Figure 9: Physical connections of 2.5D interposerwith ISL on-chip network

Note that since we propose to use an on-chip network withrouter design for the ISL, there will be active devices suchas logic gates on the ISL. For an interposer-based design,depending on the interposer type, one can implement theon-chip network router on the active interposer, or one canput only the metal routing on the passive interposer but putthe active devices for routers in the IP cores (thus reducingflexibility): (1) With current passive interposer technologies,which only have passive interconnect in order to minimizeprocess cost and maximize yield, flexible reconfiguration willrequire for each IP die to dedicate area for active routerhardware. (2) Alternatively, active interposers could be usedto provide a disaggregated interconnect network with activerouting hardware.

Such Silicon Interposer Service Layer (SISL) provides abase platform with a regular network structure and dedi-cated routers that can be employed to connect any IP diesthat are integrated onto the interposer. Dies are bonded

Silicon Interposer Service Layer

IP DieIP Die

IP Die IP Die

Interposer

Micro-bump

TSV

C4 Bump

Interconnect

Routers moved to Active Interposer

Logic and Routers in IP Dies

Only Interconnect in Passive Interposer

Figure 10: SISL implementations with passive andactive interposer technologies

to the interposer with micro-bumps at the top metal layer,so physical redesign of existing IP onto the SISL platformmay be small and could be achieved by altering only thetop metal masks. Active interposers are essentially largetraditional CMOS die, and as such do not benefit from thereduced wafer cost of passive interposer processes, but thesparse nature of the active die, with only a percentage ofactive area, means that yields may be very high despite thelarge area [7]. An example Silicon Interposer Service Layertopology is shown in Figure 8b. For both the 3D ISL and2.5D SISL platforms, the service layer may contain multi-ple superimposed heterogeneous networks to provide bettercommunication flexibility and to allow for unnecessary net-works to be gated for power. An SISL example is shown inFigure 11, where each node represents a logical connection,realized physically by multiple micro-bumps, between theinterposer network and the bonded IP die.

Figure 11: Example active network for SISL im-plementation: (a) 2x2 and 3x3 superimposed meshtopologies, (b) example overlay of IP blocks

6. CONCLUSIONAs modern process complexity increases, the effective cost

per transistor reduction is slowing and the cost per constantarea is increasing, especially when considering the growingoverhead of non-recurring costs like masks, design, and veri-fication. While traditional integration may be reaching costlimits, this paper demonstrates that die-level integration of-fers the opportunity to reduce costs through the effectivepartitioning of designs into multiple die in both TSV-based3D and interposer-based 2.5D integrated circuits. Addition-

ally, die-level integration offers new possibilities for heteroge-neous process integration and the reuse of intellectual prop-erty, allowing for additional cost benefits and the reductionin non-recurring costs through larger effective volume andreduced redesign effort by taking advantage of flexible inter-connect platforms.

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