Copyright © 2008 Heathkit Company, Inc. All Rights Reserved PC Fundamentals Presentation 24 –...
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Transcript of Copyright © 2008 Heathkit Company, Inc. All Rights Reserved PC Fundamentals Presentation 24 –...
Copyright © 2008 Heathkit Company, Inc. All Rights Reserved
PC FundamentalsPC Fundamentals
Presentation 24 – Computer MemoryPresentation 24 – Computer Memory
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Compare and contrast the following types of memory: RAM, SRAM, DRAM, SDRAM, VRAM, ROM, PROM, EPROM, and EEPROM.
Explain the difference between volatile and non-volatile memory.
Explain the purpose of cache memory. Compare and contrast the following types of
memory: SIMMs, DIMMS, DDR, and DDR2. Demonstrate the proper method to uninstall and
reinstall a single-inline memory module (DIMM). Demonstrate the proper method to uninstall and
reinstall a dual-inline memory module (DIMM).
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Describe the characteristics of the following types of memory and server memory requirements:– Memory Interleaving– ECC– Hardware Compatibility List
Define the following cache memories and explain how they work:– Processor cache– Disk cache
Explain the precautions required when upgrading memory.
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Define virtual memory.Define cache, cache hit, and cache miss.Explain how disk caching improves
performance.Describe the Least Recently Used (LRU)
cache algorithm, explain how it works, and list several applications in which it is most effective.
Describe the Read Ahead cache algorithm, explain how it works, and list several applications in which it is most effective.
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DRAM “forgets”DRAM “forgets”
Each DRAM bit is made up of a transistor and a capacitor.
Small capacitors lose their charge over time
Capacitors must be recharged
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Ch
arge
Ch
arge
Ref
resh
Ref
resh
Ref
resh
Ref
resh
Ref
resh
Ref
resh
Ref
resh
Ref
resh
TimeTime
Refresh boosts the charge
Refresh boosts the charge
Circuit loses its charge slowly
Circuit loses its charge slowly
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Synchronous DRAM… SDRAMSynchronous DRAM… SDRAM
Runs at the same speed as the main system bus.
Should be matched to the bus speed. Used in P2, P3, and some P4 systems
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Programmable Read-Only Programmable Read-Only Memory...PROMMemory...PROM
Non-Volatile Slow Difficult to Change Expensive
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45º
Centering Notch
Centering Notch
NotchedEnd
NotchedEnd
Rotate SIMM to about 45º
Rotate SIMM to about 45º
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AMIBIOS System Configuration (C) 1985-1995, American Megatrends Inc.,
Main Processor : Pentium(P54C)Math Processor : Built-InFloppy Drive A: : 1.44 MB 3½”Floppy Drive B: : NoneAMIBIOS Date : 07/15/95Processor Clock : 100MHzPower Management : Disabled
Base Memory Size: 640KBExt. Memory Size : 15360KBDisplay Type : VGA/EGASerial Port(s) : 3F8,3E8Parallel Port(s) : 378External Cache : 256KB,Enabled
Plug and Play ISA Devices:Analog Devices AD1816
Pci Devices:PCI Onboard IDE PCI Slot 2 VGA: IRQ 11
Bank 0: EDOBank 1: FP
Bank 0: EDO Bank 1: FP
Base Memory Size : 640KBExt. Memory Size : 15360KB
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DRAM vs. SRAM...DRAM vs. SRAM...DRAM vs. SRAM...DRAM vs. SRAM...
DRAM must be continually refreshed or it loses its memory.
DRAM is slow but inexpensive. SRAM is fast, does not require refreshing,
and holds its memory until power is removed.
SRAM is expensive.
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InterleavingInterleaving
Refreshing can be made more efficient by a memory design technique called Interleaving.
With Interleaving, memory is organized in banks. While a memory address in one bank is being refreshed, data is being retrieved from a memory address in another bank.
One stage gets the data from an address in a bank while at the same time the other stage refreshes an address in another bank.
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Memory OrganizationMemory OrganizationMemory OrganizationMemory Organization
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Column 1 2 3 4 5 6 7 8
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Fast Page Mode (FPM) DRAMFast Page Mode (FPM) DRAM
Memory is arranged into pages of from 512 to several kilobytes each.
All data on the page can then be accessed without relocating the page.
As long as the next piece of data needed is on the selected page, it can be accessed directly without going through the hassle of relocating the page.
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EDO (Extended Data Out) RAMEDO (Extended Data Out) RAMEDO (Extended Data Out) RAMEDO (Extended Data Out) RAM
With EDO memory, the processor takes With EDO memory, the processor takes the same time to make the first data the same time to make the first data access as it would with DRAM. But access as it would with DRAM. But once the EDO RAM finds that first once the EDO RAM finds that first
piece of data, it can send nearby bytes piece of data, it can send nearby bytes to the processor very quickly.to the processor very quickly.
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Synchronous DRAMSynchronous DRAMSynchronous DRAMSynchronous DRAM
Synchronous means that the DRAM and processor use the same clock. When the processor needs data, SDRAM can have it ready.
SDRAM may also use pipelines. One stage fetches the next memory address while another stage outputs data.
continued...
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Synchronous DRAM (continued)...Synchronous DRAM (continued)...Synchronous DRAM (continued)...Synchronous DRAM (continued)...
SDRAM has a burst counter that increments column addresses and speeds up burst accesses when next data is in the same row.
SDRAM goes to the memory address the processor wants and sends that data to the processor. It then continues “shooting” data from the memory locations after that to the processor until the processor says to quit.
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Synchronous DRAM (continued)...Synchronous DRAM (continued)...Synchronous DRAM (continued)...Synchronous DRAM (continued)...
Operates at speeds of 100 MHz and 133 MHZ. Operates at the full width of the processors data
bus. That is 64-bits (or 8 bytes) in the case of the Pentium.
Overall throughput is:– 8 bytes times 100MHz = 800 MB/sec– 8 bytes times 133MHz = 1 GB/sec– 8 bytes times 266MHz = 2 GB/sec– 8 bytes times 532MHz = 4 GB/sec– 8 bytes times 1066MHz = 8.5 GB/sec
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Rambus DRAM (RDRAM)Rambus DRAM (RDRAM)
Radically different memory design. It transfers only 16 bits (2 bytes) at a time,
but at a much higher speeds, typically 800MHz.
Throughput:– 2 bytes times 800MHz = 1.6 GB/sec
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Error Correction Code (ECC)Error Correction Code (ECC)
Corrects single bit errors. Detects, but cannot correct, 2-bit, 3-bit, and 4-
bit errors. Appends 8 additional bits on to every 64-bit
double word in main memory. The additional ECC bits are automatically
generated and stored along with the original 64 bits.
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Error Correction Code (ECC)Error Correction Code (ECC)
Later when the information is read back, the ECC bits are checked to make certain the information is still correct.
Memory with ECC protection is more expensive.
There is a slight speed penalty since some time is required to compute and then check the extra bits.
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CPU Registers
L1 Cache
L2 Cache
System Memory
Virtual Memory (Disk)
Network Virtual Memory
Speed Size
0.5ns <1kB
0.5ns
1ns
50ns
10millisecs
100millisecs
32kB
2MB
1GB
1TB
MultipleTerabyte
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Virtual MemoryVirtual Memory
Allows the Operating System (OS) to use disk space as if it were an extension of RAM.
Data can be swapped in and out of RAM from the disk.
It allows the maximum size of programs and data to be limited only by the combined size of both physical memory and available disk space.
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Caching – The technique of Caching – The technique of storing frequently-used or soon-storing frequently-used or soon-to-be-needed data in high-speed to-be-needed data in high-speed
memory so that it can be memory so that it can be accessed more quickly. accessed more quickly.
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Types of CachesTypes of Caches
High-speed memory caches that operate faster than normal system memory.
Disk caches using solid state memory that operates faster than disk drives.
Internet caches using disk drives that operate faster than Internet delivery.
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Processor CacheProcessor Cache
Level 1 or L1 cache – A small high speed memory cache that is built into the CPU core itself.
Level 2 or L2 cache – A high speed memory cache that is located outside the CPU core, but usually inside the same package as the CPU core. Typically, it is located as close as possible to the CPU. It is larger but slower than the L1 cache.
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Disk CachingDisk Caching
Speeds I/O transfers between the CPU and the disks.
Uses solid state memory and a cache controller.
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Cache Hits and MissesCache Hits and Misses
Hit - An I/O operation that retrieves data from the cache. Hits save time.
Miss - An I/O operation that fails to retrieve data from the cache. Misses waste time.
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Read AlgorithmsRead Algorithms
Least Recently Used (LRU) cache – Discards data from the cache if that data has not been used recently.
Read-ahead cache – Loads the cache with the data immediately following the data that was just read.
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Least Recently Used (LRU) Least Recently Used (LRU) CacheCache
Assumes that data that has not been used for a while probably won’t be needed in the near future.
Assumes that data that has been used recently will be used again.
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Applications benefiting from Applications benefiting from LRU CacheLRU Cache
Multi-user Database Applications Transaction Systems ERP Systems
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Read-ahead CacheRead-ahead Cache
Assumes that the next data that will be needed is that immediately following the data that was just read.
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Applications benefiting from a Applications benefiting from a Read-ahead cacheRead-ahead cache
Audio Video Graphics Multimedia File serving
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Upgrading Computer MemoryUpgrading Computer Memory
Verify hardware support for capacity increase.
Verify Operating System (OS) support for capacity increase.
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Upgrading Computer Memory Upgrading Computer Memory (Continued)(Continued)
Verify that memory is on the hardware vendor’s hardware compatibility list.
Verify that memory is on the OS vendor’s hardware compatibility list.
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Upgrading Computer Memory Upgrading Computer Memory (Continued)(Continued)
Verify memory compatibility– Speed– Brand– Type
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Upgrading Computer Memory Upgrading Computer Memory (Continued)(Continued)
When performing the upgrade use ESD best practices.
Verify that server and OS recognize the added memory