CoolRunner™-II Technology & Architecture

CoolRunner™-IITechnology & Architecture

Quick Start Training

Introducing CoolRunner-II

• 0.18 process technology• System voltage integration• Advanced design features

– Multiple I/O standards and I/O banks– Input hysteresis– Extra clocking modes

• Architecture allows design flexibility• Ultra low power using RealDigital technology• Allows CoolRunner full-CMOS circuitry to run at extremely low

power without compromising performance


High Level Architecture

Clock and Control Signals

I/O Blocks

I/O

I/O

I/O

FunctionBlock 1

AIM

Function Block n

I/O

I/O

I/O

I/O Blocks

16 16

16 16

4040

16 FB 16 FB

Direct Inputs Direct Inputs

MC1MC2

MC16

MC1MC2

MC16

PLA PLA


Function Block

• 16 macrocells available• 40 true and complement input signals from AIM• Global signals available at macrocell• Product terms add more clocks, OEs, S/Rs• Product term sharing allows very high fit rate• PLA architecture features excellent pinlocking


Function Block Architecture

PLA Array40x56

From AIM40

56 Product Terms

MC 1

MC 16

Global Clocks

Global Set/Reset

16

3

To I/O Block

Feedback to AIM


Macrocell Architecture

to I/O

FB Inputsfrom AIM

40

VCC

GNDS

R

D/T Q

CEPTC

from I/O Block (Direct Input) Feedback to AIM

PTACTRGSRGND

PTACTSGSRGND

PTC

PTA

PTB

4 Control Terms

49 P terms

CTCPTC

GCK

LatchDualEDGE

FIF

PLA Array

Macrocell

CK

application notes:http://www.xilinx.com/apps/epld.htm

PTA,B,CCTSCTRCTC

= programmable cell= product term signals= control term set= control term reset= control term clock

3


I/O Block Characteristics

I/O Pin

VREF

VCCIO

3.3V - 1.5V Input

EnabledControl Term

PTBGTS[0:3]

CGNDOpen Drain

Disabled

from Macrocell

Slewrate

Input Hysteresis

HSTL & SSTL

to Macrocell(Direct Input)

to AIM I/O Pin

VREF for Local Bank

Weak Pullup/Bus Hold

/4

128 macrocell

and larger devices

VCCIO


Reducing Power• Icc = C x V x f + Iddq

• To reduce power:– Lower capacitance– Lower voltage – Lower frequency

0.18 m lowers capacitanceLow VCC @ 1.8VHow can we reduce the frequency?

TraditionalSense Amp

Designs

Frequency

1.8 Volt (est)

2.5 Volt

3.3 Volt

~ 200MHz

~ 200mA

Note: 128 MC device estimate

~ 100mA

Icc


Clock Division

Global Clock

(GCK2)

ExternalSync

Reset

Clock Divide

By 2,4,6,…,16

DIV2

DIV4

DIV16

to FB 1

to FB n

Divide Select

• Gives solid clock division without using macrocells• Duty cycle improvement• Available in larger densities (128 macrocells and above)


DualEDGE Flip Flops

Advantages:• Distribute divided clock globally then double locally at macrocell

– Decrease Icc on global clock nets

• Use 2x clocking for double data rate (DDR) applications• No additional insertion delay

PTCGCK

CLK CT

PTC

to I/OD/T/L Q

CE

T FFLatch

DualEDGE

D

3


CoolCLOCK

Input Clock Input Clock DivideDivide

Device Device RoutingRouting

MacrocellMacrocell

GCK2

SyncReset

DIV2

MCClock Inputs

Divide by 2

D/T/L Q

TLatch

DualEDGE

D

GlobalDividedClock


DataGATE

• Available on all input pins (except JTAG pins)• Available for all I/O types• Selectable on a per pin basis• Data latch holds last valid pin value• DataGATE allows additional power savings

– Can be used to disable active board inputs• DataGATE can be also used for debugging and Hot Plug Input

Data Latch

to AIM

DataGATEAssertion Rail

InputPin

Configuration Bit


500mV Input Hysteresis

• Supports simple oscillation schemes • Ideal for slow edge rate, noisy

signals– Analog comparators & sensors– Hall effect switches– IR inputs– R/C oscillators

• Eliminate external Schmitt trigger buffers

• Reduces power consumption with slow signals

CoolRunner-II

+

_In

V


I/O Performance & FlexibilityXC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512

I/O Banks 1 1 2 2 4 4LVTTL 33

LVCMOS 33, 25, 18, 15*

SSTL3_I, SSTL2_I, HSTL_I

Input Hysteresis Option

Slew Rate Control

CoolCLOCK

DataGATE

DualEDGE flip flop

Clock Divider

Bus Hold output

Hot Pluggable

* 1.5V inputs need hysteresis


CoolRunner-II Applications

• Ideal for high speed designs:– High performance CPLD– Advanced features– Voltage translation for “free”– Double data rates

• Target device for portable designs:– Lowest power– Maximum battery life– Lower heat dissipation– Small packaging– Chip scale packaging


CoolRunner-II Family Overview

* Note: TPD

speeds are preliminary and 1.5V inputs need hysteresis

Features XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512Macrocells 32 64 128 256 384 512FToggle (MHz) 500 454 416 416 416 416

FSYSTEM (MHz) 385 270 263 238 217 217Max I/O 33 64 100 184 240 270

I/O Banks 1 1 2 2 4 4LVCMOS, LVTTL 1.5, 1.8, 2.5, 3.3 Yes Yes Yes Yes Yes Yes

HSTL, SSTL No No Yes Yes Yes YesDataGATE, DualEDGE No No Yes Yes Yes YesStandby Power (uW) 28.80 30.60 34.20 37.80 41.40 45.00

Multiple Levels of Security Yes Yes Yes Yes Yes Yes

Packages (size, type) VQ44 (10 x 10mm, leaded) 33 33 PC44 (16.5 x 16.5mm, leaded) 33 33 CP56 (6 x 6mm, chip scale) 33 45 VQ100 (14 x 14mm, leaded) 64 80 80 CP132 (8 x 8mm, chip scale) 100 106 TQ144 (20 x 20mm, leaded) 100 118 118 PQ208 (28 x 28mm, leaded) 173 173 173 FT256 (17 x 17mm, BGA) 184 212 212

Maxium User I/O


CPLD Software

http://www.xilinx.com/ise

• CoolRunner-II Software support– ISE WebPACK 5.2i– WebFITTER– Full feature support

• All Xilinx CPLDs supported!– CoolRunner-II– CoolRunner XPLA3– XC9500/XL/XV


IQ Solutions

• Multiple facets– Programmable products– IP cores– System solution boards

• PLD family members available in the range of -40°C to +125 C :

– Design services– eSP web portal– Customer education

Device Type

Spartan XL

XC9500 & XL

CoolRunner XPLA3

Spartan-II

CoolRunner-II

Spartan-IIE

XCS05XL, XCS10XL, XCS20XL, XCS30XL, XCS40XLXC9536XL, XC9572XL

XCR3032XL, XCR3064XL, XCR3128XL, XCR3256XL, XCR3384XL, XCR3512XL

XC2S15, XC2S30, XC2S50, XC2S100, XC2S150, XC2S200

Q1CY03

Q1CY03


• Silicon performance of Xilinx FPGAs with the single-chip integration of CPLDs

• Architecture combines 9500-style macrocell with XPLA3’s PLA for best silicon/software efficiency

• Industry leadership in:– High performance– I/O standards– Clock management capability– Low-power features

• Uncompromised performance at 1.8 volts

CoolRunner-II Technology Summary


Appendix


• Traditional CPLDs - bipolar sense amp product terms– Always consumes power

– Even at standby– Performance is traded for

power consumption as devices get larger

• CoolRunner-II RealDigital design uses 100% CMOS for product terms– Virtually no standby current– Combines high performance &

ultra low power– No power limits on device size

RealDigital Design Advantage

RealDigital : CMOS Everywhere - Zero Static Power

C

BA

D

Sense amplifier 0.25mA each - Standby Higher ICC at Fmax

A B C

Turbo vs Non TurboLarger R = slower response

& less powerVcc


Logic Optimization

Common logic may be shared in CoolRunner-II

X = A & B # CY = A & B # !C

PLAPLA: Requires only 3 pt’s!B CA

X Y

B CA

X YCan NOT share common logic

PAL: Requires 4 pt’s!

Indicates ‘unused’ junctionIndicates ‘fixed’ junction

Indicates ‘used’ junction


DDR SDRAM Interface

Address

Data

Control

DDRSDRAMP

• DualEDGE facilitates DDR• Utilizes SSTL interface


System Voltage Integration

CoolRunner-II featuresflexible I/O banking

1.5V1.5VPP

1.8V1.8VI/OI/O

3.3V3.3VSRAMSRAM

2.5V2.5VFlashFlash


PDA

SPI

SMBus

Battery

IrDALED

UART Docking Cradle

TouchscreenKeypad

P

LCD

Flash SRAMCompact

Flash


Web Tablet

SmartBattery

Tablet ID

ADC

RF Module

SDRAM High EndProcessor

LCDPanel

TouchScreen

CompactFlash/

Expansion

HIB

PWM

ISA Bus

SPI

SMBus


Low Power Clock Divide• Input signals: global clock (GCK2) & external sync reset• Control bits: enable/disable, & delay bit• Divide by n (2, 4, 6, 8, 10, 12, 14, or 16)

1st

Global CLK2

Sync Reset

Divide by 2 Delay bit = 0(No delay)Divide by 16

3rd 5th 7th 9th 17th

Divide by 2

Divide by 16

Clock Cycles

Delay bit = 1(Delay enabled)


DualEDGE Performance

Without DualEDGE

1st

External CLK

2nd 3rd 4th 5th

Din

Output

Clock Cycles

Internal Clock Doubler

Din

Output

With DualEDGE

Twice the performance of the system clock with double data rate


ODD CLOCKS with DualEDGE and CLOCK Divider

• Clock Divider gives ÷ 2,4,6,8,10,12,14,16• Dual EDGE double response• ODD CLOCKS at DualEDGE Flip Flops

÷ 7 ÷ 14 x 2÷ 5 ÷ 10 x 2÷ 3 ÷ 6 x 2


Multiple CLOCKS with One Global net

• Example:– GCK2 @ pin ÷ 8 distributes to Global Net

• Some flops accept CLOCK, respond to ÷ 8 • Some DualEDGE Flip Flops respond to ÷ 4

CoolRunner™-II Technology & Architecture

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