CONTROL UNIT OPERATION

MICROPROGRAMMED CONTROL

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Control Unit

Memory

ALU

Input Output

DataTransfer

Process

Input Output

Control Unit characterization:Define the basic elements of the processordescribe the micro-operations that the

processor performsDetermine the functions that the control

unit must perform to cause the micro-operations to be performed.

Types of micro-operations:Transfer data between registersTransfer data from register to externalTransfer data from external to registerPerform arithmetic or logical ops

SequencingThe CU causes the CPU to step through a

series of micro-operations in the proper sequence, based on the program being executed.

ExecutionThe CU causes each micro-operation to be

performed.

This is done using Control Signals

The inputs Clock – this is how the control unit “keeps time”

Instruction register – the opcode of the current instruction is used to determine which micro-operations to perform during the execution cycle.

Flags – These are needed by the control unit to determine the status of the processor and the outcome of the previous ALU operations.

Control signals from control bus – the control bus portion of the system bus provides signals to the control unit.

The outputs: Control signals within the processor – those that cause

data to be moved from one register to another, and those that activate specific ALU functions.

Control signals to control bus – control signals to memory, control signals to I/O modules

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Hardwired Sequential circuits Generating fixed sequence of control signals Implemented using standard digital logic design Pro: fast and small (total number of components) Con: changes of CU is difficult, requires a new

implementation Used in RISC system

Microprogramming The values of the control signal for each task are

stored in a control memory Control memory is accessed sequentially Advantages: systematic, easy for modification Disadvantages: required more components, slow

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In addition to the use of control signals, each microoperation is described in symbolic notation, a language known as micropgramming language.

Each line describes a set of micro-operations occuring at one time and is known as a microinstructions.

A sequence of instructions is known as a microprogram, or firmware. Midway between hardware and software.

Microinstructions could be arranged in a control memory.

Defines the sequence of micro-operations to be performed during each cycle, and it specifies the sequencing of these cycles.

Each routine ends with a branch or jump instruction indicating where to go next.

Has a wide word width due to the large number

of control points to be manipulated

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Control memory contains a program that describes the behavior of the CU.

The set of microinstructions is stored in the control memory.

The control address register contains the address of the next microinstruction to be read.

When a microinstruction is read from the control memory, it is transferred to a control buffer register.

A sequencing unit loads the control address register and issues a read command.

Sequence logic unit issues read command.

Word specified in control address register is read into control buffer register.

Control buffer register contents generates control signals and next address information.

Sequence logic loads new address into control buffer register based on next address information from control buffer register and ALU flags.

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Depending on ALU flags and control buffer register

Get next instruction

Add 1 to control address register

Jump to new routine based on jump microinstruction

Load address field of control buffer register into control address register

Jump to machine instruction routine

Load control address register based on opcode in IR

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Are more systematic with a well defined format.

Can be easily modified during the design process.

Require more components to implement.

However, tend to be slower than hardwired units (due to having to perform memory read operations)

Transformation of opcode to microinstruction

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opcode operand

Fetch cycle routine

Indirect cycle routine

Additionroutine

Subtractionroutine

instruction

Control Memory

Method 1: Direct Mapping

An instruction has 4 bit opcode and a control memory of the size 128 words. Each opcode has its own microprogram routine.

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1011 operand

0 1011 00

0 xxxx 00

Instruction

Mapping bit

Starting address of microroutine

Control address register

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OP-codes of Instructions ADD AND LDA STA BUN

00000001001000110100

Direct Mapping

Address10 0000 010

10 0001 010

10 0010 010

10 0011 010

10 0100 010

MappingBits 10 xxxx 010

ADD Routine

AND Routine

SUB Routine

MOV Routine

JMP Routine

Method 2:

Using ROM to mapping function

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1011 operand

ROM Control address register

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Microinstruction Format

EA is the effective address

Symbol OP-code Description

ADD 0000 AC AC + M[EA]BRANCH 0001 if (AC < 0) then (PC EA)STORE 0010 M[EA] ACEXCHANGE 0011 AC M[EA], M[EA] AC

Machine instruction format I Opcode15 14 11 10

Address

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Sample machine instructions

F1 F2 F3 CD BR AD3 3 3 2 2 7

F1, F2, F3: Microoperation fieldsCD: Condition for branching BR: Branch fieldAD: Address field

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F1 Microoperation Symbol

000 None NOP

001 AC AC + DR ADD

010 AC 0 CLRAC

011 AC AC + 1 INCAC

100 AC DR DRTAC

101 AR DR(0-10) DRTAR

110 AR PC PCTAR

111 M[AR] DR WRITE

F3 Microoperation Symbol

000 None NOP

001 AC AC DR XOR

010 AC AC’ COM

011 AC shl AC SHL

100 AC shr AC SHR

101 PC PC + 1 INCPC

110 PC AR ARTPC

111 Reserved

F2 Microoperation Symbol

000 None NOP

001 AC AC - DR SUB

010 AC AC DR OR

011 AC AC DR AND

100 DR M[AR] READ

101 DR AC ACTDR

110 DR DR + 1 INCDR

111 DR(0-10) PC PCTDR

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CD Condition Symbol Comments00 Always = 1 U Unconditional branch01 DR(15) I Indirect address bit10 AC(15) S Sign bit of AC11 AC = 0 Z Zero value in AC

BR Symbol Function

00 JMP CAR AD if condition = 1

CAR CAR + 1 if condition = 0

01 CALL CAR AD, SBR CAR + 1 if condition = 1

CAR CAR + 1 if condition = 0

10 RET CAR SBR (Return from subroutine)

11 MAP CAR(2-5) DR(11-14), CAR(0,1,6) 0

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Address Binary Microinstruction Micro Routine Decimal Binary F1 F2 F3 CD BR AD

ADD 0 0000000 000 000 000 01 01 1000011 1 0000001 000 100 000 00 00 0000010

2 0000010 001 000 000 00 00 1000000

3 0000011 000 000 000 00 00 1000000

BRANCH 4 0000100 000 000 000 10 00 0000110 5 0000101 000 000 000 00 00 1000000 6 0000110 000 000 000 01 01 1000011 7 0000111 000 000 110 00 00 1000000

STORE 8 0001000 000 000 000 01 01 1000011 9 0001001 000 101 000 00 00 0001010 10 0001010 111 000 000 00 00 1000000 11 0001011 000 000 000 00 00 1000000

EXCHANGE 12 0001100 000 000 000 01 01 1000011 13 0001101 001 000 000 00 00 0001110 14 0001110 100 101 000 00 00 0001111 15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001 65 1000001 000 100 101 00 00

1000010 66 1000010 101 000 000 00 11 0000000

INDRCT 67 1000011 000 100 000 00 00 1000100 68 1000100 101 000 000 00 10 0000000

A system uses a control memory of 1024 words of 32 bits each. The microinstruction has three fields and a 16-bit microoperations.

a. How many bits are there in the branch address field and the selection field?

b.If there are 16 status bits in the system, how many bits of the branch logic are used to select a status bit?

c.How many bits are left to select an input for the multiplexers?

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a.Control memory has 1024 words (210).Therefore required 10-bit address for each word ie address field = 10 bits

Select field = 32 – (16 + 10) = 6 bits.

b.16 (24) status bit therefore required 4 bits for the branch logic.

c. Number of bits for multiplexer = 6 – 4 = 2 bits.

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select address microoperationsMicroinstruction:

32 bit

16 bit16 bit