COMS 361 Computer Organization

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COMS 361Computer Organization

Title: Memory and MultiplicationDate: 11/09/2004Lecture Number: 18

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Announcements

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Review

• Logic design– Decoder– Multiplexor– PLA– Simple ALU

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Outline

• Memory elements– SR flip-flop (unclocked)– D Latch (clocked)– D flip-flop (clocked)– Master-Slave flop-flops– Clock

• Multiplication• Floating point numbers

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Memory Elements

• Store a state– Latches (level triggered)– Flip-flops (edge triggered)– Register files

• Latches– Output is the value of the stored state– Simplest

• Unclocked• SR latch (set-reset)

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SR Latch

• R = S = 0 – The output Q is its previous value– NOR gates act as inverters (homework)– If Q is asserted (1)

• Bottom inverter output is unasserted (0)• Input to the top inverter • Q remains asserted (1)

R

S Q

Q

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SR Latch

• R = 0, S = 1– Q = 1– Input to the top inverter (R) is 0

• Output Q = 1– Input to bottom inverter is 1

• Output Q’ = 0– Both inputs to the top inverter are 0, Q = 1

R

S Q

Q

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SR latch

• R = 1, S = 0– Q = 0– Input to the top inverter (R) is 1

• Output Q = 0– Input to bottom inverter is 0

• Output Q’ = 1– Both inputs to the top inverter are 1, Q = 0

R

S Q

Q

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SR latch

• R = S = 1– Unstable

R

S Q

Q

R S Q Q’

0 0 Q Q’

0 1 1 0

1 0 0 1

1 1 ? ?

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Memory Elements

• Clocked– Additional input (clock)– State changes are triggered by the clock– Flip-flop

• Changes state on the leading or falling clock edge– Clocked Latch

• Changes state when– Inputs change appropriately– Clock is 1

– We will use flip-flops (an edge triggered scheme)– Built from latches

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Memory Elements

• D latch– Simple memory element

• Stores the value of its input– Two inputs

• Data value to be stored (D)• Clock (C)

– Indicates when the data value (D) is read and stored

– Two outputs• Stored value • Stored value complement

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Clock

Logic 0

Logic 1

clock period

Clock high

Clock low

Falling edgeRising edge

unasserted

asserted

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D latch

C

DQ

Q

– C = 1• Latch is open• Output (Q) becomes the value on input D

– C = 0• Latch is closed• Output is the stored value

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D latch• Timing diagram

– Shows temporal relationship among elements

– Q takes on the value of D when C is asserted (1)• Said to be a transparent latch

– Q holds its value when C is not asserted (0)

D

C

Q

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D flip-flop• State changes only on the clock edge

– Can be the rising or falling edge– Built from two D latches

• Master and slave

DC

Q DC

QQ

C

D

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D flip-flop– When C is asserted

• Master is open• Follows the D input

– When C is unasserted• Master is closed• Slave is open• Stores the output from the master

DC

Q DC

QQ

C

D

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D flip-flop

D

C

Q

DC

Q DC

QQ

C

D

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D flip-flop• Circuit diagrams do not show the flip-flop

details

D

C

Q D Q

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Memory elements

• Set-up time– Time data must be stable before the clock comes

• Hold time– Time data must be stable after the clock comes

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Multiplication

• Multiplication Hardware– Implements simple algorithm

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Multiplication

• More complicated than addition– Accomplished via shifting and addition– 3 versions based on grade school algorithm

0010 (multiplicand)

x 1011 (multiplier)

0010 (intermediate product)00100 (intermediate product)000000 (intermediate product)

0010000 (intermediate product) 0010110 (sum of intermediate products)

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Multiplication (version 1)

• Product size– Multiplicand size + multiplier size– MIPS product 64 bits

• Accumulate product term by term– Terms

• Intermediate products– Left shifted multiplicand– All zeros– Determined by the bit pattern of the multiplier

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Done

1. TestMultiplier0

1a. Add multiplicand to product andplace the result in Product register

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1

No: < 32 repetitions

Yes: 32 repetitions

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• Left shifted multiplicand– Multiplicand register size must be at least

• Multiplicand bits + multiplier bits long– ALU size same as the multiplicand register

64-bit ALU

Control test

MultiplierShift right

ProductWrite

MultiplicandShift left

64 bits

64 bits

32 bits

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0000 0010x 1011

0000 0010

0000 0100

0000 0100x 0101

+ 0000 00100000 0110

0000 0000

0000 1000x 0010

+ 0000 01100000 0110

0001 0000

0001 0000x 0001

+ 0000 01100001 0110

0001 0110

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• At least half the multiplicand bits are zero– Waste to make a 64 bit adder– Left shift inserts zeros on the right end of

multiplicand– Right part of the product will not change– Shift the product register right instead– Fixes the multiplicand

• 32 bits– Multiplicand register– ALU

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Done

1. TestMultiplier0

1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1


Yes: 32 repetitions

MultiplierShift right

Write

32 bits

64 bits

32 bits

Shift right

Multiplicand

32-bit ALU

Product Control test

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0010x 1011

0010 0000+ 0000 0000

0010

0010 00000001 0000

x 0101

0010 00000001 0000

0011 00000001 1000

0010x 0010

0000 00000001 10000001 10000000 11000010

0010 00000000 1100

x 0001

0010 11000001 0110

0001 0110

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• Product register has unused space– Large enough to hold the multiplier– As unused bits are filled

• Multiplier requires less bits– Initialize product register

• Zeros in the left half• Multiplier in the right half

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Done

1. TestProduct0

1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

32nd repetition?

Start

Product0 = 0Product0 = 1


Yes: 32 repetitions

ControltestWrite

32 bits

64 bits

Shift rightProduct

Multiplicand

32-bit ALU

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