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Computer OrganizationComputer OrganizationToday:

• First Hour: Computer Organization–Section 11.3 of Katz’s Textbook

– In-class Activity #1

• Second Hour: Test Review

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Note, the BUS is treated just like a register

Note, the BUS is treated just like a register

Register Transfer OperationsRegister Transfer Operations

Register transfer operations:Register transfer operations:

PC BUSIR BUSAC BUSMBR BUSALU Result BUS

BUS PCBUS IRBUS ACBUS MBRBUS ALU BBUS MAR

AC ALU A(hardwired)

Memory Address

Bus

Memory Data BusM

A R

P C

I R

A C

A

B

M B R

BUS

Single Bus DesignSingle Bus Design

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More Realistic Datapath UnitMore Realistic Datapath UnitThree Bus Design — Supports more parallelismThree Bus Design — Supports more parallelismThree Bus Design — Supports more parallelismThree Bus Design — Supports more parallelism

Single bus replaced by three busses:Single bus replaced by three busses: Memory Bus (MBUS)Result Bus (RBUS)Address Bus (ABUS)

Memory Bus (MBUS)Result Bus (RBUS)Address Bus (ABUS)

Address Bus

M A R

P C

I R

Memory Address

Bus A C

A

B

M B R

Result Bus

Memory Bus

Memory Data Bus

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We simplified our datapath further by assuming that MBR is inside the memory system itself and MBUS has two branches. We simplified our datapath further by assuming that MBR is inside the memory system itself and MBUS has two branches.

Add MemoryAdd Memory

Every device in this diagram has control signals that must be operated.Every device in this diagram has control signals that must be operated.

RBUS

ACMBUS

A B

ALU

MemoryN bits wide2M words

MARS

PCIR

MBUS

MemoryAddress

ABUS

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Add ControlAdd Control

AC

A B

ALUMAR

S

PC

FSM

IR

MemoryAddress

Opcode

The control unit is a finite The control unit is a finite state machine (FSM).state machine (FSM).

Every bit of the Instruction Instruction RegisterRegister (IR), every other register’s OE and LOAD signals, every control input and flag output of the ALU, and every memory control signal is either an input or an output of the control unit.(Shown in red)

Reality Note #1:The control unit FSM is huge compared to the FSM examples that we’ve seen thus far!!

Reality Note #2: The diagram above is extremely simplified compared to a real processor

Reality Note #1:The control unit FSM is huge compared to the FSM examples that we’ve seen thus far!!

Reality Note #2: The diagram above is extremely simplified compared to a real processor

Control FlowData Flow

RBUS

MBUS

MemoryN bits wide2M words

MBUS

ABUS

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How does it work? (1)How does it work? (1)

3. Operand Fetch: Move operand address from IR to MAR Initiate a memory read sequence

Store Path

ACLoad Path

A B

ALU

MemoryN bits wide

2M words

MARS

PC

FSM

IR

Instruction Path

MemoryAddress

Opcode

OPCODE OPERANDSPECIFIER

Instruction Format

Let's trace an instruction: AC AC + Mem<address>

1. Instruction Fetch:Move PC to MARInitiate a memory read sequenceMove data from memory to IR

2. Instruction Decode: Opcode bits of IR are input to

control FSM Rest of IR bits encode the

operand address

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How does it work? (2)How does it work? (2)Store Path

ACLoad Path

A B

ALU

MemoryN bits wide

2M words

MARS

PC

FSM

IR

Instruction Path

MemoryAddress

Opcode

OPCODE OPERANDSPECIFIER

Instruction Format

4. Instruction Execute:Data available on load pathMove data to ALU input Configure ALU to perform ADD operationMove result S to AC

5. Housekeeping:Update PC to point at next instruction

Let us trace an instruction: AC AC + Mem<address>

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The Control UnitThe Control Unit

What the Control unit is doing:

Transfers data from one register to another Asserts appropriate control signals

We can think about the control unit most easilyin terms of a series of register transfers, using a programming-like notation

Register transfer notation - A way to represent the detailedimplementation of register transfer operations

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Register to Register movesRegister to Register moves

Register Transfer NotationRegister Transfer Notation

Instruction fetch: PC MAR; -- move PC to MARMemory Read; -- assert Memory READ signalMemory IR; -- load IR from Memory

Instruction Decode: IF IR<op code> = ADD_FROM_MEMORYTHEN

Instruction Execution: Memory ALU B; -- gate Memory to ALU BAC ALU A; -- gate AC to ALU AALU ADD; -- instruct ALU to perform ADDALU S AC; -- gate ALU result to AC

Assert ControlSignal

Assert ControlSignal

Operand fetch: IR<addr> MAR; -- move operand addr to MARMemory Read; -- assert Memory READ signal

Housekeeping: PC+1 PC; -- increment PC

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Micro-OperationsMicro-Operations

Instruction fetch: PC ABUS;ABUS MAR;1 Read/Write*;MBR MBUS;MBUS IR;

Instruction Decode: IF IR<OpCode> = LOAD_FROM_MEMORYTHEN

Instruction Execution: MBR MBUS;MBUS ALU B;ALU PASS B;ALU Result RBUS;RBUS AC;

Operand fetch: IR<addr> MAR;1 Read/Write*;

Housekeeping: PC+1 PC;

Instruction FetchInstruction Fetch

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Micro-operationsMicro-operations

One register transfer operation may be several micro-operations

Some operations are directly implemented by functional units:

e.g., ADD, Pass B, 0 PC, PC + 1 PC

Some others require multiple control operations:

e.g., PC MAR implemented as PC ABUS and ABUS MAR

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Do Activity #1 NowDo Activity #1 Now

AC

A B

ALUMAR

S

PC

FSM

IR

MemoryAddress

Opcode

Control FlowData Flow

RBUS

MBUS

MemoryN bits wide2M words

MBUS

ABUS

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RETAIN THE LAST PAGE(S) (#3 onwards)!!

For Next Class:• Bring Huang 68HC11 Textbook

• Required Reading:– Chap 1 of the Huang 68HC11 book

• This reading is necessary for getting points in the Studio Activity!