Computer Architecture & System Buses

8/12/2019 Computer Architecture & System Buses

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UNIT 3

CHAPTER 1

INTRODUCTION TO COMPUTER ORGANIZATION

Lesson 14COMPUTER ORGANIZATION & SYSTEM BUSES

Computer Organization & System BusesThe instruction set architecture, described in earlier provides a good description of

what a microprocessor can do, but it provides virtually no information on how to use

the microprocessor. The ISA describes the instructions that the microprocessor can

process, but says nothing about how the processor accesses these instructions. A

system designer needs more information than the ISA provides in order to design a

complete computer system.

In this chapter, we examine the organization of basic computer systems. A

simple computer has three primary subsystems. The central processing unit, or

CPU, performs many operations and controls the computer. A microprocessor

usually serves as the computers CPU. The memory subsystem is used to store

programs being executed by the CPU, along with the programs data. The

input/output, or I/O, subsystem allows the CPU to interact with input and output

devices, such as the keyboard and monitor of a personal computer, or the keypad and

digital display of a microwave oven.

This chapter begins with an overview of basic system organization, including

the system buses used by the CPU, memory subsystem, and I/O subsystem to

communicate with each other. Next, we examine the three system components inmore detail. We describe the functionality and organization of each component, as

well as its interface with the rest of the computer system. Finally we look at the

organization of two computer systems, one based on the Relatively Simple CPU,

introduced in Chapter 3, and another based on Intels 8085 microprocessor. In later

chapters, we examine the subsystems and system architecture in greater detail.

BASIC COMPUTER ORGANIZATION

Most computer systems, from the embedded controllers found in automobiles and

consumer appliances to personal computers and mainframes, have the same basic

organization. This organization has three main components: he CPU, the memorysubsystem, and the I/O subsystem. We discuss each of these components in more

detail later in this chapter. The generic organization of these components is shown in

Figure 4.1.

Figure 4.1

Generic computer organization


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In this section, we first describe the system buses used to connect the components in

the computer system. Then we examine the instruction cycle, the sequence of

operations that occurs within the computer as it fetches, decodes, and executes an

instruction.

SYSTEM BUSES

Physically, a bus is a set of wires. The components of the computer are connected to

the buses. To send information from one components to another, the source

component outputs data onto the bus. The destination component then inputs this data

from the bus. As the complexity of a computer system increases, it becomes more

efficient (in terms of minimizing connections) at using buses rather than directconnections between every pair of devices. Buses use less space on a circuit board

and require less power than a large number of direct connections. They also require

fewer pins on the chip or chips that comprise the CPU.

The system shown in Figure 4.1 has three buses. The uppermost bus in this

figure is the address bus. When the CPU read data or instructions from or writes data

to memory, it must specify the address of the memory location it wishes to access. It

outputs this address to the address bus; memory inputs this address from the address

bus and uses it to access the proper memory location. Each I/O device, such as a

keyboard, monitor, or disk drive, has a unique address as well. When accessing an I/O

device, the CPU places the address of the device on the address bus. Each device can

read the address off of the bus and determine whether it is the device being accessed


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information and the rest of the time they carry data bus information.) The remaining

lines incorporate control bus signals and signals used for error checking and reporting,

as well as signals to support cache memory and interrupts.

Lets start where the computer starts, with the microprocessor fetching the instruction

from memory. First, the microprocessor places the address of the instruction on to the

address bus. The memory subsystem inputs this address and decodes it to access thedesired memory location.

After the microprocessor allows sufficient time for memory to decode the address and

access the requested memory location, the microprocessor asserts a READ control

signal. The READ signal is a signal on the control bus, which the microprocessor

asserts when it is ready to read data from memory or an I/O device. (Some processors

have a signal to perform this function.) Depending on he microprocessor, the READ

signal may be active high (asserted = 1) or active low (asserted = 0).

When theREADsignal is asserted, the memory subsystem places the instruction code

to be fetched onto the computer systems data bus. The microprocessor then inputs

this data from the bus and stores it in one of its internal registers. At this point, the

microprocessor has fetched the instruction.Next, the microprocessor decodes the instruction. Each instruction may require a

different sequence of operations to execute the instruction. When the microprocessor

decodes the instruction, it determines which instruction it is in order to select the

correct sequence of operations to perform. This is done entirely within the

microprocessor; it does not use the system buses.

Finally, the microprocessor executes the instruction. The sequence of operations to

execute the instruction varies from instruction to instruction. The execute routine may

read data from memory, write data to memory, read data from or write data to an I/O

device, perform only operations within the CPU, or perform some combination of

these operations within the CPU, or perform some combination of these operations.

We now look at how the computer performs these operations from a system

perspective.

To read data from memory, the microprocessor performs the same sequence of

operations it uses to fetch an instruction from memory. After all, fetching an

instruction is simply reading it from memory. Figure 4.2(a) shows the timing of the

operations to read data from memory.

Figure 4.2

Timing diagrams for (a) memory read and (b) memory write operations


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In Figure 4.2, notice the top symbol, CLK. This is the computer system clock; the

microprocessor uses the system clock to synchronize its operations. the

microprocessor places the address onto the bus at the beginning of a clock cycle, a 0/1

sequence of the system clock. One clock cycle later, to allow time for memory to

decode the address and access its data, the microprocessor asserts the READ signal.This causes memory to place its data onto the system data bus. During this clock

cycle, the microprocessor reads the data of the system bus and stores it in one of is

registers. At the end of the clock cycle it removes the address from the address bus

and deasserts the READ signal. Memory then removes the data from the data bus,

completing the memory read operation.

The timing of the memory write operation is shown in Figure 4.2(b). The processor

places the address and data onto the system buses during the first clock cycle. The

microprocessor then asserts a WRITEcontrol signal (or its equivalent) at the start of

the second clock cycle. Just as the READ signal causes memory to read data, the

WRITE signal triggers memory to store data. Some time during this cycle, memory

writes the data on the data bus to the memory location whose address is on the addressbus. At the end of this cycle, the processor completes the memory write operation by

removing the address and data from the system buses and deasserting the WRITE

signal.

The I/O read and write operations are similar to the memory read and write

operations. Recall from Chapter 3 that a processor may use either memory mapped

I/O or isolated I/O. If the processor supports memory mapped I/O, it follows the

same sequences of operations to input or output data as to read data from or write date

to memory, the sequences shown in Figure 4.2. (Remember, in memory mapped I/O,

the processor treats an I/O port as a memory location, so it is reasonable to treat an

I/O data access the same as a memory access.) Processors that use isolated I/O can

have a memory location and an I/O port with the same address, which makes this

extra signal necessary.) For example, the 8085 microprocessor has a control signal

calledIO/M . The processor setsIO/Mto 0 for the entire length of a memory read or

write operation. For I/O operations, the processor setsIO/Mto 1 for the duration of

the I/O read or write operation.

Finally, consider instructions that are executed entirely within the microprocessor.

The INAC instruction of the Relatively Simple CPU, and the MOV i1, r2 instruction

of the 8085 microprocessor, can be executed without accessing memory or I/O

devices. As with instruction decoding, the execution of these instructions does not

make use of the system buses.


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STUDENT ACTIVITY

Answer the following questions:

1. Explain System Buses in detail.

2. What do you mean by instruction cycle.

3. Explain computer organization with diagram.


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Computer Architecture & System Buses

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