CMP For Direct Wafer Bonding of Hermetically Sealed Cavity ... · CMP to successfully pre-bond to...
Transcript of CMP For Direct Wafer Bonding of Hermetically Sealed Cavity ... · CMP to successfully pre-bond to...
CMP For Direct Wafer Bondingof Hermetically Sealed Cavity Structures
R.L. Rhoades (Entrepix) and R.B. Danzl (Medtronic)ECS Spring Meeting – Symposium E2May 25, 2009
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Outline
Introduction and Background
CMP Development for Direct Wafer Bonding
Post-CMP Cleaning Optimization
Pull Strength Testing and Hermiticity Results
Conclusions
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Introduction
• Direct Wafer Bonding (DWB)– Multiple types now available
– Surface preparation often includes CMP
– Cleaning steps are critical to ultimate DWB success
– Anneal is necessary to strengthen bonds
CMP / Clean
Activation
RT Bond
Anneal
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Types of Si DWB
Source: Kim and N
ajafi, University of M
ichigan, 2007
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3D Packaging Apps
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Hermetic Cavities
• Material contraints• Size constraints• Medical applications
– Implantable parts and components– Must survive hostile environment >7 years– Material constraints
• Why is this so different than 3D ??
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Why is CMP so critical?
• Highlight surface preparation importance• Key parameters: Flat, smooth, clean
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Guideposts for DWB
• Surface Roughness (Ra)< 0.5 nm 0.5 – 1.0 nm > 2.0 nmGood …… Usually ok ….. Poor
• Flatness or topography– No “bumps” sticking up from surface– Indents or cavities ok (preferably sharp corners)
• Surface cleanliness– Must be very clean and particle free– NO hydrocarbons
• Materials– Strongest bond is generally same-same material– Most common are oxide-oxide and Si-Si
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CMP Development
• Zoom in on CMP process development
• Assumes fundamentals of pad/slurry research are already done by suppliers
• Test wafer availability and quality often impact timeline, validity of results, etc.
• Initial process DOE’s generally focus on removal rate and gross surface quality
• Optimization stages can be interchanged or executed in parallel
• Planarity can mean step height, dishing, erosion, roughness, etc. depending on the material and intended application
• Failure at any stage usually means backing up at least one stage to try again
Consumables Screening
Process DOE's
Optimize Uniformity
Optimize Planarity
Optimize Defectivity
Stability (marathon)
Release for Device Qualification
CMP Development Sequence
Generate Test Wafers
Repeatability (multiple runs)
Screening Tests
Optimization
Repeatability
Marathon
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STORM
• Screening Tests
• Optimization
• Repeatability
• Marathon
STORMSTORM
A proven approachto successfullydeveloping newCMP processes
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CMP Experiments
• Included 3 types of substrates– Silicon wafers with grown thermal oxide layers– Silicon wafers with deposited TEOS films– Borofloat 33 glass (clear)
• Initial work performed on bare substrates and blanket film wafers to understand materials independent of pattern effects
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CMP – Thermal Oxide
Test Inputs• Thermal oxide films• IPEC 472 polisher• Klebosol silica slurry• IC1000 on Suba IV pad stack• Diamond pad conditioner
Outcome• Two pressures screened• Linear function of polish time• Surface roughness excellent at
all settings (Ra <1 nm)0
1000
2000
3000
4000
5000
6000
7000
0 20 40 60 80 100 120 140
Polish Time (seconds)
Ther
mal
Oxi
de R
emov
ed (A
ng)
Removed (low pressure)
Removed (med pressure)
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CMP – Borofloat 33 Glass
Test Inputs• Substrates of Borofloat 33• IPEC 472 polisher• Klebosol silica slurry• IC1000 on Suba IV pad stack• Diamond pad conditioner
Outcome• Same two pressures screened• Removal rate ~50% faster than
same process on thermal oxide• Multiple wafers per data point
shows excellent repeatability
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
0 20 40 60 80 100 120 140
Polish Time (seconds)
Bor
oflo
at 3
3 R
emov
ed (A
ng)
Removed (low pressure)
Removed (med pressure)
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CMP Issues with clear Borofloat 33 substrates
• Wafer metrology– Unable to use thin film metrology on clear wafers– Adapted “weight loss” technique for control
• Post-CMP clean– First attempts with OnTrak double-sided scrubber
failed due to sensors not “seeing” clear wafers– Developed modified sensor kits that now allow the
OnTrak DSS to process all wafers w/o error
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OnTrak Systems
Series II Classic or CE Synergy Synergy Integra
LoadStation
Dual Brush Module
Spin Station
UnloadHandler
User Interface
97.29 inches
28.56 inches
LoadStation
Dual Brush Module
Spin Station
UnloadHandler
User Interface
97.29 inches
28.56 inches
Chemical Dispense Manifold (Drip)
PVA Brush
DIW
Polyurethane Rollers
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OnTrak Sensor Issues
The system utilizes wafer sensors for feedback and control.
Typical config includes through beam sensing to detect the presence or passage of opaque substrates.
Clear substrates are not detected by through beam sensors nor standard capacitive sensors.
In dry environments, reflective sensors are a good solution.
Post cmp cleaning environment involves liquid sprays, highly polished metals and plastic surfaces, and other reflective surfaces which generate “noise” to the typical reflective sensor.
Tuning a standard reflective sensor to detect only the substrateand not the liquid overspray or materials was ineffective.
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Sensor Locations
Multiple Sensors:
Load station
Brush box #1
Brush box #2
Transfer carriage
Spin station
Unload station
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Sensors Resolved
New sensor types employed for clear wafers
1) Definite Reflective Sensors• Allows detection of a surface at a specific point (+\-.02”).• Mounted near to the product surface (1-2” preferred). • Uses a digital amplifier to suppress “noise” generated by
background surfaces or water droplets.
2) Retro-reflective Sensor• Enables longer distance sensing • Amplifies attenuation in received light even as it passes
through a clear surface.
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Definite Reflective
Definite Reflective SensorsThe most intense received light is reflected from the surface of the
product. Other received light can be tuned out using the amplifier
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Retro Reflective
Retro-reflective SensorWhen system constraints require longer distance sensing a polarized surface
mounted opposite the sensor assists in amplifying any attenuation in light caused by presence of the substrate.
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Pull Test Procedure
• Only performed on unpatterned bonded pairs (no device cavities) to test uniform bond strength
• Dicing saw used to cut 0.25”x0.25” samples• Posts bonded to each side with epoxy• Alliance RT/10 MTS Tensile Tester• Three common failure modes
– Bulk Fracture (FR)– Adhesive Failure (AF)– Bond Failure (BF)
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Dicing Damage
Edge chips may have contributed to some Si bulk fracture failures
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Bulk Fracture Failure
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Bond Interface Failure
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Pull Test Data
Table I. PULL TEST DATA (PSI) - BOROFLOAT GLASS WITH VARIOUS CMP FR=Bulk Fracture, AF=Adhesive Failure, BF=Bond Failure, L=Load Limit Sample Silicon Borofloat Borofloat Borofloat Borofloat 2.0umCMP 3um CMP 1 um CMP 0.45 um CMP 0.15 um CMP 1 1672 (FR) 2177 (FR) 2287 (AF) 1387 (AF) 1303 (AF) 2 1928 (AF) 2679 (FR) 2495 (AF) 3033 (FR) 3046 (AF) 3 2493 (FR) 2465 (FR) 3058 (L) 3058 (L) 2802 (AF) 4 3059 (L) 2137 (AF) 3059 (L) 3058 (FR) 3058 (L) 5 3059 (L) 2693 (FR) 2473 (AF) 3041 (FR) 297 (BF) 6 1286 (FR) 2380 (FR) 1433 (AF) 3058 (L) 2820 (AF) 7 1672 (FR) 2619 (AF) 2752 (AF) 2302 (BF) 8 857 (AF) 2452 (AF) 2714 (BF) Avg/Std 2430+/-265 2285 +/- 770 2729 +/- 584 2292 +/- 988
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Pull Test Implications
• Borofloat 33 wafers required at least some amount of CMP to successfully pre-bond to SiO2 at room temperature.
• Borofloat 33 wafers that were polished to remove at least 1um of material had fewer bond failures during pull tests.
• For the highest removal group (3um), bulk fracture of the Borofloat 33 was the most common pull test failure.– Possible residual stress from TCE mismatch during anneal– Possible inclusions or defects in the glass– Lower intrinsic fracture strength than single crystal silicon
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CMP on Cavity Wafers
Test Inputs• Cavities patterned in Si wafers
than coated in oxide• IPEC 472 polisher• Klebosol silica slurry• IC1000 on Suba IV pad stack• Diamond pad conditioner
Outcome• Range of processes studied for
impact on cavity edges• Relatively linear response
across range of CMP index (confirms Prestonian behavior)
• High pressure settings showed more edge rounding
0
500
1000
1500
2000
2500
0 50 100 150 200 250
CMP Index (Pressure * Table Speed)
Rem
oval
Rat
e (A
ng/m
in)
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Sealed Cavity
Excellent bond – no evidence of separation along interface
Cavities were fabricated across a range of CMP processes and total removal using both Borofloat 33 cap wafers and Si cap wafers with an oxide film.
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He Leak Rate Tests
• Cavities singulated and checked for integrity• Placed in pressurized He chamber for >48 hrs• Generalized leak rate test method
– Establish initial baseline (empty chamber pump cycles)– Measure two data points per sample– Repeat baseline at end of test– No sample is allowed out of pressurized He chamber for
more than 2 hours• Test method compatible with MIL-STD-883
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Cavities in Si with SiO2 on Si wafer cap
Observations• Stable baseline leak rate for
empty chamber < 1E-12• Pink line is calculated
threshold per XXXX equation (well below MIL-STD-883)
• Each sample was tested twice in succession for repeatability
• Chamber returned to baseline
Summary• One cavity failed• One cavity was borderline• Twenty-four (24) cavities
passed with substantial margin
Hermetic Testing 10/11/08
EM
PTY
CH
AM
BE
RE
MP
TY C
HA
MB
ER
EM
PTY
CH
AM
BE
RE
MP
TY C
HA
MB
ER
EM
PTY
CH
AM
BE
R1.
25 1.25
1.26
1.26
1.27
1.27 1.
361.
361.
371.
37 1.39
1.39
1.4
1.4
1.41
1.41
1.43 1.43
1.25 1.25
1.26
1.26
1.27
1.27
1.26 1.26
1.44 1.
44 1.45
1.45
1.46
1.46 1.47
1.47 1.
481.
481.
49 1.49 1.5
1.5 1.
511.
511.
52 1.52
1.53 1.
531.
541.
54 1.36 1.36
EM
PTY
CH
AM
BE
RE
MP
TY C
HA
MB
ER
EM
PTY
CH
AM
BE
RE
MP
TY C
HA
MB
ER
EM
PTY
CH
AM
BE
R1.00E-14
1.00E-13
1.00E-12
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
He
Leak
Rat
e at
m-c
c/s
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Cavities in Si with borofloat glass cap
Hermetic Testing 10/08/08
empt
y ch
ambe
rem
pty
cham
ber
empt
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ambe
rem
pty
cham
ber
empt
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6.1
6.1
6.2
6.2
6.5
6.5
empt
y ch
ambe
rem
pty
cham
ber
6.9
6.9
6.14
6.14
6.15
6.15
6.18
6.18
6.24
6.24
6.29
6.29
6.36
6.36
empt
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ambe
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cham
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r
1.00E-14
1.00E-13
1.00E-12
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
Interim conclusion: Borofloat glass is more permeable than SiO2 on Si
Observations• Stable baseline leak rate for
empty chamber < 1E-12• Same size cavities as previous• Each sample was tested twice
in succession for repeatability• Chamber returned to baseline
Summary• 100x higher leak rate than
cavities capped with Si+SiO2• One cavity passed (unexpected
result given consistency of other samples in dataset)
• Eleven (11) cavities failed to this rigid standard (may still pass MIL-STD-883)
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Summary
• CMP removal rate is controllable over reasonable range of settings for both SiO2 and Borofloat 33
• Clear wafers require modification of the sensors in an OnTrak DSS-200 scrubber
• Hermetically sealed cavities can be fabricated using CMP and direct wafer bonding.
• Bond strength is improved when both surfaces are polished and properly cleaned.
• Hermeticity (cavity leak rate) is improved by using an oxidized Si cap wafer compared to borofloat glass
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Acknowledgements
• The authors would like to thank:– Paul Lenkersdorfer, Donna Grannis and Terry Pfau (Entrepix)– Mike Mattes, Jon Stamp, and Ann Malin (Medtronic)
• For additional information, please contact:
Ralph DanzlMedtronic, Inc.
Sr. Process Engineer480 929-5503
Rob RhoadesEntrepix, Inc.
Chief Technology Officer602 426-8668