CMOS Transistors

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CMOS Transistors

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CMOS Transistors. Outline. Qualitative Description of CMOS Transistor g m /I D Design Biasing a transistor Using g m /I D Approach Design Using Cadence. A Crude Metal Oxide Semiconductor (MOS) Device. V2 causes movement of negative charges, thus current. V1 can control the - PowerPoint PPT Presentation

Transcript of CMOS Transistors

Page 1: CMOS Transistors

CMOS Transistors

Page 2: CMOS Transistors

Outline

• Qualitative Description of CMOS Transistor

• gm/ID Design

• Biasing a transistor Using gm/ID Approach

• Design Using Cadence

Page 3: CMOS Transistors

A Crude Metal Oxide Semiconductor (MOS) Device

P-Type Silicon is slightly conductive.

Positive charge attractnegative chargesto interface between insulator and silicon.

A conductive path is createdIf the density of electrons is sufficiently high.Q=CV.

V2 causes movement of negative charges,thus current.

V1 can control the resistivity of the channel.The gate

draws no current!

Page 4: CMOS Transistors

An Improved MOS Transistor

n+ diffusion allowselectrons movethrough silicon.

(provide electrons) (drain electrons)

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Typical Dimensions of MOSFETs

These diode mustbe reversed biased.tox is made really thin

to increase C, therefore, create a strong control of Q by V.

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A Closer Look at the Channel Formulation

Need to tie substrate to GNDto avoid current through PN diode.

Positive charges repel the holescreating a depletion region, a region free of holes.

Free electrons appear at VG=VTH.

VTH=300mV to 500 mV(OFF) (ON)

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Channel Resistance

As VG increases, the density of electrons increases, the value ofchannel resistance changes with gate voltage.

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Drain Current as a function of Drain Voltage

Resistance determined by VG.

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Drain Current as a function of Gate Voltage

Higher VG leads to a lower channel resistance, therefore larger slope.

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Length Dependence

The resistance of a conductor is proportional to the length.

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Dependence on Oxide Thickness

Q=CVC is inversely proportional to 1/tox.

Lower Q implies higher channel resitsance.

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Width Dependence

The resistance of a conductor is inversely proportional to the crosssection area.

A larger device also has a larger capacitance!

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Channel Pinch Off• Q=CV– V=VG-VOXIDE-Silicon

• VOXIDE-Silicon can change along the channel! Low VOXIDE-Silicon implies less Q.

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VG-VD is sufficiently largeto produce a channel

VG-VD is NOT sufficiently largeto produce a channel

No channel

Electronsare sweptby E to drain.

Drain can no longer affect the drain current!

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Regions

No channel

(No Dependence on VDS)

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Determination of Region

• How do you know whether a transistor is in the linear region or saturation region?– If VDS>(VGS-VTH) and VGS>VTH, then

the device is in the saturation region.– If VDS<(VGS-VTH) and VGS>VTH, then

the device is in the linear region.

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Graphical Illustration

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Limited VDS Dependence During Saturation

As VDS increase, effective L decreases, therefore, ID increases.

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Pronounced Channel Length Modulation in small L

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Transconductance• As a voltage-controlled current source, a MOS transistor

can be characterized by its transconductance:

• It is important to know that

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What Happens to gm/ID when W and ID are doubled?

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Body Effect

The threshold voltage will change when VSB=0!

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Experimental Data of Body Effect

The threshold voltage will increase when VSB increases.

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Small Signal Model for NMOS Transistor

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PMOS Transistor

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IV Characteristics of a PMOS

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Small Signal Model of PMOS

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Small Signal Model of NMOS

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gm/ID Design Approach

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gm/ID Design Flow

Specs

Design Equations(Analytical

)

gm/Id Data Set

(Emprical)

gm/ID Design Optimization

W/L Ratios

(F. Silveira, JSSC, 1996.)

Page 31: CMOS Transistors

Intuition

gm

gds

gm/IDgm/gds

2gm

2gds

gm/IDgm/gds

2gm

2gds

gm/IDgm/gds

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gm/ID Data Set

• gm/gds

• gm/gmbs

• ID/W

• Cgd/Cgg

• Cgs/Cgg

• ….more

(F. Silveira, JSSC, 1996.)

Page 33: CMOS Transistors

Design Example

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Calculation

(gm is determined)

Initially assume that gmro is large!

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gm/gds

(50)

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Current Density

Page 37: CMOS Transistors

Biasing an MOS Transistor Using gm/ID technique

Section 7.1

J.OuSonoma State Univeristy

Page 38: CMOS Transistors

Basic Analysis

Use 1.2 V

(Modified Ex 7.1)

Page 39: CMOS Transistors

Design Equations

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Assumption: VDD=1.2 V

Transistor Information:Type: 120 nm Specify VDSNote var1_1 is ‘vsd’ if pmos is usedNote var2_1 is ‘vns’ if nmos is used.

In this example, is initially unknown, so we will assume that it is 0.0

Page 41: CMOS Transistors

Interpolation

Since the database basecan not be so large as to keep all possible values of vds/vsb, we have to interpolate based on existing values, which are availableOn 0.1 V interval.

Current release: need to enterinBias <= the minVar1 and maxVar1.

minVar=maxVar-0.1

Page 42: CMOS Transistors

Browse Database

dBrowse2D(25, 'pfet', '15.0u', 'vsd', 0.3, 0.4, 0.353, 'vns', 0.5, 0.6, 0.577, 'vth')

Variable name=dBrowse2D(gmoverid, type, length, var1, minVar1, maxVar1,inBias1,var2, minVar2, maxVar2,inBias2,‘parameter’)

Valid parameters:gmovergds, gmovergmbs, vth, ft, gmoveridft, idoverw, vod, region, fndbderivcgdovercgg,cddovercgg, cgsovercgg, csbovercgg, cdbovercgg, ron, vdsat, rseff, rdeff

type: nfet, pfetlength: {'120n' '180n' '250n' '350n' '600n' '800n' '1.0u' '2.0u' '3.0u' '4.0u' '5.0u' '6.0u' '7.0u' '8.0u' '9.0u' '10.0u' '15.0u' '20.0u'} (text string)

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Iteration• Start with

– length=‘120nm’– gmoverid=20– VDS=VDD/2, VSB=0

• Calculate– vod_1– vth_– vgs_1– vx (gate voltage)– vs (source voltage)– ID– Idoverw– W– RD– Vd– Vds=Vd-Vs

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Iteration Example

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Design Iterations

Iteration

VS IDS W RD Vds

0 0.1 V 392uA 53.06 um

1.529Kohms

0.207 V

1 0.321 322 uA 45.16 um

1.89 Kohms

0.278 V

2 0.340 340.4 uA

46.86 um

1.762 Kohms

0.259

3 0.335 335 uA 46.44 1.788 Kohms

0.265

Page 46: CMOS Transistors

Matlab & Simulation

Parameters Matlab Cadence

W 46.56 um 46 um

Vx 0.857 V 0.857 V

ids 336.8 uA 339 uA

gm 6.7 mS 6.80 mS

gm/ids 19.94 20.05

Vs 0.336 V 0.339 V

Vd 0.6 V 0.593 V

Vds 0.263 V 0.257V

Vth 0.5 V 0.497 V

Page 47: CMOS Transistors

Circuit Design Using Cadence

J.Ou

Page 48: CMOS Transistors

Start Cadence

Start Cadence

Page 49: CMOS Transistors

Create New Cellview

Page 50: CMOS Transistors

Add Instance

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Add a Resistor

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Add Ground

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Add Power

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Add Wire

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Done!

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Start ADE L

Page 57: CMOS Transistors

Start DC Analysis

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Netlist and Run

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Annotate DC Node Voltages

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Model Library Setup

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DC Voltage Annotated

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Component Display

Page 63: CMOS Transistors

Display DC Operating Point

Click on the device to displayvalues!

Page 64: CMOS Transistors

Save State


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