CMOS Technology for Computer Architects -...
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1 1 CMOS Technology for Computer Architects Lecture 1: Introduction Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTH-ICS (University of Crete) 2 CMOS Technology for Computer Architects Spring 2012 – Lecture 1 Course Contents Implementation of high-performance digital designs CMOS ASIC designs and standard-cell flow Course goals (what will you learn?) Ability to design, implement, evaluate and optimize designs with respect to different constraints: size, speed, power dissipation, and reliability Course prerequisites Fluency in digital logic design at the gate level and above Good knowledge of Computer Architecture Some knowledge of HDL will be helpful
Transcript of CMOS Technology for Computer Architects -...
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CMOS Technology
for Computer Architects
Lecture 1: Introduction
Iakovos Mavroidis
Giorgos Passas
Manolis Katevenis
FORTH-ICS (University of Crete)
2 CMOS Technology for Computer Architects
Spring 2012 – Lecture 1
Course Contents
Implementation of high-performance digital designs
CMOS ASIC designs and standard-cell flow
Course goals (what will you learn?)
Ability to design, implement, evaluate and optimize designs with respect to different constraints: size, speed, power dissipation, and reliability
Course prerequisites
Fluency in digital logic design at the gate level and above
Good knowledge of Computer Architecture
Some knowledge of HDL will be helpful
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3 CMOS Technology for Computer Architects Spring 2012 – Lecture 1
Course Administration
Instructors Iakovos Mavroidis ([email protected])
Giorgos Passas ([email protected])
Manolis Katevenis ([email protected])
Joint Graduate Course
UoC, UPC, Chalmers
Course Web Cast
Live streaming
Recorded lectures
Check: http://evo.caltech.edu/evoGate/
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Course Administration
Website
http://www.ics.forth.gr/~jacob/cmos4arch
Project Standard cell implementation and evaluation
Sources Recent publications – Roadmaps (ITRS)
Digital Integrated Circuits, 2nd Edition, Rabaey et. al.
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Detailed Topics
Lectures
Transistor Logic and CMOS inverter
Static and dynamic CMOS gates
Interconnect
Network on Chip
Standard-Cell design flow
EDA tools
Crossbar
Memories
Chip-to-chip communication
Sequential circuits
Power consumption
Clock trees
Design intensive class
65nm and 40nm
Synopsys synthesis
Cadence PnR
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Spring 2012 – Lecture 1
Today‟s Lecture - Introduction
Digital Integrated Circuit Design: The Past, The Present and The Future
Why is designing digital ICs different today than it was before?
Will it change in the future ?
Transistor
Switch model
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Digital Design Abstraction Levels
Digital ICs are ubiquitous. Why ?
focus
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Switch Model of MOS Transistor
Electronic switching device
NMOS device
Source Drain
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Semiconductor manufacturing processes
10000
3000
1500
800 600
250
130 90
65 45
32 22
16 11
8
1
10
100
1000
10000
Te
ch
no
log
y (
nm
)
Year
tri-gate
(2011)
High-k + Metal Gate
(2007)
Strained Silicon
(2002)
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Why Scaling ?
Technology shrinks by ~0.7 per generation
With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly
Cost of a function decreases by 2x
But …
How to design chips with more and more functions?
Design engineering population does not double every two years…
Hence, a need for more efficient design methods
Exploit different levels of abstraction
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Design Complexity Trends
ITRS, 2011
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Transistor Revolution
Intel, 1971 (Moore, Noyce) 2,300 transistors 740KHz operation 10μm (=10000nm) PMOS technology
Bell Labs, 1948 First Transistor
Intel Core i7, 2011 2,600,000 transistors 3.4GHz 32nm
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Moore‟s Law
In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 months (i.e., grow exponentially with time).
He made a prediction that semiconductor technology will double its effectiveness every 18 months.
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Spring 2012 – Lecture 1
Transistor Count
Pentium
Core i7
10-Core Xeon
4004
Pentium 4
Doubles
every 2 years!
AMD K8
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Transistor Count (GPUs – FPGAs)
GPU Year Manufa
cturer
Transistor
Count
NV5 1999 NVIDIA 15M
NV15 2000 NVIDIA 25M
NV40 2004 NVIDIA 222M
GT200 2008 NVIDIA 1.4B
RV870 2009 AMD 2.1B
GF100 2010 NVIDIA 3B
Tahiti 2011 AMD 4.3B
FPGA Year Manufac
turer
Transistor
Count
Virtex-E 1998 Xilinx 200M
Virtex-II 2000 Xilinx 350M
Virtex-4 2004 Xilinx 1B
Virtex-5 2006 Xilinx 1.1B
Stratix IV 2008 Altera 2.5B
Stratix V 2011 Altera 3.8B
Virtex-7 2011 Xilinx 6.8B
~2 times more
transistors than CPUs ~3 times more
transistors than CPUs
Xilinx‟s 3D (or 2.5D) packaging
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Clock Frequency
Intel Core i7 (2011) 3.4GHz
Speed/Power tradeoff: Underclocking single core by 20% saves half the
power while sacrificing13% of the performance => use more parallelism
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Power Supply
Trends of supply voltage for various versions of ITRS
H. Iwai, Micr. Eng., 2009
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Die Size
CPU Process Cores Transistor Die Size
AMD Bulldozer 8C 32nm 8 1.2B 315mm2
AMD Thuban 6C 45nm 6 904M 346mm2
AMD Deneb 4C 45nm 4 758M 258mm2
Intel Gulftown 6C 32nm 6 1.17B 240mm2
Intel SandyBridge 4C 32nm 4 995M 216mm2
Intel Lynnfield 4C 45nm 4 774M 296mm2
Intel Clarkdale 2C 32nm 2 384M 81mm2
Intel SandyBridge 2C 32nm 2 624M 149mm2
CPU Year Die Size
Pentium Pro 1995 196mm2
Pentium II 1998 113mm2
AMD T-Bird 2000 120mm2
P4 2004 145mm2
AMD K8 2005 184mm2
grows by ~14%
every 2 years
Past
Present
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Power Dissipation
PentPro
Pentium
486
386 286 8086
8085 8080
8008 4004
0.1
1
10
100
1971 1974 1978 1985 1992 2006 Year
Po
wer
(Watt
s)
1000
Pentium4
2010
Core i5
Power has to stay
~constant (~100W)
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Technology Trends – All in one
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Design Metrics
How to evaluate performance of a digital circuit (gate, block, …) ?
Cost
Reliability
Speed/Performance (delay, frequency)
Power
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Major Design Challenges
Everything Looks a Little Different
Microscopic issues
Ultra-high speeds
Interconnect
Noise, Crosstalk
Variability
Reliability
Power dissipation
Clock distribution
Macroscopic issues
Complexity
Time-to-market
Reuse and IP, portability
Systems on a chip (SoC)
High-level abstractions
Tool interoperability
Performance
Power
Time to market
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The NMOS Transistor Cross Section
L
W
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Switch Model of NMOS Transistor
Vs < VD
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Switch Model of NMOS Transistor
Strong 0 Weak 1
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Switch Model of PMOS Transistor
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Threshold Voltage Concept
Three voltage differences
VGS = VG – VS
VDS = VD – VS
VSB = VS – VB
When VS = VB = 0
VGS = VG
VDS = VD
VSB = 0
VG
VB
Vs VD
VGS < VT
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Spring 2012 – Lecture 1
Threshold Voltage Concept
Three voltage differences
VGS = VG – VS
VDS = VD – VS
VSB = VS – VB
When VS = VB = 0
VGS = VG
VDS = VD
VSB = 0
The value of VGS where strong
inversion occurs is called the
threshold voltage, VT
VG
VB
Vs VD
VGS < VT VGS > VT VG
VB
Vs VD
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Threshold Voltage – Body Effect
VT = VT0 + (|-2F + VSB| - |-2F|)
VSB is the source-bulk voltage
VT0 is the threshold voltage at VSB = 0
F ≈ -0.3V (called Fermi Potential)
γ (called body-effect coefficient) depends on the gate capacitance per unit area
= VT0 + (|-2F + VS| - |-2F|) VB= 0
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Threshold Voltage
Trends of supply voltage and threshold voltage for various versions of ITRS
H. Iwai, Micr. Eng., 2009
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Multi-gate MOSFET and FinFET
Traditional Planar
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Multi-gate MOSFET and FinFET
Traditional Planar
Gate 1
Gate 2
Source Drain
P. Mishra et. al, “Nan. Circ. Des.”, 2011
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Multi-gate MOSFET and FinFET
Traditional Planar 3D Tri-gate
third dimension!
Mark Bohr, Intel, 2011
Wfin
Hfin
LG
FinFET announced for 22nm production („11)
After 11 years R&D
low Vdd operation and chip power savings
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Multi-gate MOSFET and FinFET
Mark Bohr, Intel, 2011
Multiple fins to increase
drive strength
P. Mishra et. al, “Nan. Circ. Des.”, 2011
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22-nm Tri-Gate Circuit
