COMPUTER AIDED CMOS BASED ANALOG CIRCUIT DESIGN · iii DECLARATION I declare that the thesis...
Transcript of COMPUTER AIDED CMOS BASED ANALOG CIRCUIT DESIGN · iii DECLARATION I declare that the thesis...
COMPUTER AIDED CMOS BASED ANALOG CIRCUIT
DESIGN
A Thesis submitted to Gujarat Technological University
for the Award of
Doctor of Philosophy
in
Electronics & Communication Engineering
by
Prajapati Pankajkumar Punamchand [129990911013]
under supervision of
Dr. Mihir V. Shah
GUJARAT TECHNOLOGICAL UNIVERSITY
AHMEDABAD
[August - 2019]
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© [Prajapati Pankajkumar Punamchand]
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DECLARATION
I declare that the thesis entitled Computer Aided CMOS Based Analog Circuit Design
submitted by me for the degree of Doctor of Philosophy is the record of research work
carried out by me during the period from October 2012 to August 2019 under the
supervision of Dr. Mihir V. Shah and this has not formed the basis for the award of any
degree, diploma, associateship, fellowship, titles in this or any other University or other
institution of higher learning.
I further declare that the material obtained from other sources has been duly acknowledged
in the thesis. I shall be solely responsible for any plagiarism or other irregularities, if
noticed in the thesis.
Signature of Research Scholar: ……………………… Date: 23/08/2019
Name of Research Scholar: Prajapati Pankajkumar Punamchand
Place: Ahmedabad
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CERTIFICATE
I certify that the work incorporated in the thesis Computer Aided CMOS Based Analog
Circuit Design submitted by Mr. Prajapati Pankajkumar Punamchand was carried out
by the candidate under my supervision/guidance. To the best of my knowledge: (i) the
candidate has not submitted the same research work to any other institution for any
degree/diploma, Associateship, Fellowship or other similar titles (ii) the thesis submitted
is a record of original research work done by the Research Scholar during the period of
study under my supervision, and (iii) the thesis represents independent research work on
the part of the Research Scholar.
Signature of Supervisor: ……………………………. Date: 23/08/2019
Name of Supervisor: Dr. Mihir V. Shah
Place: Ahmedabad
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Course-work Completion Certificate
This is to certify that Mr. Prajapati Pankajkumar Punamchand enrollment no.
129990911013 is a PhD scholar enrolled for PhD program in the branch Electronics and
Communication of Gujarat Technological University, Ahmedabad.
(Please tick the relevant option(s))
He/She has been exempted from the course-work (successfully completed during
M.Phil Course)
He/She has been exempted from Research Methodology Course only (successfully
completed during M.Phil Course)
He/She has successfully completed the PhD course work for the partial
requirement for the award of PhD Degree. His/ Her performance in the course
work is as follows-
Grade Obtained in Research
Methodology
(PH001)
Grade Obtained in Self Study Course
(Core Subject)
(PH002)
BB BB
Supervisor’s Sign
(Dr. Mihir V. Shah)
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Originality Report Certificate
It is certified that PhD Thesis titled Computer Aided CMOS Based Analog Circuit
Design submitted by Mr. Prajapati Pankajkumar Punamchand has been examined by
us. We undertake the following:
a. The Thesis has significant new work/knowledge as compared to already published
or are under consideration to be published elsewhere. No sentence, equation,
diagram, table, paragraph or section has been copied verbatim from previous work
unless it is placed under quotation marks and duly referenced.
b. The work presented is original and own work of the author (i.e. there is no
plagiarism). No ideas, processes, results or words of others have been presented as
Author own work.
c. There is no fabrication of data or results which have been compiled/analyzed.
d. There is no falsification by manipulating research materials, equipment or
processes, or changing or omitting data or results such that the research is not
accurately represented in the research record.
e. The thesis has been checked using https://turnitin.com (copy of originality report
attached) and found within limits as per GTU Plagiarism Policy and instructions
issued from time to time (i.e. permitted similarity index <=25%).
Signature of Research Scholar: ……………………………. Date: 23/08/2019
Name of Research Scholar: Prajapati Pankajkumar Punamchand
Place: Ahmedabad
Signature of Supervisor: ………………………… Date: 23/08/2019
Name of Supervisor: Dr. Mihir V. Shah
Place: Ahmedabad
vii
Copy of Originality Report
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PhD THESIS Non-Exclusive License to GUJARAT
TECHNOLOGICAL UNIVERSITY
In consideration of being a PhD Research Scholar at GTU and in the interests of the
facilitation of research at GTU and elsewhere, I, Prajapati Pankajkumar Punamchand
having Enrollment No. 129990911013 hereby grant a non-exclusive, royalty free and
perpetual license to GTU on the following terms:
a) GTU is permitted to archive, reproduce and distribute my thesis, in whole or in
part, and/or my abstract, in whole or in part (referred to collectively as the “Work”)
anywhere in the world, for non-commercial purposes, in all forms of media;
b) GTU is permitted to authorize, sub-lease, sub-contract or procure any of the acts
mentioned in paragraph (a);
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under the authority of their “Thesis Non-Exclusive License”;
d) The Universal Copyright Notice (©) shall appear on all copies made under the
authority of this license;
e) I undertake to submit my thesis, through my University, to any Library and
Archives. Any abstract submitted with the thesis will be considered to form part of
the thesis.
f) I represent that my thesis is my original work, does not infringe any rights of
others, including privacy rights, and that I have the right to make the grant
conferred by this non-exclusive license.
g) If third party copyrighted material was included in my thesis for which, under the
terms of the Copyright Act, written permission from the copyright owners is
required, I have obtained such permission from the copyright owners to do the acts
mentioned in paragraph (a) above for the full term of copyright protection.
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h) I retain copyright ownership and moral rights in my thesis, and may deal with the
copyright in my thesis, in any way consistent with rights granted by me to my
University in this non-exclusive license.
i) I further promise to inform any person to whom I may hereafter assign or license
my copyright in my thesis of the rights granted by me to my University in this non-
exclusive license.
j) I am aware of and agree to accept the conditions and regulations of PhD including
all policy matters related to authorship and plagiarism.
Signature of Research Scholar: ………………………………
Name of Research Scholar: Prajapati Pankajkumar Punamchand
Date: 23/08/2019
Place: Ahmedabad
Signature of Supervisor: ……………………………...
Name of Supervisor: Dr. Mihir V. Shah
Date: 23/08/2019
Place: Ahmedabad
Seal:
x
Thesis Approval Form
The viva-voce of the PhD Thesis submitted by Mr. Prajapati Pankajkumar
Punamchand (Enrollment No. 129990911013) entitled Computer Aided CMOS Based
Analog Circuit Design was conducted on 23/08/19, Friday at Gujarat Technological
University.
(Please tick any one of the following option)
The performance of the candidate was satisfactory. We recommend that he be
awarded the PhD degree.
Any further modifications in research work recommended by the panel after 3
months from the date of first viva-voce upon request of the Supervisor or request
of Independent Research Scholar after which viva-voce can be re-conducted by
the same panel again.
The performance of the candidate was unsatisfactory. We recommend that he
should not be awarded the PhD degree.
-------------------------------------------------- ------------------------------------------------
Name and Signature of Supervisor with Seal External Examiner -1 Name and Signature
-------------------------------------------------- ------------------------------------------------
External Examiner -2 Name and Signature External Examiner -3 Name and Signature
(Briefly specify the modifications suggested by the panel)
(The panel must give justifications for rejecting the research work)
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Abstract
The functionality of electronic gadgets and equipment has achieved remarkable growth
over the last two decades. So, the demand for high-speed and complex mixed-signal
System-on-Chip (SoC) is increasing continuously. The SoC integrates digital circuits and
analog circuits on the same chip. The mature Computer-Aided Design (CAD) tools have
been already established for digital circuits to improve the yield. The manual design of a
Complementary Metal Oxide Semiconductor (CMOS) based analog circuit is challenging
and time-consuming due to the increased complexity of physical models and process
variations with downscaling of CMOS technology. The design process is also tricky due to
the complex relationships between the design goals and the multiple design parameters.
On the contrary, the research efforts in the field of the analog circuit design are limited
compared to the digital circuit design. This leaves ample scope of improvement in the
techniques of analog circuit design. Automation for the analog circuit design process is
one of the best remedies to cope with this problem, especially keeping the time-to-market
considerations. This motivates circuit designers to explore more CAD tools for analog
circuits in current years. Hence, the area of computer-aided analog circuit design has
emerged the subject of dynamic research.
In this work, application and performance evaluation of the Cuckoo Search (CS) algorithm
for the automated design of the CMOS based analog circuits are proposed. It is explored
for sizing of commonly used CMOS based analog circuits like triple cascode current
mirror, voltage divider, common-source amplifier, cascode amplifier, three-stage current
starved Voltage Controlled Oscillator (VCO), Differential Amplifier (DA) using a current
mirror as load, two-stage op-amp, Miller Operational Transconductance Amplifier (OTA),
and Folded Cascode OTA (FOTA) in 0.18 µm and/or 0.35 µm CMOS process
technologies. These circuits are also designed by using the most commonly used
Differential Evolution (DE) and Particle Swarm Optimization (PSO) algorithms to
compare the performance of the CS algorithm with these Evolutionary Algorithms (EAs).
To exploit the benefits of the CS and PSO algorithms, a hybrid CSPSO algorithm is also
implemented by collaborating both algorithms and explored for the optimization of CMOS
based analog circuits. Further, to test the robustness of the optimizer, the effects of Process
(𝑃) , Voltage (𝑉) , and Temperature (𝑇) variations on circuit performance are also
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analysed for DA with a current mirror load and two-stage op-amp circuits. Each algorithm
is implemented using the C programming language, interfaced with Ngspice circuit
simulator, and tested on the Intel® core™ i5, 2.40 GHz processor with 8 GB internal
RAM using the Ubuntu Operating System (OS).
The CS and hybrid CSPSO algorithms succeeded for the optimization of the DA with a
current mirror load circuit for all 10 runs of experiments, whereas the PSO and DE
algorithms could not achieve success for the fulfilment of all the targeted specifications.
For the optimization of the two-stage op-amp, the CS and hybrid CSPSO algorithms
obtained 100 % success with 0.35 µm CMOS technology for all 10 runs, whereas the DE
and PSO algorithms failed to attain all the desired specifications. The CS and hybrid
CSPSO algorithms also obtained a higher success rate compared to the DE and PSO
algorithms for the current mirror, VCO, FOTA, Miler OTA, and PVT-aware optimization
of DA and two-stage op-amp circuits. In terms of the final solution and convergence speed,
the CS and CSPSO algorithms perform better than the PSO and DE algorithms for most of
the optimized circuits in this work.
Keywords: Automation of analog circuit design, EA, CS algorithm, PSO algorithm,
Hybrid CSPSO algorithm, DE algorithm, Optimization, Convergence.
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Acknowledgement
This thesis would have been impossible without the support of many people. I would
express my sincere gratitude to all of them for their invaluable support. I would like to
thank, the almighty God for giving me strength and passion for doing research.
First of all, I would like to take this opportunity to express my deepest gratitude to my
supervisor Dr. Mihir V. Shah for his valuable & enthusiastic guidance and
encouragement at every step of my research. Due to his invaluable suggestions and
extensive technical support from time to time enabled me to complete my research
successfully.
Also, I would like to express my gratitude to Dr. R. A. Thakkar and Dr. D. J. Shah. It
was a great honor to have them as my thesis Doctoral Progress Committee Members. The
completion of this work would not have been possible without their valuable suggestions.
Their rigorous examination and constructive suggestions made the thesis sound in many
aspects.
I acknowledge Honourable Vice-Chancellor, Registrar, Controller of Examination, Dean
Ph.D. section, and all staff members of the Ph.D. section of Gujarat Technological
University (GTU) for their assistance and support. I also acknowledge Principal, Head of
Department, and all staff members as well as students of EC department of L. D. College
of Engineering for their assistance and support.
I would like to express my earnest thanks to the reviewers of my thesis, for accepting to
read and review this thesis and giving approval of it. I would like to appreciate all the
researchers whose work I have used (initially in understanding my field of research and
later for updates). I would like to thank all the people who have taught me, starting with
my school teachers, my undergraduate teachers, and my post-graduate teachers. I want to
extend my special thanks to Dr. Anil Kshatriya (Asst. Prof. EC, LDCE), Mr. Krunal
Acharya (Asst. Prof. EC, VGEC), Dr. Subhash Patel (Engineer, Volansys
Technologies), and Mr. Rahul Thakur (Technical Leader, STMicroelectronics) for their
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help and support. I also want to thank my friends who helped me directly or indirectly
with their moral support and understanding during all these years.
Finally, I give the greatest respect and love to my parents, brothers, my wife, my son
Harshal, and daughter Roshani. I want to express my highest appreciation for their
support and cooperation. I would like to say thanks to my wife Mrs. Kailash for
encouraging me to do research and for her moral support. I would like to express my deep
thanks and gratitude to (late) grandparents who have been showering their blessing on me
from heaven and have always encouraged me since my early years of education. Without
their love and faith, I would not have been where I am today. For this reason, this thesis is
dedicated to them. Thanks to the Almighty God for giving me the patience to complete
research.
This thesis is dedicated with love to all of my well-wishers for assisting me to achieve the
most important stage in my life. I will never let them down and wish them all the success
in the future.
As it is a prolonged journey, maybe I have forgotten to mention few names, nonetheless,
they remain a core part of this mammoth task, and I seek forgiveness for the same and
offer my kind respect to every one of them.
Thank you,
Prajapati Pankajkumar P.
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Table of Contents
Abstract .............................................................................................................................. xi
List of Abbreviations ...................................................................................................... xvii
List of Symbols ................................................................................................................ xix
List of Figures .................................................................................................................... xx
List of Tables ................................................................................................................... xxii
1 Introduction .................................................................................................................... 1
1.1 Analog Circuit Design .......................................................................................................... 1
1.2 Motivation ............................................................................................................................ 2
1.3 Definition of the Problem ..................................................................................................... 4
1.4 Objective and Scope of Work ............................................................................................... 5
1.5 Original Contribution of the Thesis ...................................................................................... 5
1.6 Thesis Organization .............................................................................................................. 6
2 Literature Review ........................................................................................................... 8
2.1 Introduction .......................................................................................................................... 8
2.2 State-of-the-Art of Automatic Analog Circuit Design ......................................................... 9
2.3 Evolutionary Algorithms .................................................................................................... 13
2.3.1 DE Algorithm ........................................................................................................... 13
2.3.2 PSO Algorithm ......................................................................................................... 15
2.3.3 CS Algorithm ........................................................................................................... 17
2.4 Summary ............................................................................................................................. 21
3 Performance Estimation of Evolutionary Algorithms .............................................. 22
3.1 Introduction ........................................................................................................................ 22
3.2 Hybrid CSPSO Algorithm .................................................................................................. 22
3.3 Benchmark Function ........................................................................................................... 25
3.4 Experimental Settings and Results ..................................................................................... 26
3.5 Summary ............................................................................................................................. 37
4 Analog Circuit Optimization ....................................................................................... 39
4.1 Introduction ........................................................................................................................ 39
4.2 Automated Circuit Design Methodology ............................................................................ 40
4.3 Simple CMOS based Analog Circuit Optimization ............................................................ 43
4.3.1 Triple Cascode Current Mirror ................................................................................. 43
4.3.2 Common-Source Amplifier ...................................................................................... 46
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4.3.3 Voltage Divider ........................................................................................................ 47
4.3.4 Current-Starved VCO ............................................................................................... 50
4.3.5 Cascode Amplifier .................................................................................................... 52
4.4 Moderately Complex CMOS based Analog Circuit Optimization ..................................... 55
4.4.1 Differential Amplifier using a Current Mirror Load ................................................ 55
4.4.2 Two-Stage Operational Amplifier ............................................................................ 61
4.4.3 Folded Cascode OTA ............................................................................................... 68
4.4.4 Miller OTA ............................................................................................................... 73
4.5 Summary ............................................................................................................................. 80
5 PVT-aware Circuit Optimization................................................................................ 81
5.1 Introduction ........................................................................................................................ 81
5.2 PVT Variation ..................................................................................................................... 81
5.3 Circuit Optimization with PVT Corners ............................................................................. 82
5.3.1 Optimization of DA with PVT Corners .................................................................... 83
5.3.2 Optimization of Two-Stage Op-amp with PVT Corners .......................................... 86
5.4 Summary ............................................................................................................................. 88
6 Conclusions and Scope of Future Work ..................................................................... 89
6.1 Conclusions ........................................................................................................................ 89
6.2 Scope of Future Work ......................................................................................................... 90
References .......................................................................................................................... 92
List of Publications ............................................................................................................ 99
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List of Abbreviations
ABC Artificial Bee Colony
ACO Ant Colony Optimization
ADC Analog to Digital Converter
ALCPSO Particle Swarm Optimization with an Aging Leader and Challenger
BSIM Berkeley Short-channel IGFET Model
CAD Computer-Aided Design
CMOS Complementary Metal Oxide Semiconductor
CMRR Common Mode Rejection Ratio
CR Crossover Rate
CRPSO Craziness-based Particle Swarm Optimization
CS Cuckoo Search
DA Differential Amplifier
DAC Digital to Analog Converter
DPLL Digital Phase Locked Loop
dB Decibel
DE Differential Evolution
FF Fast-Fast
FOTA Folded Cascode Operational Transconductance Amplifier
FS Fast-Slow
FSR Falling Slew Rate
GA Genetic Algorithm
GB Gigabyte
GCC GNU Compiler Collection
GUI Graphical User Interface
HS Harmony Search
IC Integrated Circuit
IEEE Institute of Electrical and Electronics Engineers
MPSO Modified Particle Swarm Optimization
NFL No Free Lunch
MHz Megahertz
MOS Metal Oxide Semiconductor
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MGWO Modified Gray Wolf Optimization
NMOS N-Channel Metal Oxide Semiconductor
NP Non-deterministic Polynomial-time
Op-amp Operational amplifier
OTA Operational Transconductance Amplifier
PDF Probability Density Function
PM Phase Margin
PMOS P-Channel Metal Oxide Semiconductor
PSO Particle Swarm Optimization
PSSR Power Supply Rejection Ratio
PVT Process, Voltage, and Temperature
RMS Root Mean Square
RSR Rising Slew Rate
SA Simulated Annealing
SF Slow-Fast
SoC System-on-Chip
SPICE Simulation Program with Integrated Circuit Emphasis
SR Slew Rate
SS Slow-Slow
TS Tabu Search
TT Typical- Typical
TTA Total MOS Transistor Area
UGB Unity Gain Bandwidth
VCO Voltage Controlled Oscillator
VLSI Very Large Scale Integration
WLA Whale Optimization Algorithm
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List of Symbols
𝐷 Problem dimension
𝐹 Weighting factor
𝑁 Number of particles/nests or Size of population
𝑊 Width of transistor
𝛼 Scaling factor of the step size
𝛽 Variable which controls the distribution
𝜔 Linear time-varying inertia weight
∈ Belongs to
⊗ Entry-wise multiplication
𝛤 Gamma function
~ Random numbers drawn from a distribution
𝜆 Power coefficient
𝜎2 Variance
𝐻(𝑢) Heaviside function
𝑝𝑎 Discovery probability of a cuckoo egg by a host bird
𝒙∗ Global optimum solution of a function
𝑓(𝒙∗) Global minimum value of a function
𝑟/𝑟𝑎𝑛𝑑1/𝑟𝑎𝑛𝑑2 Random number generated from a uniform distribution
𝐶1 /𝐶2 Acceleration coefficient
𝐴𝑣 Open-loop DC gain
𝐹𝐸𝑎𝑣𝑔 Average number of function evaluations
𝐼𝑡𝑒𝑟𝑎𝑣𝑔 Average number of iterations
𝐼𝑏𝑖𝑎𝑠 Bias current
𝑁𝑖𝑛 Input-referred noise spectral density
𝑁𝑖𝑛𝑡 Total integrated input-referred noise over the specified frequency range
𝑃𝑑𝑖𝑠𝑠 DC power dissipation
𝑆𝐷𝑓 Standard deviation of a function value
𝑆𝑟𝑎𝑡𝑒 Success rate
𝑇𝑠𝑖𝑚 Total simulation time
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List of Figures
FIGURE 1.1: Analog circuit design octagon ....................................................................... 2
FIGURE 2.1: Flowchart of the DE algorithm .................................................................... 14
FIGURE 2.2: Flowchart of the PSO algorithm .................................................................. 16
FIGURE 2.3: Flowchart of the CS algorithm .................................................................... 17
FIGURE 2.4: Lévy distribution .......................................................................................... 19
FIGURE 2.5: Pseudocode of the CS algorithm .................................................................. 21
FIGURE 3.1: Trade-off between accuracy and convergence ............................................ 23
FIGURE 3.2: Pseudocode of the hybrid CSPSO algorithm ................................................ 23
FIGURE 3.3: Flowchart of the hybrid CSPSO algorithm ................................................... 24
FIGURE 3.4: Convergence graph of 30-D Ackley function for the CS, PSO, CSPSO,
and DE algorithms ........................................................................................ 32
FIGURE 3.5: Convergence graph of 2-D Beale function for the CS, PSO, CSPSO, and
DE algorithms .............................................................................................. 33
FIGURE 3.6: Convergence graph of 2-D Drop-Wave function for the CS, PSO, CSPSO,
and DE algorithms ........................................................................................ 33
FIGURE 3.7: Convergence graph of 2-D Easom function for the CS, PSO, CSPSO, and
DE algorithms .............................................................................................. 34
FIGURE 3.8: Convergence graph of 30-D Griewank function for the CS, PSO, CSPSO,
and DE algorithms ........................................................................................ 34
FIGURE 3.9: Convergence graph of 30-D Lévy function for the CS, PSO, CSPSO, and
DE algorithms .............................................................................................. 35
FIGURE 3.10: Convergence graph of 30-D Rastrigin function for the CS, PSO, CSPSO,
and DE algorithms ...................................................................................... 35
FIGURE 3.11: Convergence graph of 30-D Rosenbrock function for the CS, PSO,
CSPSO, and DE algorithms ....................................................................... 36
FIGURE 3.12: Convergence graph of 2-D Schaffer function for the CS, PSO, CSPSO,
and DE algorithms ...................................................................................... 36
FIGURE 3.13: Convergence graph of 30-D Sphere function for the CS, PSO, CSPSO,
and DE algorithms ...................................................................................... 37
FIGURE 4.1: Automated circuit design methodology framework ..................................... 41
FIGURE 4.2: Triple cascode current mirror ...................................................................... 43
FIGURE 4.3: Convergence graph of different EAs for triple cascode current mirror ........ 45
FIGURE 4.4: Common-source amplifier ........................................................................... 46
FIGURE 4.5: Voltage divider ............................................................................................. 48
FIGURE 4.6: Convergence graph of different EAs for voltage divider ............................. 49
FIGURE 4.7: Three-stage current-starved VCO ................................................................ 50
FIGURE 4.8: Convergence graph of different EAs for VCO ............................................. 52
FIGURE 4.9: Cascode amplifier ........................................................................................ 52
FIGURE 4.10: Convergence graph of different EAs for cascode amplifier ....................... 54
FIGURE 4.11: DA using a current mirror load .................................................................. 56
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FIGURE 4.12: Convergence graph of different EAs for DA optimization in 0.35 µm
CMOS technology ...................................................................................... 58
FIGURE 4.13: Convergence graph of different EAs for DA optimization in 0.18 µm
CMOS technology ...................................................................................... 61
FIGURE 4.14: Two-stage op-amp ..................................................................................... 62
FIGURE 4.15: Convergence graph of different EAs for two-stage op-amp optimization
in 0.35 µm CMOS technology ................................................................... 65
FIGURE 4.16: Convergence graph of different EAs for two-stage op-amp optimization
in 0.18 µm CMOS technology ................................................................... 67
FIGURE 4.17: Folded cascode OTA ................................................................................. 68
FIGURE 4.18: Convergence graph of different EAs for FOTA optimization in 0.35 µm
CMOS technology ...................................................................................... 71
FIGURE 4.19: Convergence graph of different EAs for FOTA optimization in 0.18 µm
CMOS technology ...................................................................................... 73
FIGURE 4.20: Miller OTA ................................................................................................ 74
FIGURE 4.21: Convergence graph of different EAs for Miller OTA optimization in
0.35 µm CMOS technology ....................................................................... 77
FIGURE 4.22: Convergence graph of different EAs for Miller OTA optimization in
0.18 µm CMOS technology ....................................................................... 79
FIGURE 5.1: Two-step approach for circuit design with PVT variations .......................... 83
FIGURE 5.2: Convergence graph of different EAs for DA optimization in 0.18 µm
CMOS technology with PVT variations ...................................................... 85
FIGURE 5.3: Convergence graph of different EAs for two-stage op-amp optimization
in 0.18 µm CMOS technology with PVT variations .................................... 88
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List of Tables
TABLE 2.1: Different phases of literature review ................................................................ 8
TABLE 3.1: Standard benchmark functions ....................................................................... 25
TABLE 3.2: Performance evaluation of different EAs with different benchmark
functions ........................................................................................................ 29
TABLE 3.3: Performance evaluation of different EAs with 20-D benchmark functions ... 30
TABLE 3.4: Performance evaluation of different EAs with 30-D benchmark functions ... 31
TABLE 4.1: List of optimized CMOS based analog circuits ............................................. 40
TABLE 4.2: Parameter settings of the DE, PSO, CS, and CSPSO algorithms ................... 42
TABLE 4.3: Search space and optimized parameters by different EAs for triple cascode
current mirror ................................................................................................. 44
TABLE 4.4: Desired specifications and simulation results by different EAs for triple
cascode current mirror .................................................................................... 44
TABLE 4.5: Performance of different EAs for optimization of triple cascode current
mirror .............................................................................................................. 45
TABLE 4.6: Search space and optimized parameters by different EAs for common-
source amplifier .............................................................................................. 46
TABLE 4.7: Desired specifications and simulation results by different EAs for
common-source amplifier .............................................................................. 47
TABLE 4.8: Performance of different EAs for the optimization of common-source
amplifier ......................................................................................................... 47
TABLE 4.9: Search space and optimized parameters by different EAs for voltage
divider ........................................................................................................... 48
TABLE 4.10: Desired specifications and simulation results by different EAs for voltage
divider ........................................................................................................... 48
TABLE 4.11: Performance of different EAs for the optimization of voltage divider ........ 49
TABLE 4.12: Search space and optimized parameters by different EAs for VCO ............ 51
TABLE 4.13: Desired specifications and simulation results by different EAs for VCO .... 51
TABLE 4.14: Performance of different EAs for the optimization of VCO ........................ 51
TABLE 4.15: Search space and optimized parameters by different EAs for cascode
amplifier ....................................................................................................... 53
TABLE 4.16: Desired specifications and simulation results by different EAs for cascode
amplifier ....................................................................................................... 53
TABLE 4.17: Performance of different EAs for the optimization of cascode amplifier .... 54
TABLE 4.18: Search space and optimized parameters by different EAs for DA in
0.35 µm CMOS technology ......................................................................... 56
TABLE 4.19: Desired specifications and simulation results by different EAs for DA in
0.35 µm CMOS technology ......................................................................... 57
TABLE 4.20: Performance of different EAs for the optimization of DA in 0.35 µm
CMOS technology ........................................................................................ 57
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TABLE 4.21: Search space and optimized parameters by different EAs for DA in
0.18 µm CMOS technology ......................................................................... 59
TABLE 4.22: Desired specifications and simulation results by different EAs for DA in
0.18 µm CMOS technology ......................................................................... 59
TABLE 4.23: Performance of different EAs for the optimization of DA using 0.18 µm
CMOS technology ........................................................................................ 60
TABLE 4.24: Search space and optimized parameters by different EAs for two-stage
op-amp in 0.35 µm CMOS technology ........................................................ 63
TABLE 4.25: Desired specifications and simulation results by different EAs for
two-stage op-amp in 0.35 µm CMOS technology........................................ 63
TABLE 4.26: Performance of different EAs for the optimization of two-stage op-amp in
0.35 µm CMOS technology ......................................................................... 64
TABLE 4.27: Search space and optimized parameters by different EAs for two-stage
op-amp in 0.18 µm CMOS technology ........................................................ 65
TABLE 4.28: Desired specifications and simulation results by different EAs for
two-stage op-amp in 0.18 µm CMOS technology........................................ 66
TABLE 4.29: Performance of different EAs for the optimization of two-stage op-amp
using 0.18 µm CMOS technology ................................................................ 67
TABLE 4.30: Search space and optimized parameters by different EAs for FOTA in
0.35 µm CMOS technology ......................................................................... 69
TABLE 4.31: Desired specifications and simulation results by different EAs for FOTA
in 0.35 µm CMOS technology ..................................................................... 69
TABLE 4.32: Performance of different EAs for optimization of FOTA in 0.35 µm
CMOS technology ........................................................................................ 70
TABLE 4.33: Search space and optimized parameters by different EAs for FOTA in
0.18 µm CMOS technology ......................................................................... 71
TABLE 4.34: Desired specifications and simulation results by different EAs for FOTA
in 0.18 µm CMOS technology ..................................................................... 72
TABLE 4.35: Performance of different EAs for the optimization of FOTA in 0.18 µm
CMOS technology ........................................................................................ 73
TABLE 4.36: Search space and optimized parameters by different EAs for Miller OTA
in 0.35 µm CMOS technology ..................................................................... 75
TABLE 4.37: Desired specifications and simulation results by different EAs for Miller
OTA in 0.35 µm CMOS technology ............................................................ 75
TABLE 4.38: Performance of different EAs for optimization of Miller OTA in 0.35 µm
CMOS technology ........................................................................................ 76
TABLE 4.39: Search space and optimized parameters by different EAs for Miller OTA
in 0.18 µm CMOS technology ..................................................................... 77
TABLE 4.40: Desired specifications and simulation results by different EAs for Miller
OTA in 0.18 µm CMOS technology ............................................................ 78
TABLE 4.41: Performance of different EAs for optimization of Miller OTA in 0.18 µm
CMOS technology ........................................................................................ 79
TABLE 5.1: Search space and optimized parameters by different EAs for DA in
0.18 µm CMOS technology with PVT variations .......................................... 84
xxiv
TABLE 5.2: Desired specifications and simulation results by different EAs for DA
in 0.18 µm CMOS technology with PVT variations ...................................... 84
TABLE 5.3: Performance of different EAs for optimization of DA in 0.18 µm CMOS
technology with PVT variations ..................................................................... 85
TABLE 5.4: Search space and optimized parameters by different EAs for op-amp in
0.18 µm CMOS technology with PVT variations .......................................... 86
TABLE 5.5: Desired specifications and simulation results by different EAs for op-amp
in 0.18 µm CMOS technology with PVT variations ...................................... 87
TABLE 5.6: Performance of different EAs for optimization of op-amp in 0.18 µm
CMOS technology with PVT variations ........................................................ 87
Analog Circuit Design
1
CHAPTER-1
1 Introduction
1.1 Analog Circuit Design
In the field of Very Large Scale Integration (VLSI), designing of Metal Oxide
Semiconductor (MOS) based analog circuit can be considered as an art. Analog
Complementary Metal Oxide Semiconductor (CMOS) circuit design process has three
stages; to select the topology of the circuit, to determine the values of design parameters of
the circuit for a given specification, and to prepare the physical layout for the schematic-
level design of the circuit [1]. Determination of the values of the design parameters of a
particular circuit is known as circuit sizing (schematic-level design). During the
schematic-level design, there are a number of design parameters which can be adjusted by
a circuit designer to obtain the desired specifications for a circuit. The design parameters
have direct control over the performance of the circuit. For a particular circuit, the
optimum selection of the design parameters yields an optimum solution. Usually, the
analog circuit is designed by hand calculations using very general analytic equations
which roughly describe the behaviour of the circuit. After that, many simulations need to
be executed to validate that the circuit works as per estimation or not. This is an iterative,
tedious, and time-consuming job. Moreover, there is no assurance about optimum circuit
design in terms of silicon area, gain, slew rate, bandwidth, power consumption, etc. One
more aspect that also needs to be considered is, the analog circuit generally requires to
meet more than one design metric. Furthermore, most of the design metrics of an analog
circuit trade-off with each other. This turns the task of exploring a given circuit's design
Introduction
2
space into a multi-objective optimization problem. Fig. 1.1 shows an analog design
octagon which illustrates this trade-off with typical design metrics.
Noise Linearity
GainPower Dissipation
Input/output
ImpedanceSupply Voltage
SpeedVoltage
Swings
FIGURE 1.1: Analog circuit design octagon [2]
1.2 Motivation
The design of analog circuits is more important in the electronic system because the world
itself is analog. Moreover, new products depend on analog circuitry to improve speed and
reduce power dissipation. The digital systems need analog components for interfacing
with the outside world and nearly 75 % of System-on-Chips (SoCs) contain an analog
circuit [3]. Analog circuit of the SoC covers just roughly 10 % of the chip area. Though
the analog circuit area is a small portion of SoC, it is much more difficult to design it
because of the complex and knowledge-intensive nature of the analog circuits. The design
and validation of this portion take about 90% of the total amount of time needed to design
the whole chip due to the advancement in Integrated Circuit (IC) technology [4]. The
downscaling of CMOS technology and increasing needs for the VLSI system to
implement mixed analog-digital systems on the same chip make the analog circuit design
more complex and challenging. Further, the analog circuit designing problem normally
has many satisfactory solutions. However, within the very broad design space, one
optimum design commonly exists that minimizes (or maximizes) one of the objectives
with given a constraint on the other metrics. So, one can’t be sure about the optimized
parameters once the circuit is designed. Without an automated circuit sizing methodology,
Motivation
3
analog circuit design suffers from long design time, high design complexity, high cost, and
requirement of highly skilled designers. The above-mentioned motives lead to the
development of a novel methodology that would automate certain portions of the analog
circuit design flow. Automated design of the analog circuits can save a vast portion of the
overall design cycle time and also reduces the cost required to design IC. Nowadays, much
research is being undertaken to develop an analog synthesis tool that would shorten the
design time of the analog circuits. Many research institutions and researchers all around
the world have been trying to develop and improve such type of Computer-Aided Design
(CAD) tool [5]–[9]. Furthermore, such a tool should be able to handle a broad range of
analog circuit design problems and synthesize variation-tolerant high-performance
circuits.
Many techniques for automatic analog circuit design at the schematic-level are presented
in the literature. These techniques can be classified into two main categories: (1)
Knowledge-based and (2) Optimization-based. In the knowledge-based technique, the
analog circuit designer generates synthesis rules based on his experience and expertise in
the field of analog design. Further, these rules are incorporated into an algorithm that leads
to a design solution [10]–[14]. This method is time-consuming, tedious, and only suitable
to a few circuit topologies. The optimization-based approach uses a search algorithm that
forces the design towards a solution specified by the user [15]–[19]. This approach is
highly reliable and gives accurate results. Many optimization methods are developed since
the last few decades and presented for analog circuit design automation. In recent years,
research efforts, motivated by metaheuristic algorithms, have initiated to appear for the
analog circuit design automation.
Heuristic means to find a solution to an optimization problem by trial and error process.
Further development over the heuristic algorithms is known as metaheuristic algorithms.
Meta means ‘beyond’ or ‘higher level’, and they generally perform better than the simple
heuristics [20]. Metaheuristic algorithms are problem independent algorithms that can be
applied to a wide range of optimization problems. There are many metaheuristic
algorithms such as Simulated Annealing (SA) [21][22], Tabu Search (TS) [23][24],
Genetic Algorithm (GA) [25], Differential Evolution (DE) [26], Particle Swarm
Optimization (PSO) [27][28], Harmony Search (HS) [29], Ant Colony Optimization (ACO)
[30], Artificial Bee Colony (ABC) [31][32] algorithms, etc., presented in the literature to
Introduction
4
optimize the design parameters of commonly used CMOS based analog circuits for the
targeted specifications.
1.3 Definition of the Problem
This research aims to develop an efficient framework for the automated optimal sizing of a
CMOS based analog circuit to meet the desired specifications. For an analog CMOS
circuit, the optimum selection of the design parameters can be modelled as an optimization
problem that minimizes the objective function based on the design parameters, while
satisfying a set of the design specifications. Most of the circuit optimization problems
concurrently need different types of variables, objectives, and constraint functions in their
formulations. To guarantee this, the search space of the design parameters should be
smooth and the optimization process should be consistent. As the algorithm related
parameters affect the performance of an analog circuit, proper selection of these
parameters is a very crucial problem for the analog circuit design automation. The
performance of an optimization algorithm varies with an optimization problem. The
problem of an analog CMOS circuit design can be considered as a multimodal, multi-
objective, and multi-constrained optimization problem. It demands an efficient
optimization technique for optimum sizing of the design parameters for the CMOS based
analog circuits.
The Cuckoo Search (CS) algorithm is a recently developed Evolutionary Algorithm (EA)
wherein a very few parameters need to be set and it has very good ability to find the global
optimum solution compared to other popular EAs. As per the reported literature, the CS
algorithm has been used many times for highly non-linear optimization problems with
real-world engineering applications, however, it has not been tested to optimize a CMOS
based analog circuit. The intention of this research is to explore the CS algorithm for the
optimization of different CMOS based analog circuit building blocks and evaluate the
performance of the CS algorithm for this application. Also, to compare the performance of
the CS algorithm with respect to other commonly used EAs for validation. Further, to find
the worst-case performance values for few circuits, the important factors for performance
variations of an analog CMOS circuit are considered.
Objective and Scope of Work
5
1.4 Objective and Scope of Work
The purpose of this work is to investigate the potential role of the optimization algorithms
for the design of CMOS based analog circuits. The main objectives of this work are listed
below:
To examine state-of-the-art and innovative multi-objective optimization methods.
To implement a few most popular optimization methods, evaluate their
performance using the standard benchmark functions, and compare their
performance.
To develop an optimizer whose objective is sizing of the devices of analog circuits
according to user required specifications using the optimization methods.
To interface developed optimizer with a Simulation Program with Integrated
Circuit Emphasis (SPICE) model of the circuit design problem and cultivate
multi-objective and multi-constrained optimization methodology for the
automation of analog circuit design.
To test the optimization system on several independent CMOS based analog
circuit examples and evaluate the performance of each optimization method.
To implement a hybrid algorithm by collaborating two algorithms to exploit the
benefits of more than one algorithms. Also to explore the hybrid algorithm for the
optimization of CMOS based analog circuits.
To develop a robust optimizer in order to guarantee a high yield design.
1.5 Original Contribution of the Thesis
In this work, an application of the EA for the CMOS based analog circuit design problem
has been demonstrated. The application of the CS algorithm is proposed for the automatic
sizing of a CMOS based analog circuit. The original contributions of this research work
can be summarized as:
The CS algorithm is implemented using the C programming language and its
performance is evaluated using typical unimodal and multimodal benchmark
functions. The performance of the CS algorithm is also compared with the PSO
and DE algorithms.
Introduction
6
By collaborating the CS algorithm with the PSO algorithm, the hybrid CSPSO
algorithm is implemented, its performance is evaluated for the same benchmark
functions, and its performance is compared with the PSO and DE algorithms.
An efficient approach for automatic sizing of a CMOS based analog circuit is
developed using different EAs such as the CS, hybrid CSPSO, PSO, and DE
algorithms. This framework is tested for the optimization of different commonly
used CMOS based analog circuits like a voltage divider, current mirror, Voltage
Controlled Oscillator (VCO), common-source amplifier, cascode amplifier,
Differential Amplifier (DA) with current mirror load, two-stage Operational
amplifier (op-amp), Miller Operational Transconductance Amplifier (OTA), and
Folded cascode OTA (FOTA) for different specifications with 0.18 µm and/or
0.35 µm CMOS process technologies. The solutions obtained by each EA are
validated through simulating designed circuits functionally using Ng-spice circuit
simulator.
The performance of the CS and CSPSO algorithms for automatic CMOS based
analog circuit design is evaluated and compared with the performance of the most
commonly used DE and PSO algorithms. Robustness of the CS and CSPSO
algorithms is also tested.
As the Process (𝑃), Supply Voltage (𝑉), and Temperature (𝑇) are three important
factors for the performance variations of an analog circuit, PVT analysis is carried
out for the DA with a current mirror load circuit and two-stage op-amp circuit
during the optimization process to find the worst-case performance values across
user-defined PVT corners.
1.6 Thesis Organization
The rest of the thesis is organized as:
The second chapter is devoted to the state-of-the-art automatic analog circuit design using
EAs. The basic concepts about three EAs such as the DE, PSO, and CS algorithms are also
described in it.
Thesis Organization
7
The third chapter includes the performance comparison of the DE, PSO, CS, and CSPSO
algorithms by solving different benchmark functions. The concept of a hybrid algorithm
by collaborating more than one algorithm is also introduced.
The fourth chapter explores the optimization methodology of a CMOS based analog
circuit at schematic-level design. In this chapter, the optimization of various commonly
used simple as well as moderately complex CMOS based analog circuits is presented. It
also demonstrates the capabilities of the system and provides some insight into factors that
affects the sizing process. The performance comparison of different EAs for automatic
sizing of different CMOS based analog circuits are also discussed.
In the fifth chapter, the optimization of DA using a current mirror load and two-stage op-
amp circuits with PVT variations using different EAs is covered to test the robustness of
the optimizer.
Finally, the sixth chapter summarizes this work and concludes. It also provides a possible
future scope to extend this work.
Literature Review
8
CHAPTER-2
2 Literature Review
2.1 Introduction
A literature review is a continuous process which has been carried out throughout the
course of research. The main objective of this section is to offer enough background
information on the automated design of analog circuits. The literature review of this
research work is divided into five different phases. Table 2.1 shows section-wise details
about these phases with their objectives and outcomes.
TABLE 2.1: Different phases of literature review
Phase Area of
Literature Review Objective Outcomes
1 Automated design
of analog circuits
To understand the concept of automated
design of analog circuits.
Design cycle time is reduced
due to the automated design
of analog circuits.
2 Optimization
Algorithms
To find capable and stable optimization
algorithms for the automated design of
analog circuits.
Different optimization
algorithms and their
limitations are studied.
3 Benchmark
Functions
To find commonly used functions to test
the performance of an optimization
algorithm.
Brief awareness of different
types of benchmark
functions is gained.
4 Analog circuits
To find out the most versatile CMOS
based analog circuits considered in the
literature for automatic sizing
procedure.
Different circuits and their
performance parameters are
studied.
5 PVT variations To understand the effect of variations of
PVT on the analog circuit performance.
PVT analysis is important to
develop a robust optimizer.
State-of-the-Art of Automatic Analog Circuit Design
9
Systematic literature survey throughout research work is useful to find the following
information:
The concept of automatic CMOS based analog circuit design.
Different types of optimization algorithms, their merits, and demerits.
Testing of the optimization algorithms with the help of benchmark functions.
Best optimization algorithm to find an optimal solution for an optimization
problem.
Different factors affecting the performance of a CMOS based analog circuit.
Validate the result through simulation.
In the last three decades, analog circuit design engineers explored many techniques for the
automation of the analog circuit sizing. In this chapter, these approaches are concisely
covered focusing on the optimization methods which are used. Different EAs such as the
DE, PSO, and CS algorithms are also described briefly.
2.2 State-of-the-Art of Automatic Analog Circuit Design
Optimization is a process of finding the best solution for a given problem based on the
available parameters of the design [33]. During the optimization of an analog circuit, the
design parameters values are selected in such a way that the actual circuit performance
meets the design specifications. The main design parameters of a CMOS based analog
circuit may be the width (𝑊) and length (𝐿) of different NMOS and PMOS transistors,
bias current (𝐼𝑏𝑖𝑎𝑠) , resistor (𝑅) , and capacitor (𝐶) . The optimization is an iterative
process in which values of the design parameters are updated until they achieve the
optimal result for the optimization problem. The desired specifications of an analog circuit
for a particular circuit topology can be represented as [34]:
𝑆𝑝𝑒𝑐𝑗 = 𝑓(𝑿, 𝒀), 𝑗 = 1, 2, . . . . . . . . . . . . . . . , 𝑁 (2.1)
Where, 𝑆𝑝𝑒𝑐𝑗 indicates different desired specifications, vector 𝑿 indicates design
parameters values, vector 𝒀 indicates power supply voltage, temperature, process-related
information, etc., and 𝑁 is the number of desired specifications.
Literature Review
10
As an illustration, consider a circuit which has 𝑝 number of MOS transistors, 𝑞 number of
resistors, 𝑟 number of capacitors, and a reference current source 𝐼𝑟𝑒𝑓. The values of these
parameters are allowed to take values within a search space which is considered on the
basis of CMOS process technology, area constraints, power dissipation, etc. The values of
these parameters are found within the search space such that performance measures satisfy
a given set of constraints for the given vector 𝒀. Thus, we can represent the analog circuit
design problem as follow [34]: Find the values of 𝐿𝑖 and 𝑊𝑖 of the transistor, 𝑅𝑗, 𝐶𝑘, and
𝐼𝑟𝑒𝑓 such that,
(
𝑆𝑝𝑒𝑐1 ≤ 𝑉𝑎𝑙𝑢𝑒1 𝑜𝑟 𝑆𝑝𝑒𝑐1 ≥ 𝑉𝑎𝑙𝑢𝑒1 𝑆𝑝𝑒𝑐2 ≤ 𝑉𝑎𝑙𝑢𝑒2 𝑜𝑟 𝑆𝑝𝑒𝑐2 ≥ 𝑉𝑎𝑙𝑢𝑒2 𝑆𝑝𝑒𝑐3 ≤ 𝑉𝑎𝑙𝑢𝑒3 𝑜𝑟 𝑆𝑝𝑒𝑐3 ≥ 𝑉𝑎𝑙𝑢𝑒3
.
.
.𝑆𝑝𝑒𝑐𝑁 ≤ 𝑉𝑎𝑙𝑢𝑒𝑁 𝑜𝑟 𝑆𝑝𝑒𝑐𝑁 ≥ 𝑉𝑎𝑙𝑢𝑒𝑁 )
(2.2)
Subject to
(
𝐿𝑚𝑖𝑛 ≤ 𝐿𝑖 ≤ 𝐿𝑚𝑎𝑥 , 𝑖 = 1, 2, …… . , 𝑝𝑊𝑚𝑖𝑛 ≤ 𝑊𝑖 ≤ 𝑊𝑚𝑎𝑥 , 𝑖 = 1, 2, …… . , 𝑝𝑅𝑚𝑖𝑛 ≤ 𝑅𝑗 ≤ 𝑅𝑚𝑎𝑥 , 𝑗 = 1, 2, …… . , 𝑞
𝐶𝑚𝑖𝑛 ≤ 𝐶𝑘 ≤ 𝐶𝑚𝑎𝑥 , 𝑘 = 1, 2, …… . , 𝑟𝐼𝑚𝑖𝑛 ≤ 𝐼𝑟𝑒𝑓 ≤ 𝐼𝑚𝑎𝑥 )
(2.3)
for the given vector 𝒀.
There are many optimization methods applied for the automated circuit sizing problem in
the past as well as in recent time. In general, optimization methods are mainly classified as
gradient-based optimization (also known as classical optimization techniques), convex
optimization, and evolutionary optimization (also known as metaheuristic optimization
techniques). The gradient-based optimization techniques are effective for small size design
problems. These techniques require computation of derivatives in each iteration and also
need a good preliminary estimate for the design variables. In the absence of initial guess
close to the globally optimum solution, these techniques would normally stick at a locally
optimal solution for a Non-deterministic Polynomial-time (NP)-hard problem with large
numbers of variables and non-linear objective functions [35]. Examples of these
techniques are sequential quadratic programming [36], Levenberg-Marquardt [37],
State-of-the-Art of Automatic Analog Circuit Design
11
steepest descent method [38], and phase I-II-III method of feasible directions [39]. The
convex optimization techniques give a globally optimal result only for the convex
functions. These techniques need a very good understanding of circuit design and physical
models to prepare constraints, which would be very tough reviewing the current state-of-
the-art MOSFET models [40]. Examples of these techniques are the interior-point
algorithm [41], geometric programming, etc., [42]–[44]. The evolutionary optimization
techniques can be used to solve multimodal as well as multi-objective optimization
problems to explore the solution space more robustly [45]. These techniques do not
undergo problems related to the gradient-based and convex optimization techniques.
These techniques do not need familiarity with circuit design and physical models. These
techniques also do not require computing complex mathematical calculations, however,
they give the global optimum solution. The main EAs such as the SA, TS, GA, DE, PSO,
DE, HS, ACO, ABC algorithms have become popular in engineering applications and
other fields. As per No Free Lunch (NFL) theorem, no single algorithm is best suited to
solve all optimization problems [46].
A lot of research work has been devoted to EA-based optimization of different topologies
of fundamental CMOS based analog circuits after proper circuit topology selection step in
the analog circuit design flow [42]–[53]. The GA is a widely used optimization algorithm
by many researchers for different optimization problems. The GA is also tested for the
optimization problem related to analog circuits [59][60]. The SA, TS, and GA require
more computation time when the complexity of the design problem increases. The ACO
algorithm takes less time and is far more consistent than the GA in finding good results in
problems of transistor sizing, so it is capable of replacing GA [61]. The PSO algorithm has
been utilized for optimal sizing of the DA with a current mirror as load and the two-stage
op-amp and compared with the performance of the GA in [62]. The authors concluded that
the PSO algorithm satisfies the desired specifications with less total MOS transistor area.
The Craziness-based PSO (CRPSO) algorithm is tested for the DA with a current mirror as
load and the two-stage op-amp in [63]. The authors concluded that CRPSO based designs
outperform with the GA, PSO, and convex optimization-based designs. In [45], ultra-low
power CMOS Miller OTA and a three-stage CMOS Miller op-amp are optimized by the
GA, PSO, and Hierarchical PSO (HPSO) algorithms [64]. The authors concluded that the
HPSO algorithm converges better than the others. The PSO algorithm gives better
accuracy compared to the GA in most of the applications. The ABC, DE, and PSO
Literature Review
12
algorithms have been explored to optimize CMOS Miller OTA in [1]. The authors
concluded that the DE algorithm achieves good performance than the PSO algorithm,
whereas the ABC algorithm does not touch the goals. In [65], The ABC, DE, HS, and PSO
algorithms were used to optimize 𝑛𝑡ℎ order filters and it is concluded that the HS
algorithm is the fastest algorithm but has the maximum fault while the other algorithms
converged superiorly. In [56], the performance of the HS and DE algorithms are compared,
the authors also derived the same conclusion. The performance of the Modified PSO
(MPSO) algorithm with the standard PSO and ABC algorithms has been compared by
optimizing bulk driven OTA and two-stage CMOS op-amp and authors concluded that
MPSO gives better results than the alternatives [66]. The ABC algorithm is good at
exploration but poor at exploitation [67]. Because of this deficiency, the ABC algorithm
exhibits slower convergence speed in case of unimodal problems and traps in local
minima while solving complex multimodal optimization problems.
The CS algorithm, developed by Yang and Deb, is a population-based stochastic
metaheuristic optimization algorithm like the ABC, PSO, and DE algorithms [68][69]. But
this algorithm uses some sort of elitism and/or selection similar to that used in the HS
algorithm. The CS algorithm requires fewer parameters to be adjusted and gives more
efficient randomization compared to the PSO and DE algorithms. In [70], the performance
of the CS, DE, PSO, and ABC algorithms is analysed and compared. The authors
concluded that the CS algorithm gives more precise and robust results than the PSO and
ABC algorithms. The major applications of the CS algorithm are data clustering, data
fusion, multilevel image thresholding, flood forecasting, travelling salesman problem,
wireless sensor networks, flow shop scheduling, ontology matching, speaker recognition,
web server composition, computer games and many more real work applications as
reviewed in [71][72]. Yet, the CS algorithm has not been explored to optimize a CMOS
based analog circuit.
Each metaheuristic algorithm generally consumes considerable computing time and
requires some parameters setting to achieve a high quality of results. Each metaheuristic
algorithm has its own advantages and disadvantages. Therefore, recent researchers have
tried to develop hybrid algorithms by collaborating two or more algorithms to achieve
higher success [73][74].
Evolutionary Algorithms
13
2.3 Evolutionary Algorithms
The invention of the Evolutionary Algorithms (EAs) is generally inspired by nature
through the researcher’s community. These algorithms are goal-oriented, efficient,
flexible, and independent of the model. Most of the researchers are working on these
optimization techniques and many new modified and improved versions are frequently
invented in scientific research. In this section, the DE, PSO, and CS algorithms are briefly
described.
2.3.1 DE Algorithm
The DE algorithm is an evolutionary optimization technique developed by Storn and Price
[26]. In the DE algorithm, the formation of a new candidate solution is carried out by
calculating a weighted difference between two randomly selected population members
added to a third randomly selected population member. The DE algorithm uses the
mutation, crossover, and selection strategies of the GA. There are ten mutation techniques
for the DE algorithm as given in the literature [26][75].
DE\best\1\exp DE\rand\1\exp DE\rand-to-best\1\exp
DE\best2\exp DE\rand2\exp
DE\best\1\bin DE\rand\1\bin DE\rand-to-best\1\bin
DE\best\2\bin DE\rand\2\bin
The DE/rand/1/bin is the most commonly used technique to search for the global optimum
solution of the optimization problem [75][76]. The DE algorithm consists of two arrays,
each one holding population size 𝑁 and dimension 𝐷. The first array holds the current
vector population, while the second array holds a vector population for the next
generation. In each generation, 𝑁 competitions are carried out to get the resultant
composition of the consecutive generation. The vector differential (𝒙𝑟0 − 𝒙𝑟1) is defined
by a pair of vectors 𝒙𝑟0 and 𝒙𝑟1. Both vectors 𝒙𝑟0 and 𝒙𝑟1 are chosen randomly, and their
weighted difference is multiplied by some weighted factor which is further added to
another randomly chosen vector 𝒙𝑟2. This process can be mathematically represented by
the following equation [26][75]:
𝒗 = 𝒙𝑟2 + 𝐹 ∗ (𝒙𝑟0 − 𝒙𝑟1) (2.4)
Literature Review
14
Where, 𝒗 is a mutant vector, 𝒙 is a target vector, and 𝑟0, 𝑟1 and 𝑟2 are the random numbers
∈ 1, 2, . . . . , 𝑁. The weighting or mutation scaling factor 𝐹 is a constant supplied by the
user in the optimal range of (0.5, 1.0) which controls the amplification of the (𝒙𝑟0 − 𝒙𝑟1)
[75]. The main steps of the DE algorithm are illustrated by the flow diagram in Fig. 2.1.
f(uk,t+1) <
f(xk,t)
Input population size (N), Problem size (D),
Weighting factor (F), Crossover Rate (CR),
Number of generations, Desired fitness value
Initialize population randomly and calculate
fitness of each individual
xk,t+1 = uk,t+1
uk,t+1 = vk,t+1 if rand (0,1) < CR otherwise xk,t
vk,t+1 = xr2,t + F * (xr0,t - xr1,t)
xk,t+1 = xk.t
Yes
No
Find xGbest
Termination criteria
Desired optimized solution
Yes
Nok = N
Yes
No
FIGURE 2.1: Flowchart of the DE algorithm [75]
In Fig. 2.1, 𝒖 is a trail vector, 𝒙𝐺𝑏𝑒𝑠𝑡 is a generation best vector, 𝑡 is a generation number,
and 𝑘 = 1, 2, . . . . , 𝑁 . The termination criteria may be either a maximum number of
Evolutionary Algorithms
15
generations or a minimum value of the fitness function. The main control parameters of
the DE algorithm are 𝐹, 𝑁, and Crossover Rate (CR) [75].
2.3.2 PSO Algorithm
The PSO algorithm is basically a swarm intelligence based evolutionary algorithm
developed by Kennedy and Eberhart [27][77][78]. This algorithm is based on the flocking
behaviour and social co-operation of birds and fish schools. Each bird or fish in folk is
known as a particle in this algorithm. This algorithm finds the best optimal result using a
set of particles with different velocities and different positions. The velocities of these
particles are dynamically adjusted based on their past performance, as well as their
neighbour in the exploration space. The particles in the population change their social
performance based on their movement towards the destination. This algorithm works in an
iterative manner and finds the best solution. Suppose particle swam consists of 𝑁 number
of particles with 𝐷 dimension. The position and velocity of the 𝑘𝑡ℎ particle are
characterized by 𝒙𝑘 = [𝑥𝑘1, 𝑥𝑘2, . . . . ., 𝑥𝑘𝐷] and 𝑽𝑘 = [𝑉𝑘1, 𝑉𝑘2, . . . . . , 𝑉𝑘𝐷]. The
velocity of the 𝑘𝑡ℎ particle after each iteration is updated according to the following
equation [79][80]:
𝑉𝑘𝑑𝑡+1 = 𝜔 ∗ 𝑉𝑘𝑑
𝑡 + 𝐶1 ∗ 𝑟𝑎𝑛𝑑1 ∗ (𝑝𝑏𝑒𝑠𝑡𝑘𝑑𝑡 − 𝑥𝑘𝑑
𝑡 )
+ 𝐶2 ∗ 𝑟𝑎𝑛𝑑2 ∗ (𝑔𝑏𝑒𝑠𝑡𝑑𝑡 − 𝑥𝑘𝑑
𝑡 )
(2.5)
Here, the range of 𝑘 is 1, 2, 3, . . . , 𝑁, the range of 𝑑 is 1, 2, 3, . . . , 𝐷, the range of 𝑡 is
1, 2, 3, . . . , 𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝑖𝑡𝑒𝑟𝑎𝑡𝑖𝑜𝑛 𝑛𝑢𝑚𝑏𝑒𝑟, 𝑥𝑘𝑑𝑡 and 𝑉𝑘𝑑
𝑡 are the position and velocity of
𝑘𝑡ℎ particle in 𝑑𝑡ℎ dimension for the 𝑡𝑡ℎ iteration respectively, 𝑝𝑏𝑒𝑠𝑡𝑘𝑑𝑡 is the personal
best position of 𝑘𝑡ℎ particle in 𝑑𝑡ℎ dimension for the 𝑡𝑡ℎ iteration, 𝑔𝑏𝑒𝑠𝑡𝑑𝑡 is the 𝑑𝑡ℎ
dimension of the global best particle in the swarm for the 𝑡𝑡ℎ iteration, 𝑟𝑎𝑛𝑑1 and 𝑟𝑎𝑛𝑑2
are uniformly distributed random numbers between 0 and 1, 𝐶1 and 𝐶2 are constants
known as acceleration coefficients, 𝜔 is known as inertia weight which is initially chosen
less than one and then reduced linearly with each iteration. 𝜔 controls the influence of the
previous direction of displacement. The position of the 𝑘𝑡ℎ particle in 𝑁 × 𝐷 dimension
of the search space can be updated using a Markov chain property as [80],
𝑥𝑘𝑑𝑡+1 = 𝑥𝑘𝑑
𝑡 + 𝑉𝑘𝑑𝑡+1 (2.6)
Literature Review
16
The linear time-varying inertia weight 𝜔 can be expressed as [45],
𝜔𝑡 = (𝜔𝑚𝑎𝑥 − 𝜔𝑚𝑖𝑛) ∗(𝑡𝑚𝑎𝑥 − 𝑡)
𝑡+ 𝜔𝑚𝑎𝑥
(2.7)
Here, 𝜔𝑚𝑎𝑥 is a maximum value of 𝜔 , 𝜔𝑚𝑖𝑛 is a minimum value of 𝜔 , 𝑡𝑚𝑎𝑥 is the
maximum number of iterations, and 𝑡 is the current iteration. The main steps of the PSO
algorithm are illustrated by the flow diagram in Fig. 2.2.
Particle number
< max. number
Generate random particle’s position and velocity
Calculate fitness of each particle
For each particle update velocity and position
Yes
No
Choose the particle with the best fitness value
from all as gbest
Termination criteria
Desired optimized solution
Yes
No
pbest = Current
position
Fitness (current
particle) < fitness
(pbest)
Yes
No
Input population size (N), Problem size (D),
C1, C2,Vmax, Inertia weight (ω),
Number of iteration, Desired fitness value
FIGURE 2.2: Flowchart of the PSO algorithm [27][81]
Evolutionary Algorithms
17
2.3.3 CS Algorithm
The CS algorithm is a bio-inspired metaheuristic algorithm developed by Yang and Deb
[68]. This algorithm is motivated by the exceptional lifestyle of a bird family, called
cuckoo. The CS algorithm is more generic and robust compared to the GA, PSO, DE, and
other metaheuristic algorithms for many global optimization problems due to the
following main reasons [68][82]:
1. A fine balance of exploration and exploitation
2. Less number of control parameters
The main steps of the CS algorithm are illustrated by the flow diagram in Fig. 2.3.
Input number of nest (N), Problem size (D),
Fraction of worst nest (pa), Number of iterations,
Desired fitness value
Generate initial population of N nest and find
current best solution
Choose the nest with the best fitness value from all
as gbest
Termination criteria
Desired optimized solution
Yes
Generate cuckoo by random Lévy walk
Evaluate fitness of each cuckoo
Replace better quality cuckoo to nest
Abandon a fraction of worse nests (pa), and build
new one at new location via random walk
No
FIGURE 2.3: Flowchart of the CS algorithm [68][83]
Literature Review
18
This algorithm starts with a random initial population like many other metaheuristic
algorithms, at the same time it explores some kind of elitism and/or selection like that of
the HS algorithm [84]. Cuckoo breeding behaviour is combined with the Lévy flight
behaviour of some birds and fruit flies to find all optima in a search space with the help of
Lévy flights.
In this algorithm, each pattern relates to a nest and each individual element of the pattern
relates to a cuckoo egg. The common process equation of the CS algorithm is defined by
the following equation [68]:
𝒙𝑡+1;𝑖 = 𝒙𝑡;𝑖 + 𝛼 ⊗ 𝐿é𝑣𝑦(𝜆) (2.8)
Here, 𝒙𝑡;𝑖 is the current solution of the 𝑖𝑡ℎ cuckoo, 𝒙𝑡+1;𝑖 is the next solution generated for
the 𝑖𝑡ℎ cuckoo with Lévy flight, 𝑡 represents a number of the current generation, product
⊗ indicates the entry-wise multiplication, and 𝛼 > 0 is a scaling factor of the step size
which depends on scales of the problem of interest. For small dimension problem, 𝛼 =
𝑂(𝐿/10) is suitable whereas, for large dimension problem, 𝛼 = 𝑂(𝐿/100) is more
appropriate [71]. Big O notation is used to represent the time complexity of an algorithm.
The characteristics of the scale 𝐿 depend on the problem to be solved. In addition,
Lévy(𝜆) is a random walk using Lévy flight which is more effective in the long run
compared to a random walk used in other algorithms such as the DE, PSO, ABC, etc. This
is a global walk intended for exploration or diversification of the search space.
Lévy(𝜆) is derived from a Lévy distribution which has an infinite variance with an infinite
mean using the following equation [68]:
𝐿é𝑣𝑦~𝑢 = 𝑡−𝜆 ; 1 < 𝜆 ≤ 3 (2.9)
Where, ‘~’ means random numbers drawn from the Lévy distribution wherein the step
size follows a random walk process with a power-law distribution with heavy-tailed as
shown in Fig. 2.4 and 𝜆 is the power coefficient [85]. In Fig. 2.4, 𝑃(𝑥) is a probability
density function of a random variable 𝑥.
Evolutionary Algorithms
19
FIGURE 2.4: Lévy distribution [84]
Lévy flight has a large coverage range in a search space of the variables. Numerous new
solutions should be generated by Lévy walk near the best solution obtained. This
procedure will speed up local exploration [86]. To confirm that the algorithm will not be
trapped in a local optimum, a substantial part of the new solutions must be generated
through far-field randomization, so that location would be sufficiently far from the current
best solution. Thus, steps generated by Lévy walk can have both large and small
components, which enable the cuckoo search to do both large-scale explorations as well as
local exploitation. Such randomization can also make the algorithm more likely to jump
out of any local optima, enabling a better overall exploration ability as well as sufficiently
strong exploitation ability [72][87]. There are a few methods to generate Lévy distribution,
but one of the most efficient and yet straightforward methods is the Mantegna algorithm
[88][69]. It generates random numbers according to symmetric Lévy stable distribution
[20]. The simple way to generate a new solution using the Lévy walk is mathematically
expressed by the following equation [70]:
𝒙𝑡+1 = 𝒙𝑡 + 𝑠𝑡𝑒𝑝 𝑠𝑖𝑧𝑒 ⊗ 𝑁(0,1) (2.10)
Literature Review
20
Using the Mantegna algorithm, the step size of the random walk is calculated by the
following equation [69][70][89]:
𝑆𝑡𝑒𝑝 𝑠𝑖𝑧𝑒 = 0.01 ∗ (𝑢
|𝑣|1𝛽⁄)⨂(𝒙𝑡 − 𝒙𝑏𝑒𝑠𝑡)
(2.11)
In the above equation, 0.01 is a factor for controlling step size of cuckoo walks, 𝒙𝑡 is the
current solution, 𝒙𝑏𝑒𝑠𝑡 is the global solution, step size is the length of walk step, ⊗ is
entry-wise product, 𝑢 and 𝑣 are normally distributed stochastic variables generated from
𝑢 ~ 𝑁(0, 𝜎2) and 𝑣 ~𝑁(0, 1),and 𝜎2 is the variance given by the following equation
[69][70]:
𝜎2 = 𝛤(1 + 𝛽) ∗ 𝑠𝑖𝑛 (
𝜋𝛽
2)
𝛤 (1+𝛽
2) ∗ 𝛽 ∗ 2(
𝛽−1
2)
⁄
1𝛽⁄
(2.12)
In the above equation, 𝛤 is a gamma function which is an extension of the factorial
function of the positive number, and 𝛽 is the variable which controls distribution by 0 ≤
𝛽 ≤ 2. The value of 𝛽 equal to 1.5 is suggested in [68].
The local random walk intended for exploitation or intensification of the search space is
expressed as [70][71],
𝒙𝑡+1 = 𝒙𝑡 + 𝑟 ⊗𝐻(𝑝𝑎 − 𝑟)⊗ (𝒙𝑗 − 𝒙𝑘) (2.13)
In the above equation, 𝒙𝑗 and 𝒙𝑘 are two different solutions selected randomly, 𝐻(𝑢) is a
Heaviside function (𝐻(𝑢) = 1 if 𝑢 > 0 and 𝐻(𝑢) = 0 if 𝑢 < 0 ), 𝑝𝑎 is the discovery
probability of a cuckoo egg by a host bird which is ∈ [0, 1] , 𝑟 is a random number
generated from a uniform distribution in (0, 1).
The CS algorithm can find the desired solutions very efficiently for many global
optimization problems as presented in the literature. The pseudocode of the CS algorithm
is illustrated in Fig. 2.5.
Summary
21
2.4 Summary
Various research papers, journal, and other articles on automatic CMOS based analog
circuit design have been referred during the first phase of the literature review. Many
researchers have worked on the optimization of CMOS based analog circuits using
different EAs like SA, TS, GA, PSO, DE, ABC, ACO, etc. The CS algorithm tested for
different real-world applications in the reported literature, but none of the researcher or
inventor has worked on optimization of CMOS based analog circuit using the CS
algorithm. The CS algorithm requires a smaller number of control parameters and has a
fine balance of exploration and exploitation compared to the SA, TS, GA, PSO, DE, ACO,
and ABC algorithms. So, in this work, the application of the CS algorithm is proposed for
automated sizing of well-known CMOS based analog circuits. Research work on a hybrid
algorithm is also reported in the literature. To use the benefits of the CS and PSO
algorithms, further, the hybrid algorithm of CS and PSO algorithms is implemented and
also explored to optimize the CMOS based analog circuits. The simulation-based approach
is used for the performance evaluation of each algorithm in this work. The performance
estimation of different EAs using different standard benchmark functions is given in the
next chapter. Automation framework for analog circuit design is presented in chapter 4.
Algorithm 1: The CS Algorithm
Input: Nest size (𝑁), Problem dimension (𝐷), Fraction of worst nest (𝑝𝑎), No. of generations,
Desired fitness function value;
Output: Optimized solution;
Begin
Objective function 𝑓(𝒙), 𝒙 = (𝑥1, 𝑥2, 𝑥3…… . . 𝑥𝐷); Generate initial a population of 𝑁 host nests 𝒙𝑖 (𝑖 = 1, 2, 3, ………… ,𝑁); While (𝑡 ˂ 𝑀𝑎𝑥. 𝑔𝑒𝑛𝑒𝑟𝑎𝑡𝑖𝑜𝑛) or (𝑠𝑡𝑜𝑝 𝑐𝑟𝑖𝑡𝑒𝑟𝑖𝑎); Get a cuckoo (say 𝑖) randomly by Lévy flights;
Evaluate its quality/fitness 𝐹𝑖; Choose a nest among 𝑁 (say 𝑗) randomly;
If (𝐹𝑖 > 𝐹𝑗) then
Replace 𝑗 with the new solution;
End If
Abandon a fraction (𝑝𝑎) of worse nests and build new ones at new locations;
Keep the best solutions;
Rank the solutions and find the current best;
End While
End
FIGURE 2.5: Pseudocode of the CS algorithm [68][83]
Performance Estimation of Evolutionary Algorithms
22
CHAPTER-3
3 Performance Estimation of Evolutionary
Algorithms
3.1 Introduction
There is no algorithm which can efficiently optimize all optimization problems. And to
resolve this issue, merging two or more algorithms can be done to find the global optimum
solution for a wide range of optimization problems [85]. This chapter begins with the
concept of a hybrid algorithm. Then, benchmark functions which are generally used to test
the performance of the optimization algorithms and the parameter settings of each
algorithm are presented. At the end of the chapter, the performance of different EAs such
as the CS, hybrid CSPSO, PSO, and DE algorithms are compared by solving the set of
commonly used benchmark functions.
3.2 Hybrid CSPSO Algorithm
A hybrid algorithm is a merger of two or more algorithms that run together and
complement each other to produce a profitable synergy from their integration [90]. In
general, the outcome of hybridization makes some improvements in terms of either
computational speed or accuracy [91]–[93]. The hybridization aims to combine the
advantages of each algorithm, while simultaneously trying to minimize any substantial
disadvantages [85]. The PSO algorithm is one of the most capable optimization
algorithms. But it converges rapidly, so it has generally a premature convergence in
Hybrid CSPSO Algorithm
23
complex problems [70]. The CS algorithm is used to solve a number of complex problems
and it outperforms other optimization algorithms [71]. The CS algorithm may converge
marginally slower but it has better explorative skill. Consequently, there is some trade-off
between accuracy and convergence which is partly related to the solution diversity that an
algorithm can produce in the searching process as illustrated in Fig. 3.1 [73].
FIGURE 3.1: Trade-off between accuracy and convergence [73]
The convergence rate and global search ability can be improved using the hybrid
algorithm. It decreases the possibility of being stuck in local minima. The hybrid
algorithm of the CS and PSO algorithms can be developed to make the preeminent use of
the best features of both algorithms. The pseudocode of the hybrid CSPSO algorithm is
illustrated in Fig. 3.2.
Algorithm 1: The Hybrid CSPSO Algorithm
Input: Nest size (𝑁), Problem dimension (𝐷), Fraction of worst nest (𝑝𝑎), No. of generations,
Desired fitness function value, 𝐶1, 𝐶2, 𝑉𝑚𝑎𝑥, ω;
Output: Optimized solution;
Begin
Objective function 𝑓(𝒙), 𝒙 = (𝑥1, 𝑥2, 𝑥3…… . . 𝑥𝐷); Generate initial a population of 𝑁 host nests 𝒙𝑖 (𝑖 = 1, 2, 3, ……… . , 𝑁); While (𝑡 < 𝑀𝑎𝑥. 𝑔𝑒𝑛𝑒𝑟𝑎𝑡𝑖𝑜𝑛) or (𝑠𝑡𝑜𝑝 𝑐𝑟𝑖𝑡𝑒𝑟𝑖𝑎); Get a cuckoo (say 𝑖) randomly by Lévy flights;
Evaluate its quality/fitness 𝐹𝑖; Choose a nest among 𝑁 (say 𝑗) randomly;
If (𝐹𝑖 > 𝐹𝑗) then
Replace 𝑗 by the new solution;
End If
For each cuckoo update velocity and position according to the PSO algorithm;
Abandon a fraction (𝑝𝑎) of worse nests and build new ones at new locations;
Keep the best solutions;
Rank the solutions and find the current best;
End while
End
FIGURE 3.2: Pseudocode of the hybrid CSPSO algorithm
Performance Estimation of Evolutionary Algorithms
24
The goal of this hybridization is to inform each cuckoo about their position and helps each
cuckoo to move to a better position. In this hybrid algorithm, each cuckoo updates its
velocity and position according to the PSO algorithm. The main steps of the hybrid
CSPSO algorithm are illustrated by the flow diagram in Fig. 3.3.
Input number of nest (N), Problem Size
(D), Number of iterations, Desired fitness
value, pa , C1, C2 ,Vmax, Inertia weight (ω)
Generate initial population of N nest and
find current best solution
Choose the nest with the best fitness value
from all as gbest
Termination criteria
Desired optimized solution
Yes
Generate cuckoo by random Lévy walk
Evaluate fitness of each cuckoo
Replace better quality cuckoo to nest
Abandon a fraction of worse nests (pa) and
build new one at new location via random
walk
No
For each cuckoo update velocity and
position according to PSO algorithm
Evaluate fitness of each cuckoo and
replace better quality cuckoo to nest
FIGURE 3.3: Flowchart of the hybrid CSPSO algorithm
Benchmark Function
25
3.3 Benchmark Function
Once the optimization algorithm is implemented, it is assessed through different
benchmark functions, which is one of the best primary ways to evaluate and compare its
performance [94]–[97]. If an algorithm can produce a satisfactory solution with the
benchmark functions, then it is proven to solve the global optimization problems in most
of the cases. There are different types of such test functions available in the literature. The
commonly used functions have been selected to evaluate the performance of the CS and
hybrid CSPSO algorithms. The performance of these algorithms also has been compared
with the DE and PSO algorithms. The benchmark functions used for this work are listed
with their equation, type, the search space of x, the global optimum solution of the
function (𝒙∗), and the global minimum value of the function 𝑓(𝒙∗) in Table 3.1 [94][96].
TABLE 3.1: Standard benchmark functions
Function Equation Type Search
Space
Global
Optimum
Solution
(x*)
f(x*)
Ackley 𝑓1(𝒙) = − 20𝑒−0.2√
1
𝐷∑ 𝑥𝑖
2𝐷𝑖=1 −
𝑒1
𝐷∑ 𝑐𝑜𝑠(2𝜋𝑥𝑖)𝐷𝑖=1 + 20 + 𝑒
Multi-
modal (-32, 32) (0, …., 0) 0
Beale
𝑓2(𝒙) = (1.5 − 𝑥0 + 𝑥0𝑥1)2 +
(2.25 − 𝑥0 + 𝑥0𝑥12)2 +
(2.625 − 𝑥0 + 𝑥0𝑥13)2
Uni-
modal (-4.5, 4.5) (3, 0.5) 0
Drop-Wave 𝑓3(𝒙) = −1 + 𝑐𝑜𝑠 (12√𝑥1
2 + 𝑥22)
0.5(𝑥12 + 𝑥2
2) + 2
Multi-
modal (-5.12, 5.12) (0, 0) -1
Easom 𝑓4(𝒙) = − 𝑐𝑜𝑠(𝑥0) 𝑐𝑜𝑠(𝑥1) 𝑒𝑥𝑝 (−(𝑥0
− 𝜋)2 − (𝑥1 − 𝜋)2)
Uni-
modal (-100, 100) (π, π) -1
Griewank 𝑓5(𝒙) =
1
4000∑ 𝑥𝑖
2 −∏ 𝑐𝑜𝑠 (𝑥𝑖
√𝑖)𝐷
𝑖=1𝐷𝑖=1 +
1
Multi-
modal (-600, 600) (0, …., 0) 0
Lévy
𝑓6(𝒙) = 𝑠𝑖𝑛2(𝜋𝜔1) + ∑ (𝜔𝑖 −
𝐷−1𝑖=1
1)2 [1 + 10𝑠𝑖𝑛2(𝜋𝜔𝑖 + 1)] + (𝜔𝐷 − 1)
2[1 + 𝑠𝑖𝑛2(2𝜋𝜔𝐷)]
where 𝜔𝑖 = 1 +𝑥𝑖−1
4
Multi-
modal (-10, 10) (1, …., 1) 0
Rastrigin 𝑓7(𝒙) = 10𝐷 +∑[𝑥𝑖2 − 10 𝑐𝑜𝑠(2𝜋𝑥𝑖)]
𝐷
𝑖=1
Multi-
modal (-5.12, 5.12) (0, …., 0) 0
Rosenbrock 𝑓8(𝒙) = ∑ [100(𝑥𝑖+1 − 𝑥𝑖
2)2 +𝐷𝑖=1
(𝑥𝑖 − 1)2]
Uni-
modal (-30, 30) (1, …., 1) 0
Schaffer
𝑓9(𝒙)
= 0.5 +(𝑠𝑖𝑛 [√𝑥1
2 + 𝑥22])
2
− 0.5
(1 + 10−3[𝑥12 + 𝑥2
2])2
Multi-
modal (-100, 100) (0, 0) 0
Sphere
𝑓10(𝒙) =∑𝑥𝑖
2
𝐷
𝑖=1
Uni-
modal (-100, 100) (0, …., 0) 0
Performance Estimation of Evolutionary Algorithms
26
3.4 Experimental Settings and Results
The CS, CSPSO, PSO, and DE algorithms are implemented using the C programming
language because execution in C language is comparatively faster and use the least
memory. These algorithms are repeatedly executed on the GNU Compiler Collection
(GCC) to find the required value for each benchmark function. The performance of all
these EAs is evaluated using multimodal as well as unimodal benchmark functions with
different problem dimensions (𝐷). These experiments are performed on a system having
Intel® core™ i5, 2.40 GHz processor with 8 GB internal RAM, and Ubuntu as an
Operating System (OS).
Every algorithm has its own parameters which affect its performance in terms of solution
quality and processing time. Depending on the nature of the optimization problem and
search, different algorithms can have different values for their parameters. In the DE
algorithm, parameters F, CR, and N are relatively tough to set and some benchmark
functions are very sensitive to appropriate settings of these parameters [75]. For the PSO
algorithm, more parameters need to be set. The CS algorithm has few parameters need to
be set. For the comparative study, the size of population (𝑁) for the DE algorithm, the
number of particles (𝑁) for the PSO algorithm, the number of nests (𝑁) for the CS
algorithm, and the number of nests (𝑁) for the CSPSO algorithm have been considered
equal. In this work, the values of the remaining parameters for each algorithm are also
considered the same for all benchmark functions. However, depending on the nature of the
optimization problem or the objective function, solution quality can be improved by
changing the values of the algorithm’s parameters. The parameters for the different EAs
are set as follows:
For the DE algorithm, 𝐹 ∈ [0, 2] and the CR ∈ [0, 1] as suggested in [26]. If 𝐹 <
0.4 or 𝐹 > 1.0, then the DE algorithm is rarely effective as mentioned in [26]. If
the population converges prematurely, then F and/or 𝑁 should be increased. The
larger value of CR increases the speed of convergence. Ali and Tӧrn have obtained
an optimal value for CR = 0.5 empirically, halfway between the two parents [98].
This policy ensures that each parent’s component has a 50% chance of being
selected to produce a new point. In this work, 𝐹 = 0.8 and CR = 0.5 are chosen for
the DE algorithm as suggested in [75][98][99].
Experimental Settings and Results
27
The PSO algorithm comparatively consists of more tuning parameters which
greatly influence its performance. As mentioned in [27], a recommended choice
for 𝐶1 and 𝐶2 is 2. Clerc has reported that 𝐶1 and 𝐶2 are important factors to
ensure convergence of the PSO algorithm in [100]. Trelea has tested the PSO
algorithm for a different set of parameters for different standard benchmark
functions [101]. From his empirical study, he suggested that 𝐶1 = 𝐶2 = 1.49 gives
a higher success rate for the PSO algorithm. Shi and Eberhart have analysed the
impact of 𝜔 and 𝑉𝑚𝑎𝑥 on the performance of the PSO algorithm in [102]. The
choice of 𝑉𝑚𝑎𝑥 = 𝑥𝑚𝑎𝑥 and linear variation of 𝜔 from 0.9 to 0.4 with iterations
provide good performance on the tested benchmark functions as mentioned in
[103]. In this work, number of particles (𝑁) = 30, 𝐶1 (importance of personal best)
= 1.49, 𝐶2 (importance of neighborhood best) = 1.49, 𝑉𝑚𝑎𝑥 = 𝑥𝑚𝑎𝑥 , 𝑉𝑚𝑖𝑛 = 𝑥𝑚𝑖𝑛,
and 𝜔 varies linearly from 0.9 to 0.4 with iterations are chosen for the PSO
algorithm as recommended in [45] [101][103].
Yang and Deb have tested different benchmark functions with different values of
population size (𝑁) and 𝑝𝑎 for the CS algorithm. From their empirical study, they
have suggested that 𝑁 = 15 to 40 and 𝑝𝑎 = 0.25 are sufficient for most
optimization problems. In this work, 𝑁 = 30 and 𝑝𝑎 = 0.25 are chosen for
simulations as suggested in [68][104].
For the CSPSO algorithm, Number of nests (𝑁) = 30, 𝑝𝑎 = 0.25, 𝐶1 = 1.49, 𝐶2 =
1.49, 𝑉𝑚𝑎𝑥 = 0.1 ∗ 𝑥𝑚𝑎𝑥 , 𝑉𝑚𝑖𝑛 = 0.1 ∗ 𝑥𝑚𝑖𝑛, and 𝜔 varies linearly from 0.9 to 0.4
with iterations are chosen.
The solution obtained by any EA to solve an objective function 𝑓(𝒙) with the solution
search space of a variable [𝑥𝑗,𝑚𝑖𝑛, 𝑥𝑗,𝑚𝑎𝑥] 𝑗 = 1,2,………… ,𝐷 is represented by a 𝒙 =
(𝑥1, 𝑥2, . . . . . . . . . . , 𝑥𝐷). Here, 𝑥𝑗,𝑚𝑖𝑛 is a minimum value of a variable 𝑥𝑗 and 𝑥𝑗,𝑚𝑎𝑥 is a
maximum value of a variable 𝑥𝑗 . In the initialization phase, each algorithm randomly
generates a solution vector which is sampled from the search space [𝑥𝑗,𝑚𝑖𝑛, 𝑥𝑗,𝑚𝑎𝑥]. The
initial values of the 𝑗𝑡ℎ attributes of the 𝑖𝑡ℎ pattern have been generated as [105],
𝑥𝑖,𝑗 = 𝑥𝑖,𝑗,𝑚𝑖𝑛 + 𝑟 ∗ (𝑥𝑖,𝑗,𝑚𝑎𝑥 − 𝑥𝑖,𝑗,𝑚𝑖𝑛) 𝑖 = 1, 2, ………… ,𝑁 (3.1)
Performance Estimation of Evolutionary Algorithms
28
In (3.1), 𝑟 represents a uniformly distributed random variable with the range (0, 1). This
randomly generated solution vector is given to a test function. Based on the results of the
test function, the algorithm will update the value of the solution vector. This process is
iterative until termination criteria are not fulfilled. The termination criteria are either a
minimum value of the function or a maximum number of iterations. These criteria are
selected based on the complexity of the optimization problem and requirement of quality
of solutions. A tolerance for the variation of function value is considered ≤ 1e-6. The
maximum number of iterations for the benchmark function testing are considered 30000.
Being a stochastic search process, a statistical study is required to compare the consistency
of the different EAs and their quality of solutions. Therefore, each benchmark function is
solved by the CS, CSPSO, DE, and PSO algorithms for 100 independent runs with
different random seeds. The performance of each EA is evaluated based on different
performance criteria such as success rate, simulation time, a standard deviation of a
function value, an average number of iterations, and an average number of function
evaluations in our experimental studies.
Standard deviation of a function value: The best value of a function 𝑓(𝒙) that each
algorithm can find is recorded in each run. The minimum, maximum, mean, and
standard deviation of the best function values are calculated. The minimum,
maximum, mean, and standard deviation of the best function values are denoted as
‘𝑀𝑖𝑛𝑓’, ‘𝑀𝑎𝑥𝑓’, ‘𝑀𝑒𝑎𝑛𝑓’, and ‘𝑆𝐷𝑓’ respectively.
Average number of iterations: The number of iterations is also recorded in
different runs when each algorithm finds the targeted value of the function within
the maximum number of iterations. Then, the average number of iterations is
calculated based on the number of runs. It is denoted as ‘𝐼𝑡𝑒𝑟𝑎𝑣𝑔’.
Average number of function evaluations: The number of function evaluations is
also recorded in different runs when each algorithm finds the targeted value of the
function within the termination criteria. Then, the average number of function
evaluations is calculated based on the number of runs. It is denoted as ‘𝐹𝐸𝑎𝑣𝑔’.
Success rate: The number of successful runs is recorded when the function value
reaches the targeted value within a maximum number of iterations. It is denoted as
‘𝑆𝑟𝑎𝑡𝑒’.
Experimental Settings and Results
29
Simulation time: The total simulation time is recorded for all runs of the function
taken by each algorithm in the respective experiment. It is denoted as ‘𝑇𝑠𝑖𝑚’.
TABLE 3.2: Performance evaluation of different EAs with different benchmark functions
Algori-
thm
Fun-
ction 𝑫 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆
𝑻𝒔𝒊𝒎
(s)
DE
𝑓1(𝒙) 10
9.1e-7 1.7e-5 1.1e-6 2.0e-6 21419 642608 99 110.77
PSO 6.5e-7 19.93 3.9e-1 2.79 4234 127025 98 24.27
CS 6.9e-7 1.0e-6 9.1e-7 0.0 1318 79121 100 24.39
CSPSO 5.7e-7 1.0e-6 9.1e-7 0.0 1090 98202 100 36.70
DE
𝑓2(𝒙) 2
1.0e-6 2.0e-1 9.3e-3 2.4e-2 30000 900030 0 33.86
PSO 2.3e-8 7.6e-1 7.6e-3 7.5e-2 580 17400 99 0.83
CS 1.2e-8 9.9e-7 5.1e-7 0.0 152 9165 100 0.60
CSPSO 1.2e-8 9.9e-7 5.5e-7 0.0 83 7524 100 0.37
DE
𝑓3(𝒙) 2
1.7e-9 9.8e-7 3.1e-7 0.0 76 2319 100 0.08
PSO 0.0 1.0e-6 3.3e-7 0.0 43 1286 100 0.04
CS 3.1e-10 1.0e-6 3.0e-7 0.0 9 576 100 0.05
CSPSO 2.3e-11 1.0e-6 3.0e-7 0.0 7 669 100 0.04
DE
𝑓4(𝒙) 2
8.9e-6 1.3e-1 7.0e-3 1.5e-2 30000 900030 0 32.04
PSO 5.6e-9 1.0e-6 5.5e-7 0.0 583 17491 100 0.92
CS 2.0e-8 1.0e-6 5.2e-7 0.0 944 56701 100 5.74
CSPSO 1.9e-8 1.0e-6 5.2e-7 0.0 764 68759 100 5.78
DE
𝑓5(𝒙) 10
9.8e-7 5.2e-1 1.4e-1 1.3e-1 29892 896811 8 128
PSO 6.8e-7 8.4e-2 3.4e-2 1.7e-2 29514 885544 2 111
CS 6.5e-7 4.6e-2 1.9e-2 1.2e-2 27787 1667298 9 526
CSPSO 7.3e-7 4.7e-2 1.7e-3 1.1e-2 27047 2434260 12 219
DE
𝑓6(𝒙) 10
8.3e-5 3.1e-1 2.5e-2 4.3e-2 30000 900030 0 144.62
PSO 4.4e-5 3.99 7.8e-2 5.6e-1 898 26948 98 4.91
CS 3.9e-7 1.0e-6 8.0e-7 0.0 901 54145 100 18.73
CSPSO 2.5e-7 9.9e-1 1.9e-2 1.4e-1 1106 99580 98 29.66
DE
𝑓7(𝒙) 10
9.8e-7 7.65 4.9e-1 1.18 29968 899099 5 85.19
PSO 6.4e-7 29.92 1.94 5.74 18209 546283 47 70.84
CS 2.1e-7 4.97 6.5e-1 9.4e-1 18618 1117138 57 305
CSPSO 4.2e-7 3.98 6.3e-1 8.5e-1 18617 1675621 55 366
DE
𝑓8(𝒙) 10
7.51 933.81 321.59 188.21 30000 900030 0 62.14
PSO 1.0e-6 90002 10813 29242 29892 896789 1 107
CS 4.1e-7 1.0e-6 8.2e-7 0.0 1576 94638 100 23.01
CSPSO 2.5e-7 1.0e-6 8.0e-7 0.0 1330 119761 100 31.19
DE
𝑓9(𝒙) 2
8.7e-7 1.0e-6 9.6e-7 0.0 5236 157098 100 6.34
PSO 0.0 1.0e-6 4.5e-7 0.0 786 23595 100 0.83
CS 1.8e-9 1.0e-6 5.8e-7 0.0 1240 74484 100 5.72
CSPSO 7.8e-9 1.0e-6 5.5e-7 0.0 476 42949 100 2.67
DE
𝑓10(𝒙) 10
9.0e-7 1.0e-6 9.9e-7 0.0 4653 139635 100 8.78
PSO 3.2e-7 1.0e-6 8.7e-7 0.0 3102 93065 100 10.47
CS 2.8e-7 1.0e-6 8.2e-7 0.0 704 42248 100 10.30
CSPSO 3.7e-7 1.0e-6 8.2e-7 0.0 480 43329 100 7.85
Performance Estimation of Evolutionary Algorithms
30
The performance criteria of each EA for different benchmark functions are tabulated in
Table 3.2. In which, Beale 𝑓2(𝒙) , Drop-Wave 𝑓3(𝒙) , Easom 𝑓4(𝒙)and Schaffer 𝑓9(𝒙)
functions are 2-D optimization problems and Ackley 𝑓1(𝒙), Griewank 𝑓5(𝒙), Lévy 𝑓6(𝒙),
Rastrigin 𝑓7(𝒙), Rosenbrock 𝑓8(𝒙), and Sphere 𝑓10(𝒙) functions are 10-D optimization
problems. In this table, the optimum values of different criteria obtained by the EA are
shown in bold letters. Ackley, Griewank, Lévy, Rastrigin, Rosenbrock, and Sphere
functions are also solved using each EA independently with 20-D as well as 30-D
optimization problems. The performance criteria of each EA for 20-D benchmark
functions are tabulated in Table 3.3.
TABLE 3.3: Performance evaluation of different EAs with 20-D benchmark functions
Algori-
thm
Fun-
ction 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆
𝑻𝒔𝒊𝒎
(s)
DE
𝑓1(𝒙)
9.6e-5 4.01 1.1e-6 2.69 30000 1200040 0 308
PSO 8.4e-7 19.95 7.1e-1 3.49 6062 242468 96 85
CS 7.7e-7 1.16 2.3e-2 1.6e-1 3752 300242 98 191
CSPSO 7.8e-7 1.16 2.3e-2 1.6e-1 3116 373976 98 173
DE
𝑓5(𝒙)
9.6e-7 9.5-1 1.5e-1 2.9e-1 17152 686130 69 178
PSO 7.6e-7 22.54 2.7e-1 2.24 28243 1129730 7 309
CS 7.1e-7 1.2e-2 5.9e-4 2.2e-3 5362 429045 93 264
CSPSO 6.3e-7 7.3e-3 2.9e-4 1.5e-3 4103 492490 96 251
DE
𝑓6(𝒙)
6.6e-4 3.2e-1 6.6e-2 7.2e-2 30000 1200040 0 365
PSO 5.8e-7 10.12 1.46 2.55 11629 465160 71 166
CS 5.6e-7 1.98 2.9e-2 2.2e-1 2842 227442 98 158
CSPSO 7.3e-7 1.98 3.8e-1 5.6e-1 11184 1342172 66 813
DE
𝑓7(𝒙)
7.48 30.39 15.74 4.68 30000 1200040 0 218
PSO 2.99 63.82 17.80 16.45 30000 1200000 0 313
CS 8.2e-7 9.95 2.23 1.91 28772 2297857 14 1246
CSPSO 7.9e-7 11.94 2.88 2.01 29117 3494106 7 1492
DE
𝑓8(𝒙)
344.56 2982.78 1014 483 30000 1200040 0 190
PSO 9.9e-7 90008 14861 32811 29592 1183698 3 250
CS 5.7e-7 3.99 4.8e-1 1.30 7859 628766 88 293
CSPSO 5.5e-7 3.99 4.4e-1 1.25 7260 871286 89 459
DE
𝑓10(𝒙)
9.8e-7 1.0e-6 1.0e-6 0.0 9696 387884 100 42
PSO 6.1e-7 1.0e-6 9.2e-7 0.0 4445 177802 100 34
CS 7.3e-7 1.0e-6 9.3e-7 0.0 1676 134152 100 62
CSPSO 5.7e-7 1.0e-6 9.2e-7 0.0 1434 172220 100 69
For 20-D optimization problems, the size of population (𝑁) for the DE algorithm, the
number of particles (𝑁) for the PSO algorithm, the number of nests (𝑁) of the CS
algorithm, and the number of nests (𝑁) for the CSPSO algorithm are changed to 40 in
Experimental Settings and Results
31
place of 30 which was set previously in the case of 10-D benchmark functions presented
in Table 3.2. Other parameters of all algorithms are unaltered.
The performance criteria of each EA for 30-D benchmark functions are tabulated in Table
3.4. For the 30-D optimization problems, the value of 𝑁 for each algorithm is changed to
60 in place of 40 set previously in the case of 20-D benchmark functions. Other
parameters of all algorithms are unchanged.
TABLE 3.4: Performance evaluation of different EAs with 30-D benchmark functions
Algori-
thm
Fun-
ction 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆
𝑻𝒔𝒊𝒎
(s)
DE
𝑓1(𝒙)
3.30 6.43 4.30 7.7e-1 30000 1800060 0 720
PSO 7.6e-7 19.96 4.41 7.01 12887 773255 71 434
CS 8.5e-7 1.16 4.9e-2 2.1e-1 6469 776356 95 644
CSPSO 8.4e-7 1.0e-6 9.7e-7 0.0 2807 505453 100 355
DE
𝑓5(𝒙)
9.7e-7 9.9-1 2.3e-1 3.8e-1 22611 1356756 74 547
PSO 6.9e-7 23.48 1.84 6.18 24057 1443456 24 590
CS 7.2e-7 1.0e-6 9.5e-7 0.0 3802 456373 100 420
CSPSO 7.3e-7 1.0e-6 9.4e-7 0.0 3272 589036 100 450
DE
𝑓6(𝒙)
1.3e-3 1.12 1.2e-1 2.3e-1 30000 1800060 0 811
PSO 8.5e-7 38.35 7.48 7.29 25273 1516390 19 780
CS 6.7e-7 1.0e-6 9.3e-7 0.0 3710 445273 100 441
CSPSO 6.7e-7 1.98 3.9e-1 5.8e-1 11835 2130421 65 1703
DE
𝑓7(𝒙)
10.62 30.71 19.23 4.47 30000 1800060 0 460
PSO 9.95 154.57 70.44 31.76 30000 1800000 0 764
CS 8.4e-7 9.95 3.57 2.12 29989 3598790 2 3166
CSPSO 8.8e-7 12.94 3.63 2.67 29952 5391439 2 4150
DE
𝑓8(𝒙)
1281 7125 3466 1055 30000 1800060 0 371
PSO 4.3e-6 90072 20247 37064 30000 1800000 0 554
CS 6.5e-7 3.99 4.8e-1 1.30 11696 1403602 88 1011
CSPSO 6.8e-7 3.99 1.6 e-1 7.8e-1 9443 1699873 96 1059
DE
𝑓10(𝒙)
9.9e-7 1.0e-6 1.0e-6 0.0 15516 931017 100 134
PSO 7.1e-7 20000 800 3059 6934 416015 93 99
CS 7.9e-7 1.0e-6 9.4e-7 0.0 2584 310190 100 211
CSPSO 6.8e-7 1.0e-6 9.3e-7 0.0 2221 399921 100 208
From Table 3.2, Table 3.3, and Table 3.4, it can be concluded that the average number of
iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) taken by the CS and CSPSO algorithms to reach the targeted function
value for most of the benchmark functions are less compared to the PSO and DE
algorithms. The CS and CSPSO algorithms also acquire a lower standard deviation of the
function value (𝑆𝐷𝑓) and achieve a higher success rate (𝑆𝑟𝑎𝑡𝑒) compared to the DE and
Performance Estimation of Evolutionary Algorithms
32
PSO algorithms for most of the test functions. Thus, The CS and CSPSO algorithms
outperform for the majority of the tested functions compared to the PSO and DE
algorithms. The PSO algorithm requires the least average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔),
average function evaluations (𝐹𝐸𝑎𝑣𝑔) , and simulation time (𝑇𝑠𝑖𝑚) for Easom function
compared to the CS and CSPSO algorithms as listed in Table 3.2. The PSO algorithm also
outperforms the CS algorithm for Schaffer function as listed in Table 3.2.
The convergence graphs of Beale, Drop-Wave, Easom, and Schaffer functions with 2-D
and Ackley, Lévy, Griewank, Rastrigin, Rosenbrock, and Sphere functions with 30-D
optimized by the CS, PSO, hybrid CSPSO, and DE algorithms are shown in Fig. 3.4 to
Fig. 3.13. The convergence graph of the particular function shows the average function
value performance of all runs with respect to iterations in the respective experiment. The
vertical axis is the average of the best function value obtained by the algorithm in each
iteration and the horizontal axis is the number of iterations.
FIGURE 3.4: Convergence graph of 30-D Ackley function for the CS, PSO, CSPSO, and DE
algorithms
Experimental Settings and Results
33
FIGURE 3.5: Convergence graph of 2-D Beale function for the CS, PSO, CSPSO, and DE algorithms
FIGURE 3.6: Convergence graph of 2-D Drop-Wave function for the CS, PSO, CSPSO, and DE
algorithms
Performance Estimation of Evolutionary Algorithms
34
FIGURE 3.7: Convergence graph of 2-D Easom function for the CS, PSO, CSPSO, and DE algorithms
FIGURE 3.8: Convergence graph of 30-D Griewank function for the CS, PSO, CSPSO, and DE
algorithms
Experimental Settings and Results
35
FIGURE 3.9: Convergence graph of 30-D Lévy function for the CS, PSO, CSPSO, and DE algorithms
FIGURE 3.10: Convergence graph of 30-D Rastrigin function for the CS, PSO, CSPSO, and DE
algorithms
Performance Estimation of Evolutionary Algorithms
36
FIGURE 3.11: Convergence graph of 30-D Rosenbrock function for the CS, PSO, CSPSO, and DE
algorithms
FIGURE 3.12: Convergence graph of 2-D Schaffer function for the CS, PSO, CSPSO, and DE
algorithms
Summary
37
FIGURE 3.13: Convergence graph of 30-D Sphere function for the CS, PSO, CSPSO, and DE
algorithms
From the convergence graph of different benchmark function obtained by the different
EAs, shown in Fig. 3.4 to Fig. 3.13, it can be observed that the CS and CSPSO algorithms
give a better solution with higher convergence speed compared to the PSO and DE
algorithms except for Easom function. The PSO algorithm also converged faster compared
to the CS algorithm for Schaffer function and converged faster than the CS and CSPSO
algorithms for Easom function.
3.5 Summary
After reviewing the previously published literature for the targeted problem, special
attention is paid to the implementation of widely used and promising EAs. In this chapter,
the focus is set on the performance evaluation of different metaheuristic EAs using
different unimodal and multimodal benchmark functions. In this chapter, a hybrid
algorithm of the CS and PSO algorithms is also presented. The concept of the hybrid
algorithm of two or more algorithms plays a prominent role to improve searching
capabilities of an algorithm and convergence rate. The limitation of the hybrid algorithm is
Performance Estimation of Evolutionary Algorithms
38
that it requires more function evaluations per iteration which may increase total
convergence time. All these algorithms have been considered for the optimization of the
commonly used analog circuits, which is presented in the next chapter. These algorithms
take the circuit performance specifications as an objective function considering the various
constraints.
Introduction
39
CHAPTER-4
4 Analog Circuit Optimization
4.1 Introduction
This chapter is dedicated toward exploring the EAs for the optimization process of CMOS
based analog circuits. The problem considered here is the optimal selection of transistor
dimensions, which is only a part of a completely analog circuit CAD tool. The task of the
EA during the optimization process of a CMOS based analog circuit is to find the suitable
values for the design parameters of the particular circuit in a way that all the desired
specifications for that circuit get satisfied. Usually, this process is termed as an automatic
circuit sizing. The number of design parameters for a particular circuit depends on the
circuit configuration. The main design parameters of a CMOS based analog circuit are the
width (𝑊) and length (𝐿) of different NMOS and PMOS transistors, bias current (𝐼𝑏𝑖𝑎𝑠),
resistance (𝑅) , and capacitor (𝐶). For a CMOS based analog circuit, the major
performance specifications may be open-loop DC gain (𝐴𝑣) , Unity Gain Bandwidth
(UGB), Phase Margin (PM), Common Mode Rejection Ratio (CMRR), Slew Rate (SR),
Power Supply Rejection Ratio (PSRR), DC Power dissipation (𝑃𝑑𝑖𝑠𝑠), etc.
In this chapter, the circuit optimization methodology framework is presented first. The
complexity of an analog circuit design problem is proportional to the number of design
parameters and the number of desired specifications of a particular circuit. So, initially,
optimization of simple CMOS based analog circuits with a few design parameters are
presented. Then, the optimization of moderately complex CMOS based analog circuits
with more design parameters and specifications are presented. The list of optimized
Analog Circuit Optimization
40
CMOS based analog circuits with different CMOS technologies by employing different
EAs in this work is listed in Table 4.1.
TABLE 4.1: List of optimized CMOS based analog circuits
Sr. No. CMOS based Circuit CMOS Technology
1 Triple cascode current mirror
0.18 µm
2 Common-source amplifier
3 Voltage divider
4 Three-stage current starved VCO
5 Cascode amplifier
6 DA with a current mirror load
0.35 µm and 0.18 µm 7 Two-stage op-amp
8 Folded cascode OTA
9 Miller OTA
4.2 Automated Circuit Design Methodology
For the CMOS based analog circuits design, some relation between the circuit parameters
such as channel width (𝑊) and channel length (𝐿) of the MOS transistors should be
maintained to obtain the desired specifications. The framework of the automated CMOS
based analog circuit design is illustrated in Fig. 4.1. This framework is a part of the larger
design automation tool and topology selection is done before this framework. Therefore,
in this system, it is assumed that circuit topologies are fixed and selected by the user.
This system consists of an optimizer and a SPICE simulation environment to design a
CMOS based analog circuit for the desired specifications. The optimizer uses an EA
which is used to optimize the design parameters of a circuit for the targeted specifications,
while the validity of the solution obtained by the EA is checked by simulating the
designed circuit functionally with Ngspice circuit simulator [106]. A SPICE netlist of each
circuit is developed to simulate the designed circuits for the targeted specifications. While
exploring for optimized design parameters of the circuit that gives desired specifications,
transistors of the design circuit should operate in the saturation region. This constraint has
been taken care off in SPICE netlist of the circuit by considering Voltage Transfer
Characteristic (VTC) and suitable bias point in the saturation region. This SPICE netlist is
given as input to the circuit simulator. A software interface provides proper
synchronization between the circuit simulator and the optimizer. A script file is developed
Automated Circuit Design Methodology
41
for the software interface. The different parameters of an EA, the design parameters of a
particular circuit, and desired specifications are given to the circuit optimizer as input.
Initially, the different design parameters are arbitrarily generated by the EA within their
predefined range. These generated design parameter values are given to the circuit
simulator.
Input algorithm parameters,
Desired specifications,
Design parameters
Optimizer
Termination criteria
Desired optimized solution
Yes
Software interface
Circuit simulator
Record simulated specifications
No
Calculation of fitness function
SPICE netlist
FIGURE 4.1: Automated circuit design methodology framework
Based on the results obtained by the circuit simulator, the value of a fitness function for
the circuit is calculated using the following equation [45]:
𝐹𝑖𝑡𝑛𝑒𝑠𝑠 𝐹𝑢𝑛𝑐𝑡𝑖𝑜𝑛 = √∑(𝑆𝑝𝑒𝑐𝑖𝑓𝑖𝑐𝑎𝑡𝑖𝑜𝑛𝑑𝑒𝑠𝑖𝑟𝑒𝑑 − 𝑆𝑝𝑒𝑐𝑖𝑓𝑖𝑐𝑎𝑡𝑖𝑜𝑛𝑠𝑖𝑚𝑢𝑙𝑎𝑡𝑒𝑑
𝑆𝑝𝑒𝑐𝑖𝑓𝑖𝑐𝑎𝑡𝑖𝑜𝑛𝑑𝑒𝑠𝑖𝑟𝑒𝑑)𝑗
2𝐷
𝑗=1
(4.1)
In (4.1), 𝐷 is a number of the desired specifications. The Root Mean Square (RMS) error
offers the same weightage to all the specifications. So, the optimizer tries to gratify all the
Analog Circuit Optimization
42
specifications with equal importance. Next step is to check for the termination criteria and
if they are satisfied, then the optimization process will stop. The termination criteria are
either a minimum value of the fitness function or a maximum number of iterations. For
this work, the minimum value for the fitness function is considered 1e-6 and the maximum
number of iterations is considered 100. If it fails to reach the termination criteria, then a
new set of design parameters will be generated by the EA. The main job of the optimizer
is to decrease the value of the fitness function for the given circuit with each iteration and
to reach the desired value for the fitness function. The efficiency of the optimizer is highly
dependent on algorithm parameters, a number of design parameters of a circuit, search
space of the design parameters, and a number of the desired specifications.
In this work, the CS, hybrid CSPSO, PSO, and DE algorithms are tested by optimizing the
commonly used CMOS based analog circuits for the given specifications independently.
The parameters of each algorithm for the optimization process of an analog circuit are set
similar to those used for the benchmark function experiments as presented in the previous
chapter. The parameter settings of the DE, PSO, CS, and hybrid CSPSO algorithms for the
optimization process of an analog circuit are listed in Table 4.2.
TABLE 4.2: Parameter settings of the DE, PSO, CS, and CSPSO algorithms
Sr.
No.
Parameters of
DE algorithm
Parameters of
PSO algorithm
Parameters of
CS algorithm
Parameters of
CSPSO algorithm
1 Size of populations
(𝑁) = 30
Number of particles
(𝑁) = 30
Number of
nests (𝑁) = 30
Number of nests
(𝑁) = 30
2 CR = 0.5 𝐶1 = 1.49 𝑝𝑎 = 0.25 𝑝𝑎 = 0.25
3 F = 0.8 𝐶2 = 1.49 --- 𝐶1 = 1.49
4 --- 𝑉𝑚𝑎𝑥 = 𝑥𝑚𝑎𝑥 --- 𝐶2 = 1.49
5 --- 𝑉𝑚𝑖𝑛 = 𝑥𝑚𝑖𝑛 --- 𝑉𝑚𝑎𝑥 = 0.1 ∗ 𝑥𝑚𝑎𝑥
6 --- 𝜔 varies linearly from
0.9 to 0.4 with iterations --- 𝑉𝑚𝑖𝑛 = 0.1 ∗ 𝑥𝑚𝑖𝑛
7 --- --- --- 𝜔 varies linearly from
0.9 to 0.4 with iterations
The test for each circuit design problem is repeated 10 times independently and results
have been recorded. The performance of the CS and CSPSO algorithms for the
optimization of CMOS based analog circuits are compared with the DE and PSO
algorithms based on success rate (𝑆𝑟𝑎𝑡𝑒), simulation time (𝑇𝑠𝑖𝑚), standard deviation of the
fitness function (𝑆𝐷𝑓), average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔), and average number of
function evaluations (𝐹𝐸𝑎𝑣𝑔).
Simple CMOS based Analog Circuit Optimization
43
4.3 Simple CMOS based Analog Circuit Optimization
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms is initially evaluated
with some simple CMOS based analog circuits such as a triple cascode current mirror,
common-source amplifier, voltage divider, three-stage current starved VCO, and cascode
amplifier. Theoretical discussion and manual design procedure of all these circuits can be
found in [2][107][108]. All these circuits are simulated using BSIM3v3 MOSFET models
in 0.18 µm CMOS technology at room temperature 27º C and supply voltage of ±1.8 V.
4.3.1 Triple Cascode Current Mirror
FIGURE 4.2: Triple cascode current mirror [107]
Current mirror circuit is an essential building block for analog circuit design. It is used to
provide bias currents and active loads to circuits. There are a number of current mirror
topologies available in the literature. The triple cascode current mirror circuit is chosen for
the optimization process in this work. This configuration is used to increase the output
Analog Circuit Optimization
44
resistance of a current source or sink. Achieving high output resistance means the output
current does not vary much with the voltage across the current source. The circuit diagram
of the triple cascode current mirror consisting of six MOS transistors M1, M2, M3, M4,
M5, M6, and one resistor R1 is shown in Fig. 4.2. Here, the length (𝐿) for each transistor
is considered identical i.e. 𝐿 = 0.18 µm. Similarly, the width (𝑊) for each transistor is
considered as 𝑊1. Therefore, this circuit has two design parameters namely 𝑊1 and 𝑅1.
The search space and optimized values achieved by different EAs for the design
parameters of this circuit are listed in Table 4.3.
TABLE 4.3: Search space and optimized parameters by different EAs for triple cascode current
mirror
Sr.
No.
Design
Parameters
Search Space of
Design
Parameters
Optimized Values of Design Parameters
PSO DE CS CSPSO
1 𝑊1 (µm) 1 µm to 1000 µm 203.14 873.73 247.43 254.25
2 𝑅1 (kΩ ) 1 kΩ to 1000 kΩ 84.42 100.87 86.70 87.01
Table 4.4 reveals the desired specifications and obtained specifications through simulation
for the above-optimized design parameters achieved by employing the different EAs for
this circuit. The number of desired specifications, in this case, are two i.e. reference
current (𝐼𝑟𝑒𝑓) and output current (𝐼𝑜𝑢𝑡). From Table 4.4, it can be observed that the
specifications obtained by the CS and CSPSO algorithms are closer to the desired
specifications compared to those obtained by the PSO and DE algorithms.
TABLE 4.4: Desired specifications and simulation results by different EAs for triple cascode current
mirror
Sr.
No.
Desired
Specifications
Obtained Specifications
PSO DE CS CSPSO
1 𝐼𝑟𝑒𝑓 = 10 µA 10.008130 µA 9.972642 µA 10.000000 µA 10.000000 µA
2 𝐼𝑜𝑢𝑡 = 10 µA 10.007990 µA 9.973582 µA 9.999994 µA 10.000010 µA
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit for 10 independent runs are listed in Table 4.5. From which, it can be
observed that success rate (𝑆𝑟𝑎𝑡𝑒) for the CS algorithm is 2 and for the CSPSO algorithm
is 1, while the DE and PSO algorithms fail to achieve the targeted specifications. The
CSPSO algorithm gives the least standard deviation for the fitness function value (𝑆𝐷𝑓)
i.e. 3.0e-6 compared to the CS, PSO, and DE algorithms. The average number of iterations
Simple CMOS based Analog Circuit Optimization
45
(𝐼𝑡𝑒𝑟𝑎𝑣𝑔) consumed for 10 independent runs of the optimization process of this circuit are
93 and 96 for the CS and hybrid CSPSO algorithms respectively. The CS and CSPSO
algorithms consumed the more average number of function evaluations (𝐹𝐸𝑎𝑣𝑔) and
simulation time (𝑇𝑠𝑖𝑚) compared to the PSO and DE algorithms.
TABLE 4.5: Performance of different EAs for optimization of triple cascode current mirror
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 7.8e-5 1.3e-1 1.4e-2 4.0e-2 100 3030 0 468
PSO 1.0e-4 2.9e-3 1.4e-3 8.9e-4 100 3000 0 483
CS 6.0e-7 2.0e-5 7.4e-6 7.0e-6 93 5646 2 877
CSPSO 1.0e-6 9.9e-6 5.0e-6 3.0e-6 96 8652 1 1575
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the triple cascode
current mirror is shown in Fig. 4.3 which shows that the CS and CSPSO algorithms give
lower average fitness value for 10 runs with higher convergence speed compared to the
PSO and DE algorithm.
FIGURE 4.3: Convergence graph of different EAs for triple cascode current mirror
Analog Circuit Optimization
46
4.3.2 Common-Source Amplifier
The common-source amplifier is one of the three basic single-stage MOS amplifier
topologies. It is used as a voltage or transconductance amplifier. The circuit diagram of the
common-source amplifier with current mirror active load consisting of one NMOS
transistor M1, two PMOS transistors M2 and M3, and one resistor R1 is shown in Fig. 4.4.
In this circuit, M1 is in a common-source configuration, M2 is an active load, and M3 is a
diode-connected transistor which mirrors current into M2. This circuit has very high input
resistance and also high output resistance. The common-source amplifier is commonly
part of a larger amplifier circuit. For this circuit optimization, the length (𝐿) for each
transistor is considered identical i.e. 𝐿 = 0.18 µm. Similarly, the width (𝑊) for each
transistor is considered as 𝑊1 for this circuit. Therefore, this circuit has two design
parameters namely 𝑊1 and 𝑅1.
FIGURE 4.4: Common-source amplifier [108]
The search space and optimized values achieved by different EAs for the design
parameters of this circuit are listed in Table 4.6.
TABLE 4.6: Search space and optimized parameters by different EAs for common-source amplifier
Sr. No. Design
Parameters
Search Space of
Design
Parameters
Optimized Values of Design Parameters
PSO DE CS CSPSO
1 𝑊1 (µm) 1 µm to 10 µm 1.75 4.63 3.29 4.25
2 𝑅1 (kΩ ) 1 kΩ to 100 kΩ 43.7 83.59 31.94 76.11
Simple CMOS based Analog Circuit Optimization
47
The desired specifications and obtained specifications through simulation for the
optimized design parameters achieved by employing the different EAs for this circuit are
listed in Table 4.7. The number of desired specifications for this circuit are three i.e. 𝐴𝑣,
UGB, and PM. This circuit is simple to design, so all EAs easily achieved all the required
specifications during the optimization process.
TABLE 4.7: Desired specifications and simulation results by different EAs for common-source
amplifier
Sr.
No.
Desired
Specifications
Obtained Specifications
PSO DE CS CSPSO
1 𝐴𝑣 > 25 dB 28.43 dB 29.28 dB 28.93 dB 29.27 dB
2 UGB > 50 MHz 59.81 MHz 55.75 MHz 96.04 MHz 58.63 MHz
3 PM > 45° 92.08° 91.77° 91.89° 91.78°
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit for 10 independent runs are listed in Table 4.8. The PSO algorithm takes the
least simulation time (𝑇𝑠𝑖𝑚) i.e. 68.30 seconds compared to all other algorithms for the
optimization of this circuit for the targeted specifications.
TABLE 4.8: Performance of different EAs for the optimization of common-source amplifier
Algorithm 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 0.0 1 60 10 137.20
PSO 0.0 1 30 10 68.30
CS 0.0 1 90 10 119.50
CSPSO 0.0 1 120 10 265.65
4.3.3 Voltage Divider
In CMOS IC design, reference voltages are derived from the power supplies using a
CMOS voltage divider. The circuit diagram of a voltage divider consisting of four MOS
transistors M1, M2, M3, and M4 is shown in Fig. 4.5. The length (𝐿) for each transistor is
considered identical i.e. 𝐿 = 0.18 µm and the width for M1, M2, M3, and M4 transistors is
considered as 𝑊1, 𝑊2, 𝑊3, and 𝑊4 respectively for this circuit sizing process. This circuit
has four design parameters namely 𝑊1, 𝑊2, 𝑊3, and 𝑊4 as observed from Fig. 4.5. The
search space and optimized values achieved by different EAs for the design parameters of
this circuit are listed in Table 4.9.
Analog Circuit Optimization
48
FIGURE 4.5: Voltage divider [34]
TABLE 4.9: Search space and optimized parameters by different EAs for voltage divider
Sr.
No.
Design
Parameters
Search Space of
Design
Parameters
Optimized values of Design Parameters
PSO DE CS CSPSO
1 𝑊1 (µm) 0.1 µm to 1000 µm 0.17 37.59 0.28 0.18
2 𝑊2 (µm) 0.1 µm to 1000 µm 992.54 1000 998.74 1000
3 𝑊3 (µm) 0.1 µm to 1000 µm 11.70 1000 88.52 9.99
4 𝑊4 (µm) 0.1 µm to 1000 µm 222.60 1000 299.01 231.41
In Table 4.10, desired specifications and obtained specifications through simulation for the
above-optimized design parameters achieved by employing the different EAs for this
circuit are listed. The number of desired specifications for this circuit are three i.e. 𝑉𝑏𝑖𝑎𝑠1,
𝑉𝑏𝑖𝑎𝑠2, and 𝑉𝑏𝑖𝑎𝑠3.
TABLE 4.10: Desired specifications and simulation results by different EAs for voltage divider
Sr. No. Desired
Specifications
Obtained Specifications
PSO DE CS CSPSO
1 𝑉𝑏𝑖𝑎𝑠1= 0.8 V 0.795107 V 0.579185 V 0.788360 V 0.795121V
2 𝑉𝑏𝑖𝑎𝑠2 = 1.2 V 1.211513 V 1.102964 V 1.235081 V 1.209722 V
3 𝑉𝑏𝑖𝑎𝑠3 = 1.7 V 1.712546 V 1.600125 V 1.685456 V 1.716108 V
Simple CMOS based Analog Circuit Optimization
49
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit for 10 independent runs are listed in Table 4.11. The CSPSO algorithm
gives the least standard deviation for the fitness function value (𝑆𝐷𝑓) i.e. 5.4e-3 compared
to all other algorithms, while the PSO algorithm takes the least simulation time (𝑇𝑠𝑖𝑚) i.e.
434 seconds and the average number of function evaluations (𝐹𝐸𝑎𝑣𝑔) i.e. 3000 compared
to all other algorithms for the optimization of this circuit.
TABLE 4.11: Performance of different EAs for the optimization of voltage divider
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 7.0e-2 2.9e-1 2.2e-1 7.7e-2 100 3030 0 462
PSO 1.3e-2 4.7e-2 2.9e-2 1.1e-2 100 3000 0 434
CS 3.3e-2 5.5e-2 4.2e-2 6.0e-3 100 6030 0 902
CSPSO 1.4e-2 3.0e-2 2.2e-2 5.4e-3 100 9030 0 1216
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the voltage
divider is shown in Fig. 4.6 which illustrates that CSPSO algorithm gives a better solution
with higher convergence speed compared to the PSO and DE algorithms. It also shows
that the PSO algorithm gives a better solution with higher convergence speed compared to
the CS algorithm.
FIGURE 4.6: Convergence graph of different EAs for voltage divider
Analog Circuit Optimization
50
4.3.4 Current-Starved VCO
The circuit diagram for the three-stage current-starved VCO consisting of fourteen MOS
transistors M1 to M14 is shown in Fig. 4.7. Its working is similar to the ring oscillator. In
this circuit, M2 and M9 work as current sources which limit the current available to the
inverter formed by M5 and M12. It means the inverter is starved for current. This circuit is
used in CMOS Digital Phase Locked Loop (DPLL), function generators, frequency
synthesizer, etc. For this circuit optimization, the length of each transistor is considered
identical i.e. 𝐿 = 0.18 µm. The width of M1 to M7 NMOS transistors is considered as
𝑊1, 𝑊2, 𝑊3, 𝑊4, 𝑊5, 𝑊6, 𝑊7 and width of M8 to M14 PMOS transistors is considered
as 𝐾 ∗𝑊1, 𝐾 ∗𝑊2, 𝐾 ∗𝑊3, 𝐾 ∗𝑊4, 𝐾 ∗𝑊5, 𝐾 ∗𝑊6, 𝐾 ∗𝑊7. Here, 𝐾 is the multiplying
factor for the width of PMOS transistors. Thus, this circuit has eight design parameters
namely 𝑊1, 𝑊2, 𝑊3, 𝑊4, 𝑊5, 𝑊6, 𝑊7 , and 𝐾 . The search space and optimized values
achieved by different EAs for the design parameters of this circuit are listed in Table 4.12.
FIGURE 4.7: Three-stage current-starved VCO [107]
Simple CMOS based Analog Circuit Optimization
51
TABLE 4.12: Search space and optimized parameters by different EAs for VCO
Sr.
No.
Design
Parameters
Search Space of
Design
Parameter
Optimized Values of Design Parameters
PSO DE CS CSPSO
1 𝑊1 (µm) 1 µm to 1000 µm 708.60 715.19 946.11 113.16
2 𝑊2 (µm) 1 µm to 1000 µm 665.74 975.66 544.97 733.87
3 𝑊3 (µm) 1 µm to 1000 µm 235.39 1000.00 777.51 899.58
4 𝑊4 (µm) 1 µm to 1000 µm 572.96 1000.00 587.11 823.29
5 𝑊5 (µm) 1 µm to 1000 µm 526.66 1000.00 691.77 674.29
6 𝑊6 (µm) 1 µm to 1000 µm 740.49 1000.00 958.19 787.80
7 𝑊7 (µm) 1 µm to 1000 µm 664.06 957.09 836.72 784.74
8 𝐾 1 to 5 4.50 3.38 3.74 4.49
In Table 4.13, desired specifications and obtained specifications through simulation for the
above-optimized design parameters achieved by employing the different EAs for this
circuit are listed. The desired specification, in this case, is only one i.e. oscillation
frequency (𝑓𝑜).
TABLE 4.13: Desired specifications and simulation results by different EAs for VCO
Sr.
No.
Desired
Specifications
Obtained
Specifications
(PSO)
Obtained
Specifications
(DE)
Obtained
Specifications
(CS)
Obtained
Specifications
(CSPSO)
1 𝑓𝑜 = 400 MHz 400.0035 MHz 400.0237 MHz 400.0003 MHz 400.0002 MHz
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit for 10 independent runs are listed in Table 4.14. The CSPSO algorithm takes
less average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) i.e. 84.8, gives the least standard deviation for
the fitness function value (𝑆𝐷𝑓) i.e. 2.0e-6 and higher success rate (𝑆𝑟𝑎𝑡𝑒) i.e. 4 compared
to all other algorithms, whereas the PSO algorithm takes the least simulation time (𝑇𝑠𝑖𝑚)
i.e. 1789 seconds and average number of function evaluations (𝐹𝐸𝑎𝑣𝑔) i.e. 2985 compared
to all other algorithms for the optimization of this circuit.
TABLE 4.14: Performance of different EAs for the optimization of VCO
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 8.5e-5 2.3e-4 1.0e-4 7.0e-5 100 3030 0 2103
PSO 5.0e-7 4.6e-5 1.2e-5 1.3e-5 99.5 2985 1 1789
CS 7.5e-7 6.8e-5 2.8e-6 2.0e-6 95.6 5766 2 4349
CSPSO 5.0e-7 8.8e-6 2.2e-6 2.0e-6 84.8 7662 4 7470
Analog Circuit Optimization
52
FIGURE 4.8: Convergence graph of different EAs for VCO
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the VCO is shown
in Fig. 4.8 which shows that the CSPSO and CS algorithms give a better solution with
higher convergence speed compared to the DE and PSO algorithms.
4.3.5 Cascode Amplifier
FIGURE 4.9: Cascode amplifier [108]
Simple CMOS based Analog Circuit Optimization
53
The circuit diagram for a cascode amplifier consisting of five MOS transistors M1, M2,
M3, M4, and M5 is shown in Fig. 4.9 [108]. It gives higher output impedance and reduces
the effect of Miller capacitance on the input of the amplifier, which will be very important
in designing the frequency behaviour of the op-amp. It can provide high voltage gain in a
single stage. The length (𝐿) for all transistors is considered identical as 𝐿 = 0.18 µm and
the width of M1, M2, M3, M4, and M5 transistors is considered as 𝑊1, 𝑊2, 𝑊3 = 𝑊4, 𝑊5
respectively for this circuit optimization. So, this circuit has four design parameters
namely 𝑊1, 𝑊2, 𝑊3, and 𝑊5. The circuit is optimized to drive the load capacitor of 10 pF.
The value of the current source 𝐼𝑏𝑖𝑎𝑠 is set to 150 µA. The search space and optimized
values achieved by different EAs for the design parameters of this circuit are listed in
Table 4.15.
TABLE 4.15: Search space and optimized parameters by different EAs for cascode amplifier
Sr.
No.
Design
Parameters
Search Space of
Design
Parameters
Optimized Values of Design Parameters
PSO DE CS CSPSO
1 𝑊1 (µm) 0.2 µm to 10 µm 7.65 8.72 7.60 9.99
2 𝑊2 (µm) 0.2 µm to 10 µm 5.65 10.00 10.00 8.81
3 𝑊3 (µm) 0.2 µm to 10 µm 1.64 1.84 1.09 0.75
4 𝑊5 (µm) 0.2 µm to 10 µm 0.82 1.18 0.93 0.93
Table 4.16 lists the desired specifications and obtained specifications through simulation
for the above-optimized design parameters achieved by employing the different EAs for
this circuit. The number of desired specifications for this circuit are five i.e. 𝐴𝑣, UGB, PM,
RSR, and FSR.
TABLE 4.16: Desired specifications and simulation results by different EAs for cascode amplifier
Sr.
No. Specifications
Desired
value
Obtained Specifications
PSO DE CS CSPSO
1 𝐴𝑣 (dB) > 35 35.56 36.48 36.78 37.21
2 UGB (MHz) > 10 26.21 27.44 26.30 29.22
3 PM (°) > 45 90.83 90.71 90.69 90.62
4 RSR (V/µs) > 10 16.75 16.92 15.99 14.99
5 FSR (V/µs) > 10 60.83 69.81 83.74 83.05
The performance of the different EAs for the optimization of the cascode amplifier for 10
independent runs are listed in Table 4.17. The DE, CS, and hybrid CSPSO algorithms
obtained all the targeted specifications for all 10 runs but the PSO algorithm achieved all
Analog Circuit Optimization
54
the targeted specifications for a single time only out of 10 runs. The average number of
iterations required (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) i.e. 4.6 for 10 independent runs is less for the CSPSO
algorithm compared to those required for the CS, DE, and PSO algorithms. The DE
algorithm takes the least simulation time (𝑇𝑠𝑖𝑚) i.e. 1094 seconds and the least average
number of function evaluations (𝐹𝐸𝑎𝑣𝑔) i.e. 243 compared to all other algorithms for the
optimization process of this circuit.
TABLE 4.17: Performance of different EAs for the optimization of cascode amplifier
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 0.0 0.0 0.0 0.0 7.10 243 10 1094
PSO 0.0 2.0e-1 9.4e-2 5.6e-2 90.10 2703 1 10696
CS 0.0 0.0 0.0 0.0 8.10 516 10 2432
CSPSO 0.0 0.0 0.0 0.0 4.6 444 10 1956
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the cascode
amplifier is shown in Fig. 4.10 which illustrates that the CSPSO and CS algorithms give a
better solution with higher convergence speed compared to the PSO and DE algorithms.
From the optimization results of all the circuits presented in this section, we can conclude
that the CSPSO and CS algorithms outperform the DE and PSO algorithms in terms of
solution accuracy and convergence speed.
FIGURE 4.10: Convergence graph of different EAs for cascode amplifier
Moderately Complex CMOS based Analog Circuit Optimization
55
4.4 Moderately Complex CMOS based Analog Circuit Optimization
Differential Amplifier (DA), op-amp, and OTA are the circuits commonly used in many
interface circuits like Analog to Digital Converters (ADC), Digital to Analog Converters
(DAC), mixers, filters, modulators, regulators, comparators, etc. Op-amp is used for low-
frequency applications whereas, OTA is used at high frequency for various analog circuits
and systems. So, the optimum design of all these fundamental CMOS based analog
circuits is the basis of a design background for various applications. The performance of
the CS, hybrid CSPSO, PSO, and DE algorithms are also evaluated by optimizing some
higher-level CMOS based analog circuits such as DA with current mirror load, two-stage
op-amp, FOTA, and Miller OTA. All these circuits require more design parameters and
we have also considered more desired specifications for all these circuits. So, the
complexity of the optimization problem for all these circuits is more due to the greater
number of design parameters and desired specifications. All these circuits are simulated
using BSIM3v3 MOSFET models in 0.18 µm and 0.35 µm CMOS technologies at room
temperature 27º C. The results are also compared with the results presented in the selected
literature to check the efficiency and reliability of our automated design methodology.
4.4.1 Differential Amplifier using a Current Mirror Load
The circuit diagram for DA using a current mirror load consisting of six MOS transistors
M1, M2, M3, M4, M5, M6, and current source 𝐼𝑏𝑖𝑎𝑠 is shown in Fig. 4.11. More details
about the theoretical and mathematical analysis of this circuit can be found in [108]. This
circuit is optimized to drive the load capacitor of 0.5 pF. The supply voltage is set to ±1.8
V and ±3.3 V for 0.18 µm and 0.35 µm CMOS technologies respectively. The length of
transistor Mi is considered as 𝐿𝑖 and width of transistor Mi is considered as 𝑊𝑖, where 𝑖 =
1, 2, . . . . . , 6. Here, 𝐿1, 𝐿2, 𝐿3, and 𝐿4 are set equal to 3.5 µm, 𝐿5 and 𝐿6 are set equal to
1.4 µm, 𝑊1 and 𝑊2 are considered identical, 𝑊3 and 𝑊4 are considered identical, and 𝑊5
and 𝑊6 are also considered identical for this circuit optimization. So, this circuit has four
design parameters namely 𝑊1 = 𝑊2, 𝑊3 = 𝑊4, 𝑊5 = 𝑊6, and 𝐼𝑏𝑖𝑎𝑠 . The search space
and optimized values achieved by different EAs for the design parameters of this circuit
with 0.35 µm CMOS technology are listed in Table 4.18.
Analog Circuit Optimization
56
FIGURE 4.11: DA using a current mirror load [108]
TABLE 4.18: Search space and optimized parameters by different EAs for DA in 0.35 µm CMOS
technology
Sr.
No.
Design
Parameters
Search Space of
Design
Parameters
Optimized Values of Design Parameters
PSO DE CS CSPSO [63] [62]
1 𝑊1 = 𝑊2 (µm) 3.5 µm to 30 µm 27.85 30.00 28.46 30.00 38.5 29.4
2 𝑊3 = 𝑊4 (µm) 3.5 µm to 30 µm 3.79 4.11 3.53 3.50 12.3 11.3
3 𝑊5 = 𝑊6 (µm) 3.5 µm to 30 µm 14.99 21.11 13.90 5.24 3.9 4.2
4 𝐼𝑏𝑖𝑎𝑠 (µA) 3.5 µA to 30 µA 13.73 15.34 10.00 10.00 125 125
Table 4.19 reveals the desired specifications and obtained specifications through
simulation for the above-optimized design parameters achieved by employing the different
EAs for this circuit. The number of desired specifications for this circuit are twelve i.e. 𝐴𝑣,
UGB, PM, +ve PSSR, -ve PSSR, RSR, FSR, CMRR, 𝑃𝑑𝑖𝑠𝑠, input-referred noise spectral
density (𝑁𝑖𝑛) @ 10 kHz, total integrated input-referred noise (𝑁𝑖𝑛𝑡) over the specified
frequency range from 1 Hz to 100 kHz, and Total MOS Transistor Area (TTA). The
complexity of the optimization problem for this circuit is more compared to the
optimization problem of the circuits presented in the previous section due to a great
number of desired specifications and design parameters are considered for this circuit.
Moderately Complex CMOS based Analog Circuit Optimization
57
TABLE 4.19: Desired specifications and simulation results by different EAs for DA in 0.35 µm CMOS
technology
Sr.
No. Specifications
Desired
value
Obtained Specifications
PSO DE CS CSPSO [63] [62]
1 𝐴𝑣 (dB) > 47 47.01 47.00 47.01 47.01 44.49 42
2 UGB (MHz) > 10 30.06 33.91 24.88 24.52 12.44 12.3
3 PM (°) > 45 57.63 55.64 58.63 58.10 81.71 83.8
4 +ve PSSR (dB) > 40 47.62 47.66 47.51 47.52 46.43 40.1
5 -ve PSSR (dB) > 70 82.90 82.71 81.41 83.85 91.29 68
6 RSR (V/µs) > 10 29.47 34.71 22.86 21.56 14.19 22.4
7 FSR (V/µs) > 10 23.76 26.83 18.44 17.78 --- ---
8 CMRR (dB) > 70 74.23 73.35 77.84 76.69 84.44 84.2
9 𝑃𝑑𝑖𝑠𝑠 (µW) < 1000 105.95 124.40 81.78 77.65 580.6 1260
10 𝑁𝑖𝑛 (nV/√𝐻𝑧)
@ 10 kHz < 50 18.16 16.93 20.19 20.35 --- ---
11 𝑁𝑖𝑛𝑡 (µVrms)
(1 Hz – 100 kHz) < 50 5.82 5.41 6.50 6.56 --- ---
12 TTA (µm2 ) < 400 263.45 297.86 262.84 249.16 369.18 296
The CSPSO algorithm achieved all the targeted specifications with the least power
dissipation (𝑃𝑑𝑖𝑠𝑠) i.e. 77.65 µW and the least TTA i.e. 249.16 µm2 for this design.
Vural et al. [62] have reported the optimization of the similar circuit using the PSO
algorithm and Mallick et al. [63] have applied the Craziness-based PSO (CRPSO)
algorithm for the optimum design of the same circuit with similar CMOS technology.
Results reported in the literature are presented in Table 4.19 for the performance
comparison. From the results, it can be observed that although we have considered some
additional specifications compared to those reported in the literature, our methodology can
satisfy the objective function of this design problem.
TABLE 4.20: Performance of different EAs for the optimization of DA in 0.35 µm CMOS technology
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 0.0 3.4e-3 1.0e-3 1.1e-3 67.5 2055 5 3718
PSO 0.0 1.5e-2 8.0e-3 5.4e-3 80.2 2406 2 4930
CS 0.0 0.0 0.0 0.0 5.4 354 10 630
CSPSO 0.0 0.0 0.0 0.0 2.0 210 10 371
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit with 0.35 µm CMOS technology for 10 independent runs are listed in Table
4.20. The CS and hybrid CSPSO algorithms succeeded 10 times out of 10 runs to achieve
Analog Circuit Optimization
58
all the targeted specifications, whereas the DE algorithm succeeded for 5 times and the
PSO algorithm succeeded for only 2 times out of 10 runs to achieve all the targeted
specifications for this circuit. The average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) taken by 10
independent runs of the optimization process of this circuit is less for the CS and CSPSO
algorithms compared to taken for the DE and PSO algorithms. The CS and CSPSO
algorithms also achieved zero standard deviation for the fitness function value (𝑆𝐷𝑓).
Thus, the CS and CSPSO algorithms outperform the DE and PSO algorithms for this case.
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the optimization
of this circuit with 0.35 µm CMOS technology is shown in Fig. 4.12 which shows that the
CS and CSPSO algorithms give a better solution with higher convergence speed compared
to the PSO and DE algorithms.
FIGURE 4.12: Convergence graph of different EAs for DA optimization in 0.35 µm CMOS technology
This circuit is also optimized in 0.18 µm CMOS technology by the CS, hybrid CSPSO,
PSO, and DE algorithms. The search space and optimized values achieved by different
EAs for the design parameters of this circuit with 0.18 µm CMOS technology are listed in
Table 4.21.
Moderately Complex CMOS based Analog Circuit Optimization
59
TABLE 4.21: Search space and optimized parameters by different EAs for DA in 0.18 µm CMOS
technology
Sr.
No.
Design
Parameters
Search Space of
Design
Parameters
Optimized Values of Design Parameters
PSO DE CS CSPSO [109]
1 𝑊1 = 𝑊2 (µm) 3.5 µm to 30 µm 27.34 30.00 30.00 25.84 6.38
2 𝑊3 = 𝑊4 (µm) 3.5 µm to 30 µm 9.24 11.65 5.10 3.50 6.24
3 𝑊5 = 𝑊6 (µm) 3.5 µm to 30 µm 29.07 30.00 8.70 6.30 2.8
4 𝐼𝑏𝑖𝑎𝑠 (µA) 3.5 µA to 30 µA 10.00 6.11 5.47 6.78 ---
Desired specifications and obtained specifications through simulation for the above-
optimized design parameters achieved by employing the different EAs for this circuit with
0.18 µm CMOS technology are recorded in Table 4.22.
TABLE 4.22: Desired specifications and simulation results by different EAs for DA in 0.18 µm CMOS
technology
Sr.
No. Specifications
Desired
value
Obtained Specifications
PSO DE CS CSPSO [109]
1 𝐴𝑣 (dB) > 40 40.23 40.07 40.37 40.53 42.15
2 UGB (MHz) > 10 24.58 17.27 16.99 19.82 2.48
3 PM (°) > 45 47.03 47.54 49.53 50.97 60.38
4 +ve PSSR (dB) > 40 40.98 40.77 41.08 41.25 --
5 -ve PSSR (dB) > 70 69.97 70.25 70.44 70.33 --
6 RSR (V/µs) > 10 26.31 14.36 13.94 16.25 12.32
7 FSR (V/µs) > 10 18.25 11.55 10.67 12.95 --
8 CMRR (dB) > 70 69.32 70.03 70.08 70.04 --
9 𝑃𝑑𝑖𝑠𝑠 (µW) < 1000 53.74 34.52 28.06 32.87 --
10 𝑁𝑖𝑛 (nV/√𝐻𝑧)
@ 10 kHz < 50 17.92 22.12 22.62 20.65 21.26
11 𝑁𝑖𝑛𝑡 (µVrms)
(1 Hz – 100 kHz) < 50 5.68 7.04 7.20 6.57 --
12 TTA (µm2 ) < 400 337.40 375.60 270.09 223.02 87.35
The CS and CSPSO algorithms optimized this circuit for the targeted specifications in
0.18 µm CMOS technology with Total MOS Transistor Area (TTA) of 270.09 µm2 and
223.02 µm2 respectively. The TTA and power dissipation (𝑃𝑑𝑖𝑠𝑠) obtained by the CS and
CSPSO algorithms are less compared to those achieved by the DE and PSO algorithms.
The CSPSO algorithm achieved all the targeted specifications with low 𝑃𝑑𝑖𝑠𝑠 i.e. 32.87 µW
and the least TTA i.e. 223.02 µm2 compared to those achieved through the DE and PSO
algorithms.
Analog Circuit Optimization
60
Singh et al. [109] have reported the optimization of a similar circuit using the PSO with an
aging leader and challengers (ALCPSO) algorithm implemented on the same CMOS
technology. Results reported in the literature are presented in Table 4.22 for the
performance comparison. From the results, it is revealed that although we have considered
some additional specifications compared to those reported in the literature, our
methodology can satisfy the objective function of this design problem.
TABLE 4.23: Performance of different EAs for the optimization of DA using 0.18 µm CMOS
technology
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 0.0 0.0 0.0 0.0 15.6 458 10 1118
PSO 4.4e-3 1.9e-2 1.1e-2 5.1e-3 100 3000 0 7429
CS 0.0 0.0 0.0 0.0 12.7 792 10 1457
CSPSO 0.0 0.0 0.0 0.0 20.2 1848 10 4047
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit in 0.18 µm CMOS technology for 10 independent runs are listed in Table
4.23. The CS, hybrid CSPSO, and DE algorithms succeeded 10 times out of 10 runs to
achieve all the targeted specifications during the optimization process of this circuit,
whereas the PSO algorithm could not achieve success for a single time to obtain all the
targeted specifications. The average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) required for 10
independent runs of the optimization process of this circuit is the least for the CS
algorithm compared to those required for the CSPSO, DE, and PSO algorithms. The CS,
CSPSO, and DE algorithms also achieved zero standard deviation for the fitness function
value (𝑆𝐷𝑓), whereas the PSO algorithm achieved 5.1e-3. Thus, the CS, DE, and CSPSO
algorithms outperform the PSO algorithm for this case.
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the optimization
of DA in 0.18 µm CMOS technology is shown in Fig. 4.13. It shows that the CS algorithm
is faster to reach the targeted fitness value compared to the DE, CSPSO, and PSO
algorithms.
Moderately Complex CMOS based Analog Circuit Optimization
61
FIGURE 4.13: Convergence graph of different EAs for DA optimization in 0.18 µm CMOS technology
4.4.2 Two-Stage Operational Amplifier
Operational amplifiers (op-amps) are the significant components in an analog processing
system such as amplifiers, oscillators, summers, differentiators, integrators, and filters for
low-frequency applications. An op-amp circuit can be considered as the main bottleneck
in the most of analog circuits. A two-stage op-amp is a commonly used configuration
among different configurations of CMOS op-amp. The circuit diagram of two-stage
CMOS op-amp is shown in Fig. 4.14 [107][108]. The main parts of this circuit are a
differential gain stage, second gain stage, and a bias circuit. The differential gain stage is
built of the transistors M1 to M4. The input stage of the amplifier is formed by transistors
M1 and M2. The gate of transistor M1 is an inverting input, and the gate of transistor M2
is the noninverting input. The transistors M3 and M4 act as the active load for the
differential amplifier circuit. The second gain stage, formed by the transistor M6, provides
an extra gain in the amplifier. This transistor is connected in common source topology.
The transistors M6 and M7 get the output through the drain of M2 and amplify it through
the transistor M6. The transistor M7 works as the load resistance for M6. The circuit
Analog Circuit Optimization
62
biasing is given by three transistors with the help of the current source. A voltage between
the gate and source of transistors M5 and M7 is given by transistor M8 and the current
source supply. More about the theoretical background and manual design procedure for
this circuit can be found in [108][110].
FIGURE 4.14: Two-stage op-amp [107][108]
This circuit is optimized to drive the load capacitor of 0.5 pF. The supply voltage is set to
±1.8 V and ±3.3 V for 0.18 µm and 0.35 µm CMOS technologies respectively. The length
of transistor Mi is considered as 𝐿𝑖 and width of transistor Mi is considered as 𝑊𝑖, where
𝑖 = 1, 2, . . . . , 8. The width of different transistors is considered as 𝑊1 = 𝑊2, 𝑊3 = 𝑊4,
𝑊5 = 𝑊8, 𝑊6, and 𝑊7 for this circuit sizing. The length of different transistors is
considered as 𝐿1 = 𝐿2 = 𝐿5 = 𝐿7 = 𝐿8 = 1.75 µ𝑚, and 𝐿3 = 𝐿4 = 𝐿6 = 1.00 µm for the
optimization process of this circuit using 0.35 µm CMOS technology. So, this circuit has
six design parameters namely 𝑊1 = 𝑊2 , 𝑊3 = 𝑊4, 𝑊5 = 𝑊8, 𝑊6,𝑊7, and 𝐼𝑏𝑖𝑎𝑠 as
observed from Fig. 4.14. The search space and optimized values achieved by different
EAs for the design parameters of this circuit with 0.35 µm CMOS technology are listed in
Table 4.24.
Moderately Complex CMOS based Analog Circuit Optimization
63
TABLE 4.24: Search space and optimized parameters by different EAs for two-stage op-amp in 0.35
µm CMOS technology
Sr.
No.
Design
Parameters
Search Space
of Design
Parameters
Optimized Values of Design Parameters
PSO DE CS CSPSO [63] [111]
1 𝑊1 = 𝑊2 (µm) 1 µm to 10 µm 8.26 9.61 6.41 9.96 4.9 4
2 𝑊3 = 𝑊4 (µm) 1 µm to 10 µm 3.29 2.57 2.06 2.55 5.9 4
3 𝑊5 = 𝑊8 (µm) 1 µm to 10 µm 4.18 3.20 1.74 2.80 2.1 2.8
4 𝑊6 (µm) 1 µm to 10 µm 10.00 10.00 7.71 9.99 89.3 27.8
5 𝑊7 (µm) 1 µm to 10 µm 10.00 8.70 4.86 7.91 15.89 11.5
6 𝐼𝑏𝑖𝑎𝑠 (µA) 1 µA to 10 µA 8.70 10.00 9.78 9.87 38.97 25
Desired specifications and obtained specifications through simulation for the above-
optimized design parameters achieved by employing the different EAs for this circuit are
tabulated in Table 4.25. The number of desired specifications for this circuit are twelve i.e.
𝐴𝑣, UGB, PM, +ve PSSR, -ve PSSR, RSR, FSR, CMRR, 𝑃𝑑𝑖𝑠𝑠, 𝑁𝑖𝑛 @ 1 kHz, 𝑁𝑖𝑛𝑡 over
the specified frequency range from 1 Hz to 100 kHz, and Total MOS Transistor Area
(TTA). The optimization problem of this circuit is more complex compared to the
optimization problem of the DA circuit because of the larger number of design parameters
for this circuit. The CS algorithm optimized this circuit with the least TTA of 48.86 µm2
compared to that achieved by the DE, CSPSO, and PSO algorithms.
TABLE 4.25: Desired specifications and simulation results by different EAs for two-stage op-amp in
0.35 µm CMOS technology
Sr.
No. Specifications
Desired
value
Obtained Specifications
PSO DE CS CSPSO [63] [111]
1 𝐴𝑣 (dB) > 72 74.40 72.46 74.13 75.04 68.09 78
2 UGB (MHz) > 10 12.08 13.77 12.05 13.79 5.52 5.36
3 PM (°) > 45 45.29 45.17 46.20 45.10 66.4 68.3
4 +ve PSSR (dB) > 80 100.26 80.09 92.06 82.95 83.43 84.69
5 -ve PSSR (dB) > 80 79.23 79.89 80.17 80.15 97.06 106
6 RSR (V/µs) > 10 12.33 13.57 10.17 11.20 13.44 8
7 FSR (V/µs) > 10 9.49 10.59 12.47 10.48 --- ---
8 CMRR (dB) > 70 75.40 82.97 74.33 80.48 86.32 88.26
9 𝑃𝑑𝑖𝑠𝑠 (µW) < 1000 507.32 608.12 579.42 614.76 917.7 616.3
10 𝑁𝑖𝑛 (nV/√𝐻𝑧)
@ 10 kHz < 50 25.58 23.14 24.72 23.15 --- ---
11 𝑁𝑖𝑛𝑡 (µVrms)
(1 Hz – 100 kHz) < 50 28.72 25.98 27.75 25.99 --- ---
12 TTA (µm2 ) < 300 77.62 75.2 48.86 73.59 262.04 121.8
Analog Circuit Optimization
64
Mallick et al. [63] have reported the optimization of the similar circuit using the CRPSO
algorithm and Mallick et al. [111] have applied the opposition concept based HS algorithm
for the optimum design of the same circuit using similar CMOS technology. Results
reported in the literature are presented in Table 4.25 for the performance comparison.
From which, it is revealed that although we have considered some additional
specifications compared to those reported in the literature, our methodology is able to
satisfy the objective function of this design problem.
TABLE 4.26: Performance of different EAs for the optimization of two-stage op-amp in 0.35 µm
CMOS technology
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 3.2e-4 1.4e-2 5.9e-3 4.3e-3 100 3030 0 4038
PSO 2.3e-2 2.4e-1 1.4e-1 7.9e-2 100 3000 0 4013
CS 0.0 0.0 0.0 0.0 51.60 3126 10 3804
CSPSO 0.0 0.0 0.0 0.0 38.4 3486 10 4900
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit in 0.35 µm CMOS technology for 10 independent runs are tabulated in
Table 4.26. The CS and hybrid CSPSO algorithms succeeded 10 times out of 10 runs to
achieve all the targeted specifications during the optimization process of this circuit,
whereas the DE and PSO algorithms could not achieve success for a single time to obtain
all the targeted specifications. The average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) consumed by 10
independent runs of the optimization process of this circuit are 38.4 and 51.60 for the
CSPSO and CS algorithms respectively. 𝐼𝑡𝑒𝑟𝑎𝑣𝑔 required for the CS and CSPSO
algorithms are less compared to those required for the DE and PSO algorithms. The
average value (𝑀𝑒𝑎𝑛𝑓) for the fitness function obtained by the CS and CSPSO algorithms
is zero, whereas the average value for the fitness function obtained (𝑀𝑒𝑎𝑛𝑓) by the DE
and PSO algorithms is 5.9e-3 and 1.4e-1 respectively. Thus, the CS and CSPSO
algorithms outperform both the DE and PSO algorithms for this case in every aspect.
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the optimization
of two-stage op-amp in 0.35 µm CMOS technology is shown in Fig. 4.15. It shows that
the CSPSO algorithm is faster in obtaining the targeted fitness function value compared to
the DE, CS, and PSO algorithms. It also shows that the PSO and DE algorithms are unable
to reach the targeted fitness function value within the maximum number of iterations.
Moderately Complex CMOS based Analog Circuit Optimization
65
FIGURE 4.15: Convergence graph of different EAs for two-stage op-amp optimization in 0.35 µm
CMOS technology
This circuit is also optimized with 0.18 µm CMOS technology by the CS, hybrid CSPSO,
PSO, and DE algorithms. The length of different transistors for this circuit is set as 𝐿1 =
𝐿2 = 𝐿5 = 𝐿7 = 𝐿8 = 0.75 µ𝑚, and 𝐿3 = 𝐿4 = 𝐿6 = 0.50 µm for the optimization
process of this circuit using 0.18 µm CMOS technology. The search space and optimized
values achieved by different EAs for the design parameters of this circuit using 0.18 µm
CMOS technology are listed in Table 4.27.
TABLE 4.27: Search space and optimized parameters by different EAs for two-stage op-amp in 0.18
µm CMOS technology
Sr.
No.
Design
Parameters
Search Space
of Design
Parameters
Optimized values of Design Parameters
PSO DE CS CSPSO [112] [113]
1 𝑊1 = 𝑊2 (µm) 1 µm to 10 µm 9.11 10.00 1.00 1.97 4 2.06
2 𝑊3 = 𝑊4 (µm) 1 µm to 10 µm 7.27 5.46 3.73 2.64 4 2.06
3 𝑊5 = 𝑊8 (µm) 1 µm to 10 µm 8.59 9.39 1.00 1.22 2 2.06
4 𝑊6 (µm) 1 µm to 10 µm 10.00 10.00 10.00 10.00 21.54 6.15
5 𝑊7 (µm) 1 µm to 10 µm 8.03 8.77 1.41 2.54 5.38 3
6 𝐼𝑏𝑖𝑎𝑠 (µA) 1 µA to 10 µA 10.00 10.00 9.83 10.00 49 20
Analog Circuit Optimization
66
TABLE 4.28: Desired specifications and simulation results by different EAs for two-stage op-amp in
0.18 µm CMOS technology
Sr.
No. Specifications
Desired
value
Obtained Specifications
PSO DE CS CSPSO [112] [113]
1 𝐴𝑣 (dB) > 72 69.78 70.28 72.05 72.08 61 75.3
2 UGB (MHz) > 10 26.56 26.02 10.35 14.04 3 3.52
3 PM (°) > 45 80.25 59.92 58.19 55.51 - 60.50
4 +ve PSSR (dB) > 80 81.93 82.76 81.00 81.85 - 84.50
5 -ve PSSR (dB) > 80 94.32 118.18 104.69 116.04 - 77.45
6 RSR (V/µs) > 10 16.86 16.91 12.93 13.14 20 18.20
7 FSR (V/µs) > 10 10.17 10.14 11.44 12.47 - -
8 CMRR (dB) > 70 73.89 72.81 76.73 76.17 - 83.01
9 𝑃𝑑𝑖𝑠𝑠 (µW) < 1000 70.38 70.90 69.10 87.18 1137.3 90
10 𝑁𝑖𝑛 (nV/√𝐻𝑧)
@ 10 kHz < 50 19.20 18.61 31.20 24.30 - -
11 𝑁𝑖𝑛𝑡 (µVrms)
(1 Hz – 100 kHz) < 50 21.53 20.85 35.01 27.26 - -
12 TTA (µm2 ) < 300 44.83 46.13 12.79 14.31 93.86 21.51
Table 4.28 lists the desired specifications and obtained specifications through simulation
for the optimized design parameters achieved by employing the different EAs for this
circuit. The CS algorithm optimized this circuit with the least Total MOS Transistor Area
(TTA) of 12.79 µm2 and the least power dissipation (𝑃𝑑𝑖𝑠𝑠) of 69.10 µW compared to
those achieved by other algorithms while satisfying other specifications.
Sarkar et al. [112] have reported the optimization of the same circuit using the Whale
Optimization Algorithm (WOA) and Majeed et al. [113] have applied the hybrid WOA
and Modified Gray Wolf Optimization (MGWO) algorithm for the optimum design of the
same circuit using similar CMOS technology. Results reported in the literature are also
presented in Table 4.28 for the performance comparison. From which, it can be observed
that although we have considered some additional specifications compared to those
reported in the literature, our methodology is able to satisfy the objective function of this
design problem.
The performance of the CS, CSPSO, PSO, and DE algorithms for the optimization of this
circuit with 0.18 µm CMOS technology for 10 independent runs are listed in Table 4.29.
The CS algorithm succeeded 6 times and hybrid CSPSO succeeded 3 times out of 10 runs
to achieve all the targeted specifications for the optimization of this circuit, whereas the
DE and PSO algorithms could not obtain success for a single time to achieve all the
Moderately Complex CMOS based Analog Circuit Optimization
67
targeted specifications. The average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) required by 10
independent runs of the optimization process of this circuit is less for the CS and CSPSO
algorithms compared to those required for the DE and PSO algorithms. The PSO
algorithm consumed the least simulation time (𝑇𝑠𝑖𝑚) of 4412 seconds for 10 runs of this
optimization process. The CSPSO algorithm required more average function evaluations
(𝐹𝐸𝑎𝑣𝑔) i.e. 11633 compared to all other algorithms. Thus, the CS and CSPSO algorithms
outperform both the DE and PSO algorithms for this case also.
TABLE 4.29: Performance of different EAs for the optimization of two-stage op-amp using 0.18 µm
CMOS technology
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 1.4e-2 2.4e-2 2.1e-2 3.7e-2 100 3030 0 4679
PSO 2.7e-2 5.4e-2 3.2e-2 8.1e-3 100 3000 0 4412
CS 0.0 1.9e-2 5.6e-3 7.3e-3 77.80 4698 6 6695
CSPSO 0.0 2.1e-2 9.4e-3 7.2e-3 88.30 7977 3 11633
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the optimization
of two-stage op-amp in 0.18 µm CMOS technology is shown in Fig. 4.16. It shows that
the CS and CSPSO algorithms give a better solution with higher convergence speed
compared to the PSO and DE algorithms.
FIGURE 4.16: Convergence graph of different EAs for two-stage op-amp optimization in 0.18 µm
CMOS technology
Analog Circuit Optimization
68
4.4.3 Folded Cascode OTA
There are different topologies of CMOS Folded cascode OTA (FOTA) available in the
literature, one of them is shown in Fig. 4.17. More details about the theoretical and
mathematical analysis of this circuit can be found in [114][115].
FIGURE 4.17: Folded cascode OTA [114]
The length of transistor Mi is considered as 𝐿𝑖 and width of transistor Mi is considered as
𝑊𝑖 , where 𝑖 = 1, 2, . . . . , 14 . The width of different transistors is considered as 𝑊1 =
𝑊2 = 𝑊12, 𝑊3 = 𝑊4, 𝑊5 = 𝑊6, 𝑊7 = 𝑊8, 𝑊9 = 𝑊10, 𝑊11, 𝑊13, and 𝑊14 for this circuit.
The length of each transistor is chosen identical i.e. 𝐿𝑖 = 1 µm. So, this circuit has nine
design parameters namely 𝑊1 = 𝑊2 = 𝑊12 , 𝑊3 = 𝑊4 , 𝑊5 = 𝑊6 , 𝑊7 = 𝑊8 , 𝑊9 = 𝑊10 ,
𝑊11, 𝑊13, 𝑊14, and 𝐼𝑏𝑖𝑎𝑠 as observed from Fig. 4.17. The circuit is optimized to drive the
load capacitor of 0.1 pF. The supply voltage is set to ±1.8 V and ±2 V for 0.18 µm and
0.35 µm CMOS technologies respectively. The search space and optimized values
achieved by different EAs for the design parameters of this circuit using 0.35 µm CMOS
technology are listed in Table 4.30.
Moderately Complex CMOS based Analog Circuit Optimization
69
TABLE 4.30: Search space and optimized parameters by different EAs for FOTA in 0.35 µm CMOS
technology
Sr.
No.
Design
Parameters
Search Space
of Design
Parameters
Optimized values of Design Parameters
PSO DE CS CSPSO [114] [114]
1 𝑊1,2,12 (µm) 1 µm to 200 µm 157.87 200 179.27 97.64 25.6 28.5
2 𝑊3,4 (µm) 1 µm to 200 µm 96.63 89.80 54.84 28.85 12.8 49.9
3 𝑊5,6 (µm) 1 µm to 200 µm 171.80 148.18 115.06 108.04 4.5 16.4
4 𝑊7,8 (µm) 1 µm to 200 µm 171.80 148.18 115.06 108.04 4.5 34.2
5 𝑊9,10 (µm) 1 µm to 200 µm 200 200 69.28 136.74 49.2 49.85
6 𝑊11 (µm) 1 µm to 200 µm 200 194.67 108.05 56.05 9 68.4
7 𝑊13 (µm) 1 µm to 200 µm 89.44 200 33.22 54.14 25.6 99.8
8 𝑊14 (µm) 1 µm to 200 µm 166.77 193.12 118.40 198.99 9 32.8
9 𝐼𝑏𝑖𝑎𝑠 (µA) 1 µA to 200 µA 111.79 154.35 109.13 80.18 27.5 30
Desired specifications and obtained specifications through simulation for the above-
optimized design parameters achieved by employing the different EAs for this circuit are
listed in Table 4.31. The number of desired specifications for this circuit are also twelve
i.e. 𝐴𝑣, UGB, PM, +ve PSSR, -ve PSSR, RSR, FSR, CMRR, 𝑃𝑑𝑖𝑠𝑠, 𝑁𝑖𝑛@ 1 Hz, 𝑁𝑖𝑛𝑡 over
the specified frequency range from 1 Hz to 100 MHz, and TTA. The optimization problem
of this circuit is more complex compared to the optimization problem of the DA and two-
stage op-amp circuits due to the larger number of design parameters for this circuit. The
CSPSO algorithm achieved all the targeted specifications with the least power dissipation
(𝑃𝑑𝑖𝑠𝑠) i.e. 510.61 µW and the least Total MOS Transistor Area (TTA) i.e. 1365.41 µm2
compared to those achieved by the CS, DE, and PSO algorithms.
TABLE 4.31: Desired specifications and simulation results by different EAs for FOTA in 0.35 µm
CMOS technology
Sr.
No. Specifications
Desired
value
Obtained Specifications
PSO DE CS CSPSO [114] [114]
1 𝐴𝑣 (dB) > 70 73.82 74.19 72.03 74.65 76 85.5
2 UGB (MHz) > 100 152.79 200.70 196.53 183.60 420 537
3 PM (°) > 45 85.60 80.09 63.06 83.49 -- --
4 +ve PSSR (dB) > 65 68.91 68.50 68.65 70.05 57.68 79
5 -ve PSSR (dB) > 75 84.67 85.07 82.17 83.01 57.68 79
6 RSR (V/µs) > 40 73.51 139.58 61.33 76.26 200 290
7 FSR (V/µs) > 40 49.72 72.77 67.02 53.14 200 290
8 CMRR (dB) > 80 126.94 113.39 107.87 110.66 59.23 61.75
9 𝑃𝑑𝑖𝑠𝑠 (µW) < 1000 721.90 985.34 720.41 510.61 660 696
10 𝑁𝑖𝑛 (µV/√𝐻𝑧)
@ 1 Hz < 20 10.39 8.61 10.73 11.03 116.49 0.63
11 𝑁𝑖𝑛𝑡 (µVrms)
(1 Hz – 100 MHz) < 200 80.77 73.72 89.95 93.99 -- --
12 TTA (µm2 ) < 3000 2210.12 2360.10 1505.95 1365.41 262.4 984.36
Analog Circuit Optimization
70
Daoud et al. [114] have reported the optimization of the same circuit through the heuristic
programming method as well as the 𝑔𝑚/𝐼𝐷 method using similar CMOS technology.
Results reported in the literature are presented in Table 4.31 for the performance
comparison. From which, it is revealed that although we have considered some additional
specifications compared to those reported in the literature, our methodology is able to
satisfy the objective function of this design problem.
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit with 0.35 µm CMOS technology for 10 independent runs are listed in Table
4.32. The CS and CSPSO algorithms succeeded 10 times out of 10 runs to achieve all the
targeted specifications during the optimization process of this circuit, whereas the DE
algorithm succeeded 9 times and PSO algorithm succeeded 2 times out of 10 runs to
achieve all the targeted specifications. The CSPSO algorithm takes the less average
number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) to obtain the final targeted fitness function value for 10
independent runs of the optimization process of this circuit compared to those required for
the CS, DE, and PSO algorithms. The CS and CSPSO algorithms consume more function
evaluations (𝐹𝐸𝑎𝑣𝑔) compared to the DE and PSO algorithms. Thus, the CS and CSPSO
algorithms outperform both the DE and PSO algorithms in terms of success rate.
TABLE 4.32: Performance of different EAs for optimization of FOTA in 0.35 µm CMOS technology
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 0.0 2.6e-2 2.6e-3 7.8e-3 42.2 1296 9 2838
PSO 0.0 5.7e-1 3.2e-1 2.1e-1 85.4 2562 2 4988
CS 0.0 0.0 0.0 0.0 63.90 3864 10 8227
CSPSO 0.0 0.0 0.0 0.0 28.3 2577 10 5514
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the optimization
of FOTA with 0.35 µm CMOS technology is shown in Fig. 4.18. It shows that the CSPSO
algorithm is faster in obtaining the targeted fitness function value compared to the CS, DE,
and PSO algorithms. Thus, the CSPSO algorithm performs better than the CS, DE, and
PSO algorithms in terms of the final solution and convergence speed.
Moderately Complex CMOS based Analog Circuit Optimization
71
FIGURE 4.18: Convergence graph of different EAs for FOTA optimization in 0.35 µm CMOS
technology
This circuit is also optimized with 0.18 µm CMOS technology by the CS, hybrid CSPSO,
PSO, and DE algorithms. The search space and optimized values achieved by different
EAs for the design parameters of this circuit with 0.18 µm CMOS technology are listed in
Table 4.33.
TABLE 4.33: Search space and optimized parameters by different EAs for FOTA in 0.18 µm CMOS
technology
Sr.
No.
Design
Parameters
Search Space of
Design
Parameters
Optimized values of Design Parameters
PSO DE CS CSPSO [116]
1 𝑊1,2,12 (µm) 1 µm to 200 µm 196.01 188.46 156.87 61.61 30
2 𝑊3,4 (µm) 1 µm to 200 µm 100.13 99.92 43.81 56.13 24
3 𝑊5,6 (µm) 1 µm to 200 µm 194.31 200 78.34 160.87 4
4 𝑊7,8 (µm) 1 µm to 200 µm 194.31 200 78.34 160.87 42
5 𝑊9,10 (µm) 1 µm to 200 µm 148.71 185.66 168.72 148.61 69
6 𝑊11 (µm) 1 µm to 200 µm 200 200 85.00 112.52 --
7 𝑊13 (µm) 1 µm to 200 µm 137.05 200 34.03 144.06 --
8 𝑊14 (µm) 1 µm to 200 µm 154.46 200 198.44 63.42 --
9 𝐼𝑏𝑖𝑎𝑠 (µA) 1 µA to 200 µA 115.34 139.53 73.86 84.86 --
In Table 4.34, desired specifications and obtained specifications through simulation for the
above-optimized design parameters achieved by employing the different EAs for this
circuit are tabulated. The CS algorithm achieved all the targeted specifications with the
Analog Circuit Optimization
72
least power dissipation (𝑃𝑑𝑖𝑠𝑠) i.e. 437.15 µW and the least TTA i.e. 1526.54 µm2
compared to those achieved by the CSPSO, DE, and PSO algorithms.
TABLE 4.34: Desired specifications and simulation results by different EAs for FOTA in 0.18 µm
CMOS technology
Sr.
No. Specifications
Desired
value
Obtained Specifications
PSO DE CS CSPSO [116] [117]
1 𝐴𝑣 (dB) > 70 76.52 77.58 77.78 78.61 52.1 49.3
2 UGB (MHz) > 100 122.83 152.02 154.16 133.67 50.1 31.4
3 PM (°) > 45 80.01 68.93 62.33 71.53 83.3 86.9
4 +ve PSSR (dB) > 65 76.87 79.93 79.08 80.15 -- --
5 -ve PSSR (dB) > 75 76.29 78.04 78.43 78.30 -- --
6 RSR (V/µs) > 30 71.09 165.30 169.88 65.65 34.4 12
7 FSR (V/µs) > 30 37.42 43.09 38.37 33.57 -- 31.6
8 CMRR (dB) > 80 130.32 149.17 134.35 132.04 -- --
9 𝑃𝑑𝑖𝑠𝑠 (µW) < 1000 703.54 841.54 437.15 528.81 720 360
10 𝑁𝑖𝑛 (µV/√𝐻𝑧)
@ 1 Hz < 20 8.69 8.18 11.35 9.75 8.74 13.5
11 𝑁𝑖𝑛𝑡 (µVrms)
(1 Hz – 100 MHz) < 200 85.86 67.29 94.46 82.51 78.3 76.8
12 TTA (µm2 ) < 3000 2354.46 2536.53 1526.54 1557.83 1200 700
Akbari et al. [116][117] have reported the optimization of the same circuit through gm/ID
methodology using the same CMOS technology. Results reported in the literature are
presented in Table 4.34 for the performance comparison. From which, it can be observed
that although we have considered some additional specifications compared to those
reported in the literature, our methodology is able to satisfy the objective function of this
design problem.
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit using 0.18 µm CMOS technology for 10 independent runs are listed in Table
4.35. The CSPSO succeeded 10 times out of 10 runs to achieve all the targeted
specifications, whereas the CS algorithm succeeded 9 times out of 10 runs, the DE
algorithm succeeded 7 times out of 10 runs, and the PSO algorithm succeeded only 2
times out of 10 runs to achieve all the targeted specifications during the optimization
process of this circuit. The CSPSO algorithm required the least average number of
iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) and average function evaluations (𝐹𝐸𝑎𝑣𝑔) for 10 independent runs of
the optimization process of this circuit compared to those required for all other algorithms.
Thus, the CSPSO algorithm outperforms the CS, DE, and PSO algorithms for this case.
Moderately Complex CMOS based Analog Circuit Optimization
73
TABLE 4.35: Performance of different EAs for the optimization of FOTA in 0.18 µm CMOS
technology
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 0.0 1.2e-1 2.2e-2 4.0e-2 60.9 1857 7 3730
PSO 0.0 8.1e-1 1.6e-1 2.3e-1 86.9 2607 2 5470
CS 0.0 1.2e-1 1.2e-2 3.6e-2 48.2 2922 9 6072
CSPSO 0.0 0.0 0.0 0.0 13.30 1227 10 2615
The convergence graph of CS, CSPSO, DE, and PSO algorithms for the optimization of
FOTA with 0.18 µm CMOS technology is shown in Fig. 4.19. It shows that the CSPSO
algorithm converges faster compared to the CS, DE, and PSO algorithms. In Fig. 4.19, a
sudden change of fitness value for CSPSO is appearing due to far-field randomization
used in the Lévy random walk.
FIGURE 4.19: Convergence graph of different EAs for FOTA optimization in 0.18 µm CMOS
technology
4.4.4 Miller OTA
Operational transconductance amplifier (OTA) is a significant building block for many
analog circuits and systems. Based on the system requirements, an OTA must fulfil many
design requirements. There are different topologies of CMOS Miller OTA presented in the
Analog Circuit Optimization
74
literature [118][119]. Here, a simple rail-to-rail CMOS Miller OTA is sized using different
EAs. The circuit diagram of CMOS Miller OTA is shown in Fig. 4.20. The main parts of
this circuit are bulk-driven differential amplifier and dc level shifters. The inputs are
applied at the bulk-terminals of the M1 and M2 transistors. This circuit has rail-to-rail
input and output swing. This circuit is suitable for low voltage and low power
applications.
FIGURE 4.20: Miller OTA [118]
The circuit is optimized to drive the load capacitor of 15 pF. The supply voltage is set to
±600 mV for both 0.18 µm and 0.35 µm CMOS technologies. The length of transistor Mi
is considered as 𝐿𝑖 and the width of transistor Mi is considered as 𝑊𝑖 , where 𝑖 =
1, 2, . . . . , 9, 𝑎𝑛𝑑 𝑝. The width of different transistors is considered as 𝑊1 = 𝑊2, 𝑊3𝑎 =
𝑊4𝑎, 𝑊3𝑏 = 𝑊4𝑏, 𝑊5, 𝑊6, 𝑊7, 𝑊8 = 𝑊9, and width of Mp transistor as 𝑊𝑝 for this circuit.
The length of different transistors is set as 𝐿1 = 𝐿 2 = 𝐿3𝑎 = 𝐿4𝑎 = 𝐿3𝑏 = 𝐿4𝑏 = 𝐿6 = 1
µm and 𝐿5 = 𝐿7 = 𝐿8 = 𝐿9 = 𝐿𝑝 = 9 µm for the optimization process of this circuit. So,
this circuit has eleven design parameters namely 𝑊1 = 𝑊2, 𝑊3𝑎 = 𝑊4𝑎, 𝑊3𝑏 = 𝑊4𝑏, 𝑊5,
𝑊6, 𝑊7, 𝑊8 = 𝑊9, 𝑊𝑝, 𝑅𝑐, 𝐶𝑐, and 𝐼𝑏𝑖𝑎𝑠 as observed from Fig. 4.17. The search space and
optimized values achieved by different EAs for the design parameters of this circuit with
0.35 µm CMOS technology are listed in Table 4.36.
Moderately Complex CMOS based Analog Circuit Optimization
75
TABLE 4.36: Search space and optimized parameters by different EAs for Miller OTA in 0.35 µm
CMOS technology
Sr.
No.
Design
Parameters
Search
Space of
Design
Parameters
Optimized values of Design Parameters
PSO DE CS CSPSO [61] [45] [118]
1 𝑊1 = 𝑊2
(µm)
1 µm to 200
µm 138.12 200 173.51 196.71 67 130 250
2 𝑊3𝑎 = 𝑊4𝑎
(µm)
1 µm to 200
µm 199.80 136.01 35.63 75.95 32 19.5 100
3 𝑊3𝑏 = 𝑊4𝑏
(µm)
1 µm to 200
µm 163.13 200 53.41 99.92 41.5 86. 400
4 𝑊5 (µm) 1 µm to 200
µm 174.82 200 150.74 197.31 180 87 200
5 𝑊6 (µm) 1 µm to 200
µm 188.90 200 23.51 79.72 62 86.5 400
6 𝑊7 (µm) 1 µm to 200
µm 122.80 200 65.83 119.74 150.5 104 800
7 𝑊8 = 𝑊9
(µm)
1 µm to 200
µm 40.75 27.46 13.26 12.87 17 18 100
8 𝑊𝑝 (µm) 1 µm to 200
µm 100.55 39.09 1.44 99.54 83 34.5 200
9 𝑅𝑐 (kΩ) 1 kΩ to 200
kΩ 55.47 100.00 74.60 77.47 96 81 73.1
10 𝐶𝑐 (pF) 1 pF to 10
pF 8.90 5.24 2.69 2.67 2.1 1.9 5
11 𝐼𝑏𝑖𝑎𝑠 (nA) 1 nA to
1000 nA 533.20 200 2.31 498.87 180 109 130
Desired specifications and obtained specifications through simulation for the above-
optimized design parameters achieved by employing the different EAs for this circuit are
listed in Table 4.37.
TABLE 4.37: Desired specifications and simulation results by different EAs for Miller OTA in 0.35
µm CMOS technology
Sr.
No. Specifications
Desired
value
Obtained Specifications
PSO DE CS CSPSO [61] [45] [118]
1 𝐴𝑣 (dB) > 75 63.12 86.72 86.98 90.90 74.92 82.67 73.5
2 UGB (kHz) > 10 15.71 45.60 72.82 61.16 42.27 48.61 13.02
3 PM (°) > 45 81.62 79.23 50.14 53.29 49.56 58.01 54.1
4 +ve PSSR (dB) > 90 83.30 90.07 89.52 96.18 -- -- 58.1
5 -ve PSSR (dB) > 70 64.01 73.15 78.78 76.76 -- -- --
6 RSR (V/ms) > 10 26.82 53.54 25.41 29.71 17.28 21.77 14.7
7 FSR (V/ms) > 10 19.02 23.02 25.51 14.78 14.36 23.11 14.7
8 CMRR (dB) > 100 77.40 114.45 101.32 103.08 -- -- 67.4
9 𝑃𝑑𝑖𝑠𝑠 (nW) < 1000 1112 990.32 845.36 953.15 540 545.49 550
10 𝑁𝑖𝑛 (nV/√𝐻𝑧)
@ 1 kHz < 500 686.58 499.97 468.03 499.61 -- -- 290
11 𝑁𝑖𝑛𝑡 (µVrms)
(1 Hz – 100 kHz) < 300 260.44 180.77 170.84 182.78 -- -- --
12 TTA (µm2 ) < 1500 5508 5718.10 2749.47 4805.79 3348 2911.5 14500
Analog Circuit Optimization
76
The number of desired specifications, in this case, are twelve i.e. 𝐴𝑣 , UGB, PM, +ve
PSSR, -ve PSSR, RSR, FSR, CMRR, 𝑃𝑑𝑖𝑠𝑠 , 𝑁𝑖𝑛 @ 1 kHz, 𝑁𝑖𝑛𝑡 over the specified
frequency range from 1 Hz to 100 kHz, and TTA. The complexity of the optimization
problem for this circuit is more compared to the optimization problem of DA, two-stage
op-amp, and FOTA circuits because of the larger number of design parameters for this
circuit. The CS algorithm achieved all the targeted specifications with the least power
dissipation (𝑃𝑑𝑖𝑠𝑠) i.e. 845.36 nW and the least Total MOS Transistor Area (TTA) i.e.
2749.47 µm2 compared to those achieved by the CSPSO, DE, and PSO algorithms.
Thakkar et al. [45] have reported the optimization of the same circuit using the HPSO
algorithm, Gupta et al. [61] have applied the ACO algorithm for the optimum design of
the same circuit, and Ferreira et al. [118] have used the Laker and Sansen method to obtain
the size of the same circuit using similar CMOS technology. Results reported in the
literature are presented in Table 4.37 for the performance comparison. From which, it is
revealed that although we have considered some additional specifications compared to
those reported in the literature, our methodology is able to satisfy the objective function of
this design problem.
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit with 0.35 µm CMOS technology for 10 independent runs are listed in Table
4.38. The CSPSO algorithm succeeded 7 times out of 10 runs, the CS algorithm and the
DE algorithm succeeded 4 times out of 10 runs to achieve all targeted specifications
during the optimization process of this circuit, whereas the PSO algorithm could not
obtain success for a single time to achieve all the targeted specifications. The CS and
CSPSO algorithms required the less average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) for 10
independent runs of the optimization process of this circuit compared to those required for
the DE and PSO algorithms. Thus, the CS and CSPSO algorithms outperform both the DE
and PSO algorithms for this case also.
TABLE 4.38: Performance of different EAs for optimization of Miller OTA in 0.35 µm CMOS
technology
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 0.0 1.2e-1 3.2e-2 4.2e-2 92.2 2796 4 3794
PSO 3.3e-1 1.13 5.7e-1 2.3e-1 100 3000 0 4374
CS 0.0 8.8e-2 3.1e-2 3.4e-2 86.8 5238 4 7233
CSPSO 0.0 9.5e-2 1.8e-2 3.4e-2 80.50 7275 7 9978
Moderately Complex CMOS based Analog Circuit Optimization
77
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for Miller OTA is
shown in Fig. 4.21. It also shows the CSPSO algorithm performs better than the CS, DE,
and PSO algorithms in terms of the final solution and convergence speed.
FIGURE 4.21: Convergence graph of different EAs for Miller OTA optimization in 0.35 µm CMOS
technology
This circuit is also optimized with 0.18 µm CMOS technology by the CS, hybrid CSPSO,
PSO, and DE algorithms. The search space and optimized values achieved by different
EAs for the design parameters of this circuit using 0.18 µm CMOS technology are listed
in Table 4.39.
TABLE 4.39: Search space and optimized parameters by different EAs for Miller OTA in 0.18 µm
CMOS technology
Sr.
No.
Design
Parameters
Search Space of
Design
Parameters
Optimized values of Design Parameters
PSO DE CS CSPSO [45] [120]
1 𝑊1 = 𝑊2 (µm) 1 µm to 200 µm 135.38 200 200 200 17 486
2 𝑊3𝑎 = 𝑊4𝑎 (µm) 1 µm to 200 µm 200 130.08 54.76 200 38.5 114
3 𝑊3𝑏 = 𝑊4𝑏 (µm) 1 µm to 200 µm 200 200 113.92 163.59 138 170
4 𝑊5 (µm) 1 µm to 200 µm 156.58 188.32 63.22 181.44 122.5 356
5 𝑊6 (µm) 1 µm to 200 µm 165.61 200 98.90 200 98 200
6 𝑊7 (µm) 1 µm to 200 µm 171.41 200 76.36 99.54 194 416
7 𝑊8 = 𝑊9 (µm) 1 µm to 200 µm 73.44 21.30 1.32 1.00 15 200
8 𝑊𝑝 (µm) 1 µm to 200 µm 184.77 95.19 61.61 134.87 110.5 179
9 𝑅𝑐 (kΩ) 1 kΩ to 200 kΩ 95.63 100.00 1.00 90.31 99 100
10 𝐶𝑐 (pF) 1 pF to 10 pF 10 4.30 1.00 1.00 2.7 5
11 𝐼𝑏𝑖𝑎𝑠 (nA) 1 nA to 1000 nA 695.13 466.25 476.43 646.00 350 50
Analog Circuit Optimization
78
Table 4.40 reveals the desired specifications and obtained specifications through
simulation for the above-optimized design parameters achieved by employing the different
EAs for this circuit. The CS algorithm achieved all the targeted specifications with the
least power dissipation (𝑃𝑑𝑖𝑠𝑠) i.e. 591.49 nW and the least Total MOS Transistor Area
(TTA) i.e. 2670.74 µm2 compared to those achieved by the CSPSO, DE, and PSO
algorithms.
Thakkar et al. [45] have reported the optimization of the similar circuit using the HPSO
algorithm and Akbari et al. [120] have reported the optimization of the similar circuit
through Gm-C compensation technique with similar CMOS technology. Results reported
in the literature are presented in Table 4.40 for the performance comparison. From which,
it can be observed that although we have considered some additional specifications
compared to those reported in the literature, our methodology is able to satisfy the
objective function of this design problem.
TABLE 4.40: Desired specifications and simulation results by different EAs for Miller OTA in 0.18
µm CMOS technology
Sr.
No. Specifications
Desired
value
Obtained Specifications
PSO DE CS CSPSO [45] [120]
1 𝐴𝑣 (dB) > 75 67.11 86.14 81.76 93.08 75 72.5
2 UGB (kHz) > 10 16.61 78.70 74.64 52.45 58 9.5
3 PM (°) > 45 84.43 59.61 75.63 70.94 59.7 76
4 +ve PSSR (dB) > 90 138.26 127.62 129.38 130.93 -- --
5 -ve PSSR (dB) > 80 62.87 78.15 84.15 83.42 -- --
6 RSR (V/ms) > 10 22.46 48.00 32.16 26.06 30.87 --
7 FSR (V/ms) > 10 25.74 25.34 13.37 13.54 16.4 --
8 CMRR (dB) > 100 107.30 109.62 103.48 114.50 -- 114.7
9 𝑃𝑑𝑖𝑠𝑠 (nW) < 1000 1117.47 963.57 591.49 914.84 571 396
10 𝑁𝑖𝑛 (nV/√𝐻𝑧)
@ 1 kHz < 500 636.12 308.88 365.83 285.72 -- 169
11 𝑁𝑖𝑛𝑡 (µVrms)
(1 Hz – 100 kHz) < 300 240.10 111.94 144.73 127.93 -- 116
12 TTA (µm2 ) < 14500 7173.23 5995.38 2670.74 5087.90 4598 5911
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit with 0.18 µm CMOS technology for 10 independent runs are listed in Table
4.41. The CS and CSPSO algorithms succeeded 10 times out of 10 runs to achieve all the
targeted specifications during the optimization process of this circuit, whereas the DE and
PSO algorithms did not succeed a single time to achieve all the targeted specifications.
Moderately Complex CMOS based Analog Circuit Optimization
79
The CSPSO and CS algorithms required the less average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔)
for 10 independent runs of the optimization process of this circuit compared to those
required for the DE and PSO algorithms. Thus, the CS and CSPSO algorithms outperform
both the DE and PSO algorithms for this case also.
TABLE 4.41: Performance of different EAs for optimization of Miller OTA in 0.18 µm CMOS
technology
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 2.3e-3 6.0e-2 2.6e-2 1.6e-2 100 3030 0 4871
PSO 1.9e-1 6.5e-1 4.0e-1 1.6e-1 100 3000 0 4086
CS 0.0 0.0 0.0 0.0 51.10 3096 10 4183
CSPSO 0.0 0.0 0.0 0.0 49.3 4467 10 6099
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for Miller OTA is
shown in Fig. 4.22. It also shows that the CS and CSPSO algorithms are able to reach at
the targeted fitness value, whereas the DE and PSO algorithms are not able to reach the
targeted fitness value within the limit of the maximum number of iterations. Thus, the CS
and CSPSO algorithms give a better solution with higher convergence speed compared to
the PSO and DE algorithms.
FIGURE 4.22: Convergence graph of different EAs for Miller OTA optimization in 0.18 µm CMOS
technology
Analog Circuit Optimization
80
4.5 Summary
In this chapter, the basis of the automatic cell sizing of CMOS based analog circuits is
introduced. The EAs give a great improvement in the analog circuit design automation
process. The focus is set on the performance of different metaheuristic EAs for the
solution of practical problems in the electronic design automation field. As the number of
desired specifications of a circuit and design parameters increase, the optimization
problem becomes more complex and takes more time to optimize a given circuit. The
optimization problems of DA, two-stage op-amp, and OTA are more complex. The
performance of the CS, hybrid CSPSO, DE, and PSO algorithms for the optimization of
simple as well as moderately complex CMOS based analog circuits are evaluated. The CS
and CSPSO algorithms have given are more consistent performance than the DE and PSO
algorithms in finding the targeted results. Only with basic knowledge of the circuit, the
user can design an analog circuit for the given specifications using this methodology.
Introduction
81
CHAPTER-5
5 PVT-aware Circuit Optimization
5.1 Introduction
This chapter explores robust CMOS based analog circuit designs i.e. designs that are
guaranteed to meet a set of specifications with the Process, Supply Voltage, and
Temperature (PVT) variation effects. First, the effects of the PVT variations on the
performance of CMOS based analog circuits are introduced. Then, the optimization of
CMOS based analog circuits such as DA and two-stage op-amp circuits with PVT
variations are presented.
5.2 PVT Variation
Process (𝑃), Supply Voltage (𝑉), and Temperature (𝑇) are three important factors which
contribute to performance variation of the CMOS based analog circuits [121]. Process
variations are due to deviation in a fabrication process. Variation in the process parameters
can be impurity concentration densities, oxide thicknesses, and diffusion depths. This
introduces variations in the sheet resistance and transistor parameters such as threshold
voltage. This causes variations in (𝑊/𝐿) of MOS transistors. There are five possible
process corners known as Typical- Typical (TT), Fast-Fast (FF), Slow-Slow (SS), Fast-
Slow (FS), and Slow-Fast (SF). The performance of a MOS transistor also depends on the
power supply. The variation in the supply voltage affects the saturation current which
inflects the propagation delay of a cell. The supply voltage is not constant throughout the
PVT-aware Circuit Optimization
82
chip, hence the prorogation delay varies in a chip. Temperature variation is unavoidable in
every day’s operation of a design. During operation of a chip, the temperature can vary
throughout the chip. This is due to the power dissipation in the MOS transistors. The
power consumption in the MOS transistor is mainly due to switching, short-circuit, and
leakage power consumption.
5.3 Circuit Optimization with PVT Corners
PVT variations are taken into account by individually varying 𝑃 , 𝑉 , and 𝑇 over their
allowable ranges and analyzing subsequent combinations are called PVT corners. In
modern designs, there can be hundreds or thousands of PVT corners. The main aim of
PVT analysis is to find the worst-case performance values across user-defined PVT
corners. The robustness and yield of the designed circuit are increased by guaranteeing
that it complies with all design goals and constraints in some or all corners. The problem
is that simulating each corner can take several seconds or minutes based on the complexity
of the circuit. To simulate all possible corners could take hours or even days. Here, three
process corners i.e. TT, FF, and SS, three values of a supply voltage, and three values of
temperature are considered during PVT-aware circuit design as a proof of concept. So,
there would be a total of 3*3*3 = 27 combinations of the PVT corners.
Two-step approach, as shown in Fig. 5.1, is used to find the worst-case performance with
PVT analysis [122]. PVT corners are used within the iterative circuit optimization loop for
PVT-aware circuit optimization. First, the optimization of a circuit for the targeted
specifications is only done. After the circuit optimization with the required fitness function
value by the optimizer implemented using an EA, the circuit is tested with user-defined
PVT corners. If the circuit fulfils the required fitness value for each user-defined PVT
corners then the optimization process will stop. If the circuit does not satisfy the required
fitness value for any user-defined PVT corners, then the optimizer will redesign the circuit
until the termination criteria are not fulfilled. The termination criteria are either the
maximum number of iterations that have been reached or a minimum fitness function
value is satisfied. If the termination criteria meet, then this process will stop.
Circuit Optimization with PVT Corners
83
Optimization of a circuit
Termination criteria
Desired optimized solution
Yes
Optimization with
PVT corners
No
Fitness
function value
< 1e-6
FIGURE 5.1: Two-step approach for circuit design with PVT variations
The PVT analysis is carried out for DA with a current mirror and two-stage op-amp
circuits with 0.18 µm CMOS technology during the optimization process with the CS,
hybrid CSPSO, PSO, and DE algorithms.
5.3.1 Optimization of DA with PVT Corners
The circuit diagram of DA with a current mirror load is presented in chapter 4 (page No.
53). The length of transistor Mi is considered as 𝐿𝑖 and width of transistor Mi is
considered as 𝑊𝑖, where 𝑖 = 1, 2, . . . . . , 6. For the optimization process of this circuit with
different PVT corners using 0.18 µm CMOS technology, the length of different transistors
is set as 𝐿1 = 𝐿2 = 𝐿3 = 𝐿4 = 3.5 µm and 𝐿5 = 𝐿6 = 1.4 µm. The width of different
transistors is set as 𝑊1 = 𝑊2, 𝑊3 = 𝑊4, and 𝑊5 = 𝑊6 . So, this circuit has four design
parameters namely 𝑊1 = 𝑊2, 𝑊3 = 𝑊4, 𝑊5 = 𝑊6, and 𝐼𝑏𝑖𝑎𝑠. The circuit is optimized to
drive the load capacitor of 0.5 pF. The supply voltage is set to ±1.8 V. The search space
and optimized values achieved by different EAs for the design parameters of this circuit
with 0.18 µm CMOS technology with the PVT-aware circuit optimization process are
listed in Table 5.1.
PVT-aware Circuit Optimization
84
TABLE 5.1: Search space and optimized parameters by different EAs for DA in 0.18 µm CMOS
technology with PVT variations
Sr. No. Design
Parameters
Search Space of
Design
Parameters
Optimized values of Design Parameters
PSO DE CS CSPSO
1 𝑊1 = 𝑊2 (µm) 3.5 µm to 30 µm 27.10 25.80 10.97 22.29
2 𝑊3 = 𝑊4 (µm) 3.5 µm to 30 µm 12.17 10.06 3.50 3.50
3 𝑊5 = 𝑊6 (µm) 3.5 µm to 30 µm 28.82 27.92 8.25 4.69
4 𝐼𝑏𝑖𝑎𝑠 (µA) 3.5 µA to 30 µA 8.46 12.20 8.67 10.00
Desired specifications and obtained specifications through simulation for the above-
optimized design parameters achieved by employing the different EAs with the PVT-
aware optimization process for this circuit are listed in Table 5.2. The CS algorithm
optimized this circuit with the least Total MOS Transistor Area (TTA) of 124.36 µm2 and
the least power dissipation (𝑃𝑑𝑖𝑠𝑠) of 43.62 µW compared to those achieved by the
CSPSO, DE, and PSO algorithms. The TTA i.e. 193.67 µm2 and 𝑃𝑑𝑖𝑠𝑠 i.e. 44.68 µW
obtained by the CSPSO algorithm are also less compared to those achieved by the DE and
PSO algorithms.
TABLE 5.2: Desired specifications and simulation results by different EAs for DA in 0.18 µm CMOS
technology with PVT variations
Sr. No. Specifications Desired
value
Obtained Specifications
PSO DE CS CSPSO
1 𝐴𝑣 (dB) > 39 39.04 39.15 39.48 39.46
2 UGB (MHz) > 10 18.41 23.76 22.09 21.72
3 PM (°) > 45 46.30 46.40 60.15 50.26
4 +ve PSSR (dB) > 35 40.95 41.09 41.09 41.44
5 -ve PSSR (dB) > 60 71.45 71.20 71.28 72.06
6 RSR (V/µs) > 9 21.55 29.60 21.74 21.24
7 FSR (V/µs) > 9 14.64 20.28 17.76 17.23
8 CMRR (dB) > 50 56.18 55.94 58.60 55.80
9 𝑃𝑑𝑖𝑠𝑠 (µw) < 1000 45.04 62.69 43.62 44.68
10 𝑁𝑖𝑛 (nV/√𝐻𝑧)
@ 10 kHz < 50 23.25 19.93 20.08 21.39
11 𝑁𝑖𝑛𝑡 (µVrms)
(1 Hz – 100 kHz) < 50 7.38 6.32 6.38 6.79
12 TTA (µm2 ) < 1500 355.57 329.20 124.36 193.67
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit using 0.18 µm CMOS technology with PVT variations for 10 independent
runs are listed in Table 5.3. The CS and CSPSO algorithms succeeded 10 times out of 10
runs to achieve all the targeted specifications during the optimization process of this
circuit, whereas the DE algorithm succeeded 8 times and the PSO algorithm succeeded 3
Circuit Optimization with PVT Corners
85
times only out of 10 runs to achieve all the targeted specifications for this case. The CS
algorithm took the least average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) for 10 independent runs of
the optimization process of this circuit compared to those required for the DE and PSO
algorithms. The CS and CSPSO algorithms also achieved zero standard deviation
(𝑆𝐷𝑓) for the fitness function. Thus, the CS and CSPSO algorithms outperform the DE
and PSO algorithms for this case.
TABLE 5.3: Performance of different EAs for optimization of DA in 0.18 µm CMOS technology with
PVT variations
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 0.0 5.9e-3 1.1e-3 2.2e-3 40.30 1239 8 3124
PSO 0.0 6.8e-3 2.1e-3 2.4e-3 70.30 2109 3 4875
CS 0.0 0.0 0.0 0.0 8.2 522 10 1027
CSPSO 0.0 0.0 0.0 0.0 23.6 2154 10 4594
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the optimization
of DA with 0.18 µm CMOS technology with PVT-aware circuit optimization is shown in
Fig. 5.2. It shows that the CS algorithm converges faster compared to the DE, CSPSO, and
PSO algorithms. The CS and CSPSO algorithms give a better solution with higher
convergence speed compared to the PSO and DE algorithms.
FIGURE 5.2: Convergence graph of different EAs for DA optimization in 0.18 µm CMOS technology
with PVT variations
PVT-aware Circuit Optimization
86
5.3.2 Optimization of Two-Stage Op-amp with PVT Corners
We have also optimized two-stage op-amp circuit with 0.18 µm CMOS technology at
different PVT corners by the CS, hybrid CSPSO, PSO, and DE algorithms. The circuit
diagram of the two-stage op-amp is presented in chapter 4 (page No. 59). The length of
transistor Mi is considered as 𝐿𝑖 and width of transistor Mi is considered as 𝑊𝑖, where 𝑖 =
1, 2, . . . . , 8. The width of different transistors is considered as 𝑊1 = 𝑊2, 𝑊3 = 𝑊4, and
𝑊5 = 𝑊8 for this circuit. The length of different transistors is set as 𝐿1 = 𝐿2 = 𝐿5 = 𝐿7 =
𝐿8 = 0.75 µm and 𝐿3 = 𝐿4 = 𝐿6 = 0.50 µm for the optimization process of this circuit
with different PVT corners in 0.18 µm CMOS technology. The search space and
optimized values achieved by different EAs for the design parameters of this circuit with
0.18 µm CMOS technology with the PVT variations are listed in Table 5.4.
TABLE 5.4: Search space and optimized parameters by different EAs for op-amp in 0.18 µm CMOS
technology with PVT variations
Sr. No. Design
Parameters
Search Space of
Design
Parameters
Optimized Values of Design Parameters
PSO DE CS CSPSO
1 𝑊1 = 𝑊2 (µm) 1 µm to 10 µm 4.17 2.73 1.41 1.57
2 𝑊3 = 𝑊4 (µm) 1 µm to 10 µm 2.17 2.40 3.35 2.20
3 𝑊5 = 𝑊8 (µm) 1 µm to 10 µm 3.88 3.78 1.00 5.89
4 𝑊6 (µm) 1 µm to 10 µm 9.48 10.00 10.00 8.24
5 𝑊7 (µm) 1 µm to 10 µm 7.85 7.82 1.47 9.57
6 𝐼𝑏𝑖𝑎𝑠 (µA) 1 µA to 10 µA 8.93 10.00 10.00 9.36
Desired specifications and obtained specifications through simulation for the above-
optimized design parameters achieved by employing the different EAs with the PVT-
aware optimization process for this circuit are listed in Table 5.5. The CS algorithm
optimized this circuit with the least Total MOS Transistor Area (TTA) of 13.07 µm2 and
the least power dissipation 𝑃𝑑𝑖𝑠𝑠 of 97.19 µW with the fulfilment of other specifications
compared to those achieved by the CSPSO, DE, and PSO algorithms.
Circuit Optimization with PVT Corners
87
TABLE 5.5: Desired specifications and simulation results by different EAs for op-amp in 0.18 µm
CMOS technology with PVT variations
Sr. No. Specifications Desired
value
Obtained Specifications
PSO DE CS CSPSO
1 𝐴𝑣 (dB) > 60 69.44 69.27 72.36 67.64
2 UGB (MHz) > 10 14.77 13.95 10.37 11.05
3 PM (°) > 45 45.29 49.53 52.41 51.94
4 +ve PSSR (dB) > 70 82.96 82.32 81.91 82.29
5 -ve PSSR (dB) > 70 97.55 105.65 100.99 91.70
6 RSR (V/µs) > 10 14.27 15.66 13.34 15.60
7 FSR (V/µs) > 10 12.46 13.73 12.20 13.44
8 CMRR (dB) > 60 71.43 71.57 76.63 69.23
9 𝑃𝑑𝑖𝑠𝑠 (µw) < 1000 120.58 134.52 97.19 116.00
10 𝑁𝑖𝑛 (nV/√𝐻𝑧)
@ 10 kHz < 50 24.36 25.55 32.24 29.50
11 𝑁𝑖𝑛𝑡 (µVrms)
(1 Hz – 100 kHz) < 50 27.34 28.67 36.18 33.12
12 TTA (µm2 ) < 300 24.87 23.02 13.07 24.68
The performance of the CS, hybrid CSPSO, PSO, and DE algorithms for the optimization
of this circuit with 0.18 µm CMOS technology with PVT variations for 10 independent
runs are listed in Table 5.6. The CS algorithm succeeded 4 times and the CSPSO
succeeded 2 times out of 10 runs to achieve all the targeted specifications during the
optimization process, whereas the DE and PSO algorithms succeeded a single time only
out of 10 runs to achieve all the targeted specifications. The CS and CSPSO algorithms
took the less average number of iterations (𝐼𝑡𝑒𝑟𝑎𝑣𝑔) for 10 independent runs of the
optimization process of this circuit compared to those required for the DE and PSO
algorithms. Thus, the CSPSO and CS algorithms outperform both the DE and PSO
algorithms for this case also.
TABLE 5.6: Performance of different EAs for optimization of op-amp in 0.18 µm CMOS technology
with PVT variations
Algorithm 𝑴𝒊𝒏𝒇 𝑴𝒂𝒙𝒇 𝑴𝒆𝒂𝒏𝒇 𝑺𝑫𝒇 𝑰𝒕𝒆𝒓𝒂𝒗𝒈 𝑭𝑬𝒂𝒗𝒈 𝑺𝒓𝒂𝒕𝒆 𝑻𝒔𝒊𝒎 (s)
DE 0.0 8.7e-1 4.0e-1 3.6e-1 90.10 2733 1 4828
PSO 0.0 7.9e-1 1.8e-1 2.9e-1 90.20 2706 1 4480
CS 0.0 2.4e-1 4.3e-2 7.1e-2 66.4 4014 4 5899
CSPSO 0.0 9.9e-1 1.3e-1 2.9e-1 82 7410 2 11761
The convergence graph of the CS, CSPSO, DE, and PSO algorithms for the optimization
of two-stage op-amp in 0.18 µm CMOS technology with PVT-aware circuit optimization
is shown in Fig. 5.3. It shows that the CS and CSPSO algorithms give lower average
PVT-aware Circuit Optimization
88
fitness value for 10 runs with higher convergence speed compared to the PSO and DE
algorithms. In PVT-aware circuit design procedure, due to different PVT corners, there
may be a possibility of change in the fitness function value as compared to that achieved
for the fixed state. So, the fitness function value may increase or decrease as observed in
Fig. 5.2 and Fig. 5.3 due to the PVT variations.
FIGURE 5.3: Convergence graph of different EAs for two-stage op-amp optimization in 0.18 µm
CMOS technology with PVT variations
5.4 Summary
In this chapter, the focus is set on the PVT-aware circuit optimization to find a design
which meets the desired specifications across all the user-defined PVT corners. DA and
two-stage op-amp circuits with different 27 PVT corners are optimized for the targeted
specifications in 0.18 µm CMOS technology by different metaheuristic EAs. The
performance of each EA is also compared for the PVT-aware design of DA and two-stage
op-amp circuits. The CS and CSPSO algorithms are also highly reliable and give accurate
results compared to the PSO and DE algorithms for the PVT-aware circuit optimization
process.
Conclusions
89
CHAPTER-6
6 Conclusions and Scope of Future Work
6.1 Conclusions
In this research work, the DE, PSO, and CS algorithms are analysed and implemented
using the C programming language. The performance of each algorithm is evaluated
using different ten standard unimodal and multimodal benchmark functions. To exploit
the benefits of the CS and PSO algorithms, the hybrid CSPSO algorithm is implemented
and evaluated. The application and impact of the CS and hybrid CSPSO algorithms are
presented to optimize the basic building blocks of an analog CMOS IC such as voltage
divider, triple cascode current mirror, three-stage current starved VCO, common-source
amplifier, cascode amplifier, DA with a current mirror load, two-stage op-amp, FOTA,
and Miller OTA. Each circuit is optimized by the CS, hybrid CSPSO, PSO, and DE
algorithms for 10 independent runs with different random seeds.
For the optimization process of the triple cascode current mirror circuit, the success for
the CS algorithm is 20 %, for the hybrid CSPSO algorithm is 10 %, whereas the PSO and
DE algorithms could not achieve success even for a single time to obtain all the targeted
specifications. The hybrid CSPSO and CS algorithms achieved 40 % success and 20 %
success respectively for the optimization of the three-stage current-starved VCO, whereas
the PSO and DE algorithms could not attain success for the fulfilment of all the desired
specifications. The success for the optimization of the cascode amplifier circuit is 100 %
for the CS, hybrid CSPSO, and DE algorithms, whereas for the PSO algorithm is only
10 %. The CS and hybrid CSPSO algorithms achieved 100 % success for the optimization
of the DA with a current mirror load circuit for both 0.35 µm CMOS technology as well
Conclusions and Scope of Future Work
90
as for 0.18 µm CMOS technology. For the optimization of the two-stage op-amp circuit
with 0.35 µm CMOS technology, the success for the CS and hybrid CSPSO algorithms is
100 %, whereas the DE and PSO algorithms failed to achieve all the targeted
specifications for all 10 runs with 0.35 µm as well as for 0.18 µm CMOS technologies.
The success rate achieved for the optimization of the FOTA and Miller OTA is higher for
the CS and hybrid CSPSO algorithms compared to the DE and PSO algorithms. The CS
and hybrid CSPSO algorithms are more consistent than the DE and PSO algorithms in
finding the targeted specifications for almost all the optimized circuits. The experimental
simulation results for the standard benchmark functions and the optimization of CMOS
based analog circuits show that the CS and hybrid CSPSO algorithms are highly reliable
and outperform both the DE and PSO algorithms.
PVT variations are also considered for the robust design of DA and two-stage op-amp
during the optimization process. This methodology of analog circuit design simplifies the
design process due to fine-tuning, verification, and optimization of the circuit
functionality over the PVT corners are automated. This design methodology of the analog
circuit is also easy and effective compared to the manual design methodology, even
though the circuit designer does not have detailed knowledge of a given circuit. This work
justifies the effectiveness of the automation for CMOS based analog circuit design which
can be extended to achieve a practical solution for complex analog modules.
6.2 Scope of Future Work
In the area of analog circuit design automation, the exploration is continuously existing
and dynamic. There is yet, a surely long way to end with the design gap between the
enhancement in manufacturing productivity and the growth in productivity attained by
CAD tools and design methodologies. Based on this work, there are some
recommendations and potential research directions that extend this work as the scope of
future work. The suggestions for future research are given as per the following:
To develop an intuitive Graphical User Interface (GUI) for this work, allowing the
designer to manage and interact with the design automation process.
Scope of Future Work
91
To develop a completely analog circuit design automation environment linking the
presented system with automatic topology selection and chip layout generation
modules. The merger of layout information with the optimization sizing process
improves the robustness and consistency of the design solutions.
Other nature-inspired EAs can be explored for analog circuit design automation
and evaluate their performance.
This methodology can also be applied to optimize other circuits and can be
inserted into any electronic CAD software.
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List of Publications
99
List of Publications
[1] Pankaj P. Prajapati, Krunal P. Acharya, and Mihir V. Shah, “Optimal cell sizing of CMOS two-
stage operational amplifier using cuckoo search algorithm,” in Journal of Artificial Intelligence
Research and Advances, eISSN No. 2395-6720, vol. 6, no. 2, pp. 109-118, July 2019.
[2] Pankaj P. Prajapati, Krunal P. Acharya, and Mihir V. Shah, “Optimization of CMOS Miller OTA
using differential evolutionary algorithm,” in Internation Journal of Intelligent Systems and
Applications in Engineering, ISSN No. 2147-6799, vol. 7, no. 1, pp. 47-51, March 2019,
DOI: https://doi.org/10.18201/ijisae.2019151254.
[3] Pankaj P. Prajapati and Mihir V. Shah, “Optimization of CMOS current mirror load-based
differential amplifier using hybrid cuckoo search and particle swarm optimization algorithm,” in
Journal of Artifical Intelligence Research & Advances, eISSN No. 2395-6720, vol. 5, no. 3, pp. 71-
78, Feb. 2019.
[4] Pankaj P. Prajapati and Mihir V. Shah, “Performance estimation of differential evolution, particle
swarm optimization, and cuckoo search algorithms,” in International Journal of Intelligent Systems
and Applications (IJISA), ISSN No. 2074-9058, vol. 10, no. 6, pp. 59-67, June 2018, DOI:
10.5815/ijisa.2018.06.07.
[5] Pankaj P. Prajapati and Mihir V. Shah, “Automated sizing methodology for CMOS Miller
operational transconductance amplifier,” in Soft Computing: Theories and Applications, Advances
in Intelligent Systems and Computing, Springer, Singapore, ISSN No. 2194-5357, vol. 584, pp.
301-308, Nov. 2017, DOI.org/10.1007/978-981-10-5699-4_29.
[6] Pankaj P. Prajapati, Swati A. Sharma, and Mihir V. Shah, “Design of CMOS operational
amplifier using differential evolutionary algorithm,” in NCCICT-2016, GEC, Gandhinagar, ISBN
978-93-5288-056-0, pp. 108-111, Sep. 2016.
[7] Pankaj P. Prajapati and Mihir V. Shah, “Two stage CMOS operational amplifier design using
particle swarm optimization algorithm,” in Proceeding of IEEE UP Section Conference on
Electrical, Computer and Electronics, IIIT- Allahabad, Dec. 2015, DOI: 10.1109/UPCON.2015.
7456700.
[8] Pankaj P. Prajapati and Mihir V. Shah, “Automatic circuit design of CMOS Miller OTA using
cuckoo search algorithm,” accepted in International Journal of Applied Metaheuristic Computing
(IJAMC), ISSN No. 1947-8283, May 2018.
[9] Pankaj P. Prajapati and Mihir V. Shah, “Automatic sizing of CMOS based analog circuits using
cuckoo search algorithm,” accepted in International Journal of Intelligent Systems Technologies
and Applications, ISSN No. 1740-8865, Sep. 2018.