Class17 18 IBIS Io Buffer Class
description
Transcript of Class17 18 IBIS Io Buffer Class
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I/O Buffer Modeling Class 2 lectures
Prerequisite Reading – Chapter 7IBIS spec will be used as reference
Additional Acknowledgement to Arpad Muranyi, Intel Corporation
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Additional Information
URLsIBIS home page: http://www.eigroup.org/ibis/ibis.htmIBIS 3.2 spec: http://www.vhdl.org/pub/ibis/ver3.2/IBIS-X: http://www.eda.org/pub/ibis/futures/
ToolsGolden Parser: http://www.eda.org/pub/ibis/ibischk3Visual IBIS editor, SPICE-to-IBIS tool on IBIS web site. We will use this free tool. http://www.mentor.com/hyperlynx/visibis.cfm
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Key Topics What is a model? Importance of accurate models Types of buffer models IBIS and the portions of an IBIS model How model data is generated How to calculate VOL and VOH from a model Package modeling in IBIS IBIS HSPICE example Bergeron diagrams
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Theories, Modeling, and Reality“I take the positivist viewpoint that a physical theory
is just a mathematical model and that it is meaningless to ask whether it corresponds to reality. All that one can ask is that its predictions should be in agreement with observation. “ 1
1 Steven W. Hawking, September 30 1994, Public Lecture on “Time and Space”
Electrical models can be derived in two waysFrom physical structures and propertiesFrom observed behavior
It is irrelevant whether the electrical models correspond to physical reality.
It only needs to predict behavior.Hence all models are behavioral
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What is a Model?
Electrical representation of a physical device For example, a transmission line can be modeled as:
A package can be modeled as a combination of transmission lines and lumped elements.
An input or output buffer can be modeled in various ways as well.
? ?
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Importance of Accurate Models T-lines, package, connectors, vias, return paths,
etc. can all be modeled to extreme detail, but if the input (stimulus) is not accurate, it’s wasted.
Garbage in, garbage out.
It is extremely important for engineers to understand the origins of model data, be familiar with modeling types and limitations, and double-check models, whether they create them or they receive them from someone else!
Also, know how your tool uses model data!
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How do we model I/O buffers?
Linear Models
Description
Mor
e de
tail
BehavioralModels
Linear or non-linearI-V and V-t data
TransistorCircuit / Netlist
SimulationSpeed
All buffer details including driving transistors, pre-driver circuitry, receiver diff. amp,
etc.
Intellectual Property
“Sweep-ability”
RS
Slowest
Fast
Fast Very
Somewhat
limited
Very Little
Little
Lots
RHigh
RLow
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Basic C-MOS Buffer Model
Pad Capacitance
Output / Driver Input / Receiver
ESD Diodes+
Inherent Diodes in Transistors
Pull-upDevice
Pull-downDevice
9Review Lattice Diagram Analysis
V(source) V(load)
Vlaunch
source
load
Vlaunch load
Vlaunch
0
Vlaunch(1+load)
Vlaunch(1+load +load source)
Time
0
2N ps
4N ps
Vlaunch loadsource
Vlaunch loadsource
Vlaunch load
source
Vlaunch(1+load+loadsource+
loadsource)
Time
N ps
3N ps
5N psVs
RsZoV(source) V(load)
TD = N ps0Vs
Rt
A signal can be determined by just knowing Vlaunch, load, and
source plus delay
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Refining Buffer Assumptions
The original assumption was that Vlaunch, load and source are constant in time and linear.
Most buffers are not linear.In other words, there is a current dependent voltage that changes with the time varying voltage.We call these “I-V” curve elements instead of resistors, capacitors, or inductors
Vintial VsZL
ZL Z0 load
ZL Z0ZL Z0
sourceZS Z0ZS Z0
and and
ZL Zload V I( )ZS Zsource V I( )
then then
Vintial VsZload V I( )
Zload V I( ) Z0 load
Zload V I( ) Z0
Zload V I( ) Z0source
Zsource V I( ) Z0
Zsource V I( ) Z0
11Beginning of Behavioral Buffer Modeling
This was the basis for a buffer specification that was created in the early 90’s called IBIS
Consider that Vs is Vs(t) and V is V(t), so Vintial, load, and source are Vinitial(t), load(t), and source(t). Also, the propagation functions can be described in a similar manner.Hence the voltage and current response and for all nodes in the network can be determined by replacing the buffer with the appropriate “I-V” impedance functions and don’t require the actual transistor models for the buffer.
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IBIS and Other Model Types IBIS = I/O Buffer Information Specification The beginnings of IBIS occurred at Intel during
Pentium Pro days. Engineers wanted a way to give buffer information to customers, and decided on I-V curves. The initial IBIS spec was created shortly thereafter. IBIS went through many iterations, eventually adding V-t curves (rev 2.1) and other features like staged devices (rev 3.0). The current revision is 3.2.
Other I-V/V-t model types include:Various simulator vendors have their own internal models.
However most will convert IBIS to their internal format.We often use controlled switched resistors (V-t curves of sorts) in SPICE.
Colloquial Terminology ~ V-t = V/T = V(t); I-V = I/V = I(V)
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What is in an IBIS file?
First IBIS is a standard for describing the analog behavior of the buffers of digital devices using plain ASCII text formatted data
IBIS files are really not models, they just contain the data that will be used. Casually they may be referred to as a models but are really specifications.Simulation tools interpret this behavioral specification to implement their own models and algorithms
Key areas of spec
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Key Portions of an IBIS Model
Die Pad Capacitance
Output / Driver Input / Receiver
ESD Diodes+
Inherent Diodes in Transistors
Pull-downDevice
I(V)V(t)
I(V)V(t)
I(V)
I(V) I(V)
I(V)
Pull-upDevice Vcc
Vss may be 0V
Vcc
Vss may be 0V
Package
Package
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MOS I-V Curves Impedance of a buffer is dynamic during transitions - between fully open and fully
driving (RON). Example – let’s take a look at a high-to-low transition below. In the next few slides we will learn how we can model this dynamic
V-I characteristic.
VOUT (t=0) = VCC
VGS (t=0) = 0
VCC
Triode(Ohmic)
Saturation
t=2t=0, t=1
(no current below Vt)
t=3t=4
t=5
IDtime
VGS
0
VT
1 2 3 4 5
+VGS
-
Gate
Source
Drain +
VDS = VOUT
-
VCC
Drain
Source
Gate
ID
Assume pulled up to Vcc at t=0
Vcc
Vss
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Generating pull down I-V Data
Output / Driver
Pull-downDevice
off
I(V)V(t)
I(V)V(t)
I(V)
I(V)
Pull-upDevice
on
DrivingLOW
+I
Sweep V–Vcc to 2Vcc
Pull-down I-VMeasurement or Simulation Setup
I
V
Current is positive above Vss per definition if I flows
(N-channel curve)
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Generating Ground Clamp I-V Data
Tristate+I
Sweep V–Vcc to 2Vcc
Ground Diode I-VMeasurement or Simulation Setup
I
V
Output / Driver
Pull-downDevice
off
I(V)V(t)
I(V)V(t)
I(V)
I(V)
Pull-upDevice
on
Current is negative below Vss per definition if I flows
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Generating pull up I-V Data
DrivingHIGH
+I
Sweep V–Vcc to 2Vcc
Pull-up I-VMeasurement or Simulation Setup
I V
Vcc
Output / Driver
Pull-downDevice
off
I(V)V(t)
I(V)V(t)
I(V)
I(V)
Pull-upDevice
on
Current is negative below Vcc per definition if I flows.
It is desirable to make the curve referenced to Vcc. Will explain later
(P-channel curve)
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Generating Power Clamp I-V Data
Output / Driver
Pull-downDevice
off
I(V)V(t)
I(V)V(t)
I(V)
I(V)
Pull-upDevice
on
Current is positive above Vcc per definition if I flows
Tristate+I
Sweep V–Vcc to 2Vcc
Pull up diode I-VMeasurement or Simulation Setup I
V
Power Clamp
It is desirable to make the curve referenced to Vcc. Will explain next
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Double Counting Resolution Sometimes the clamp current is not zero
in the range of operation. Before use in IBIS the clamp current
needs to be subtracted. Below is an example for the ground clamp
and pull down data
I
V
Power Clamp
I
VccVcc Vcc
I
VccVcc
I(V)V(t)
I(V)V(t)
I(V)
I(V)
I(V)V(t)
I(V)V(t)
I(V)
I(V)I(V)V(t)
I(V)V(t)
I(V)
I(V)
Pull up measurement
Pull up curve
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I-V Curves in IBIS IBIS uses Vcc-referenced I-V curves for all devices
hooked to the power rail (pull-up and high-side diode).
This effectively shifts and flips the I-V curve. Major reason is so same model can be used
regardless of power connection (independent of Vcc).
For example, a 5-V and 3.3-V part can use the same model.
I
V
I
V
Power Clamp
Power Clamp
I V
Vcc
I V
Vcc
Pull-upPull-up
Measured Curve IBIS Curve
DrivingHIGH +I
Sweep V–Vcc to 2Vcc
Vcc
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Simple model of High/Low drive
The high and low switches are ideally complementary
They switch in opposite senses simultaneously Real devices have slightly different
switching characteristics.
I(V)V(t)
I(V)V(t)
I-V
I-V
Controls V(t) for High Curve
Controls V(t) for Low Curve
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How to Generate the V-t Data
Driver
Vcc
Pull-down V-tMeasurement or Simulation Setup
RLOAD
(typically 50 ohms)
Driver
Pull-up V-tMeasurement or Simulation Setup
RLOAD
(typically 50 ohms)
V
t
VOH
+
V
t
VOH
VCC VCC
V
t
VCC
+
V
t
VOL
VCC
VOL
4 V-t curves are required2 for each switch for high and low switching
Accuracy is improved if Rload is within 20% of the usage model load
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Why Four V-t Curves? It is important for the V-t curves to be time-
correlated. The four V-t curves describe the relative switching
times of the pull-up and pull-down devices.
VOH
VCC
VOL
All V-t curve measurements or simulations are started
at time zero.
NMOS is completely OFF
NMOS begins turning OFF PMOS begins
turning ONPMOS is
completely OFF
NMOS is completely ON
PMOS is completely ON
PMOS begins turning OFF
NMOS begins turning ON
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More on IBIS transition time
Two ways to synchronize switchBuild delay into curvesUse version 3.1 Scheduled drivers
Make sure the total transition time to settling is shorter that half the period.
Start of bit time
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PVT Corners PVT = Process, Voltage, Temperature Models in the past have historically been built at the
“corners.” All buffer characteristics are considered dependent parameters with respect to PVT.
Fast Corner = Fast process, high voltage, low temp.Slow Corner = Slow process, low voltage, high temp.
These can be entered into an IBIS model in the “min” and “max” columns.
Fast/strong in the max columnSlow/weak in the min column
In recent generations we have found that just providing fast and slow corners does not adequately cover all effects. In these cases other model types can be given (e.g., “max ringback” model).
Compensated buffers explode the combination of required buffer corners.
They use extra circuits to counteract (compensate) PVT effectsThis makes PVT and buffer characteristics independent parameters.
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“Envelope” or “Spec” Models Historically, we have repeatedly predicted buffer
strength and edge rates incorrectly.Buffer strengths are often weaker in silicon.Edge rates are often slower in silicon.
One approach that can be used is to create “envelope” or “spec” models. For example:
I
V
Envelope.All measured curves should
fall within these specs.
V
t
Key point!!!:These spec curves can be given to I/O designers to describe required buffer
behavior.
Weak
Strong
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Issues with spec curve models
These are legal according to the spec.
Sometimes more qualification is required.
I
V
Envelope.All measured curves should
fall within these specs.
V
t
Weak
Strong
Instantaneously a short
Instantaneously an open
Non-monotonic
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Example: Create CMOS Model Given:
Vcc = 2.0 VMeasurement threshold = 1 V; VIL = 0.8 V; VIH = 1.2 VNMOS RON = 10 ohmsPMOS RON = 10 ohmsAll edge rates are ramps of 2 V/nsCapacitance at the die pad of the buffer = 2.5 pFClamps are 1 ohms and start 0.6V above and below railsPMOS starts turning on 100 ps after NMOS starts turning off (rising edge)NMOS starts turning on 100 ps after PMOS starts turning off (falling edge)
Will use Mentor Graphic Visual IBIS editor in example
http://www.mentor.com/hyperlynx/visibis.cfm
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Example: Header information
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Package definition and pin allocation
mysimple_buffer
2pF
12mohms2nH
signal001
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Model statement Notice the name “special_IO” is assign to our single pin
before. Many pins and models can specified for single component
mysimple_buffer
signal001 2pF
12mohms2nH
2.5pF
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I-V curves
Construct in this example with a spread sheet
Break session to IBIS Edit to view I/V curves
Assignment: Use this example and change the pull and pull down curves to 15 ohms. Check with Visual IBIS. Correct VT waveforms.
34The 4 V-t waveforms w/ spec 100ps delay
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Match V-t and I-CurvesThe intersection of the load line of
the fixture (specified in the waveform section) and a corresponding I-V curve determines the Voh and Voh that should to be used in the respective V-t section
I
Vdd
Pull down
Vdd Vdd
VddVolV-t
More on load lines later
Fixture load line
R_fixture
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End and Ramp
The ramp is specified but the simulator tool can determine whether to use the ramp or the V-t data
The End statement is require The IBIS 3.1 and 2.1 are spec are
actually readable IBIS code and can be view with an IBIS editor.
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GTL+ on die termination Recall that a GTL buffer contains pull-down
transistors only No switched PMOS Many of Intel’s processors and chipsets have
started to include termination devices inside the I/O buffer.
This eliminates the stub on the PWB to connect to the termination resistance
Vcc
On- or off-die resistor for pull-up and termination
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On-die Termination One way to include on-die termination is to use
superposition and add the termination currents to the diode currents in the clamp sections.
The clamps are always active in an IBIS model, regardless of whether the buffer is driving or receiving. Since the termination is always active, also, this scheme works well.
I V
Vcc
On-diePull-upResistor
I
V
Power Clamp
Vcc+
I
V
Power Clamp + On-die term.(Put full curve into power clamp
section of IBIS model.)
Vcc
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Package Modeling in IBIS Three ways to model packages in IBIS:
Lumped R, L, C values in IBIS filePackage modelsEBD (Electrical Board Description)
Package models and EBDs follow this convention:[Len=l R=r L=l C=c]
Examples:Lumped resistor: Len=0 R=50 L=0 C=0Capacitor package: Len=0 R=[ESR] L=[ESL] C=1uFPackage trace: Len=1.234 R=0 L=10E-9 C=2E-12
40Example: VOL Calculation – Resistor Load Line
The I-V for the resistor load is below
Vcc = 2V50 ohmsRLoad
I
V
Pull-down I-V curve
Load lineSlope = -1/RLOAD
Vcc
VccRLOAD
VOL
50 ohm load line
Zero Current
ZeroVoltage
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Example: VOL Calculation - buffer Now create the NMOS I-V curve for load line
analysis below:
~10ohms
I
V
Pull-down I-V curve
Vcc
VccRLOAD
VOL
~10 I -V
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Example: VOL Calculation Using the intersection of the NMOS I-V curve and
load line, calculate VOL: The Vol should correspond the Vol in the V-t
waveforms
~10ohms
Vcc = 2V
50 ohms
50 ohms
I
V
Pull-down I-V curve
Load lineSlope = -1/RLOAD
Vcc
VccRLOAD
VOL
Sanity check and solution:
Vcc = 2V
50 ohms
10 ohms
VOL = 0.33 V
50 ohm load line
~10 I -V
Zero Current
ZeroVoltage
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Example: Calculate VOH
calculate VOH from the intersection of PMOS I-V curve and the resistor load line:
The Voh should correspond to the Voh in the V-T waveforms
~10ohms
Vcc = 2V
65 ohms
30 ohms
I
VVOH
VCC
Example: VOH = 1.5 VNeeds to agree with V-T data
~10 I -V
30 ohm load line terminated to ground this time)
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Using IBIS Models in HSPICE
Use the IBIS file presented earlier (10 ohm up down resistor.
Compare to
Using prior HSPICE example and MYBUF subciruit library and switch case with alters.
New net list name: testckt_ibis.sp
0-2V.33ns r/f full transition time
10
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Recall HSPICE Block Diagram
Printed WiringBoard
Buffers
packa
ge
packa
ge
Receiver
Data
genera
tor
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Create three libraries for MYBUF ‘driver’ – source/resistor model ‘driver_ibis’ – 10 ohm CMOS IBIS model
using ramp data ‘driver_ibis_two’ - 10 ohm CMOS IBIS
model 2 V-t curves for rising and falling edges. (4 total)
Good example to show how to use libraries.
In some cases we start with a behavioral model move to a transistor model to fine tune the buffer design and solutions space. This modularity enables this migration path with minimal impact to the system model.
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The three alters produces .tr0, .tr1, .tr2
Before the end statement insert the alter statements
Adjust the pulse source to .333 ns
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Resistor Source Library
Use delay to synchronize casesWe will force IBIS to start on the 50%
point in the bit drive waveform
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HSPICE IBIS example This is a simple
example. Many more controls are possible
Buffer=2 tells hspice to use an output buffer model
Ramp_fwf and ramp_rwf = 0 means use the ramp
Ramp_fwf and ramp_rwf = 2 means use the 2 V-t curves for each edge
The edges are scaled by 1/10 also to match the resistor/source
What does NINT do?
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Results: first glance seem not bad
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Closer look at rising wave
Ramp is slightly distorted
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Closer look at falling edge
Ramp produces unexpected results
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Additional IBIS Modeling Information
IBIS files can be tuned to produce desired performance
Simulator may vary on how the IBIS files are used. Especially when the used far away from the specified loads.
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Bergeron Diagrams – Intro. A Bergeron diagram is another way of analyzing a transmission
line. It is useful to analyze:Reflections from non-linear drivers or loadsUsage is in industry is low – Can do same with equations and simulators.
First example – analyze a low-to-high transition: Process
1. Draw all I-V curves of transmitter and receiver2. Transmission lines are load lines of 1/Zo or -1/Zo depending on
direction of wave.3. Start at initial condition. For this case, it is 0V, 0A and move on the
transmission line slope to intersection of load.4. Determine intersection V and I. 5. Create equation for transmission line with -1/Zo slope at the
intersection6. Bounce back and forth using the parallel transmission line load
curves and the receiver load which is a 0v horizontal line for this case and repeat until stable.
7. For this case, voltage on the load line is for Tx and a 0v is for Tx
55Simple Bergeron Bounce Diagram Example
I
V
R Pull-upI-V curve
1) Slope of 1/Z0 2) Slope
of -1/Z0
t=0
Vs/R Initial Voltage -Tx
Forward
Wave
Reverse Wave
V at Rx
~R=10 I -V
Zo=50 ohm (open)
Vs
Open load line
Why I-V’s work?
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Determine Initial Voltage
at TxSolve for VV
Zo
VR
Vs
R V
Vs
R ZoZo
The intersection is where source resistor load line and transmission line forward wave is
Initial wave looks like the voltage divider we expect
Zo
Zo RVs 0.833
0 0.4 0.8 1.2 1.6 20
0.024
0.048
0.072
0.096
0.12
V
Zo
VR
Vs
R
V
First Forward Wave Transmission Line Load CurveIV
Zo
Source Resistor Load Line ( More on f(V) later)I f V( )or IV
R
Vs
R
V 0 .1 2Zo 50R 10Vs 1let
Bergeron Analysis
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Determine first voltage step at Rx
2Vs
R Zo Zo 1.667
at RxV 2Vs
R ZoZo
0 0.4 0.8 1.2 1.6 20
0.024
0.048
0.072
0.096
0.12
V
Zo
VR
Vs
R
V
Zo2
Vs
R Zo
V
The open circuit receiver load line is horizontal line at 0 amps. This where the next wave reflects from. So lets solve for V in the above for where I=0
IV
Zo2
Vs
R Zo
IVs
Zo RandV
Zo
Zo RVsGiven
b 2Vs
R Zo
We can find b because we know one V,I pointsolve for b and substitute V and I
IV
Zob-->I m V b
Now the wave continues with as slope for -1/Zo from this pointThe next task is to determine the equation of this line which has the form
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Find next voltage at Tx again
Now the wave follows the 1/Zo I=mV+b and we solve for b again from above
b 2Vs
R Zo and I
V
Zo2
Vs
R Zo
This line intersects the Tx load line
IV
R
Vs
R so
VR
Vs
R
V
Zo2
Vs
R Zo
at TxV Vs
3 R Zo
R Zo( )2
Zo I VsZo R
R Zo( )2
0 0.4 0.8 1.2 1.6 20.1
0.08
0.06
0.04
0.02
0
0.02
0.04
0.06
0.08
V
Zo
VR
Vs
R
V
Zo2
Vs
R Zo
V
Zo2
Vs
R Zo
V
Vs3 R Zo
R Zo( )2
Zo 1.111
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Find voltage at Rx againThe reflected wave follows a 1/-Zo line. Again the task is to find b. But since we know a V and I above this is easy
IV
Zob b 4 Vs
R
R Zo( )2
Then IV
Zo4 Vs
R
R Zo( )2
when I=0 V 4 VsR
R Zo( )2
Zo I 4 Vs RZo 1
R Zo( )2
at Rx
0 0.4 0.8 1.2 1.6 20.1
0.08
0.06
0.04
0.02
0
0.02
0.04
0.06
0.08V
Zo
VR
Vs
R
V
Zo2
Vs
R Zo
V
Zo2
Vs
R Zo
V
Zo4 Vs
R
R Zo( )2
V
4 VsR
R Zo( )2
Zo 0.556
And so on....
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The non-linear caseBergeron Analysis For Non-Linear I/V
let Vs 1 R 20 Zo 10 V 0 .01 2
Ifct V( )
V
2
5
2
R
Vs
R
Source I-V curve)
IV
Zo First Forward Wave Transmission Line Load Curve
0 0.4 0.8 1.2 1.6 20
0.024
0.048
0.072
0.096
0.12
V
Zo
Ifct V( )
V
GivenI0V0
ZoI0
V0
2
5
2
R
Vs
R
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Use MathCad Solve blocks at Tx
I1
V1
Find I0 V0( ) 2 4.8548445530883573148 10-2
.48548445530883573148
need to choose correct solution, look at graph to pickI1
V1
0.049
0.485
at Tx
Given next line is
Given
I1V1
Zob b1 Find b( ) 9.7096891061767146296 10
-2
b1 0.097
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First Step at the Rxat the axis I2 0
Given
I2V2
Zob1 V2 Find V2( ) .97096891061767146296
0 0.4 0.8 1.2 1.6 20
0.024
0.048
0.072
0.096
0.12
V
Zo
Ifct V( )
V
Zob1
V
V2 0.971at Rx
Reflected line I3 0
Given
I2V2
Zob2 b2 Find b2( ) 9.7096891061767146296 10
-2
I3V3
Zob2
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Assignment:
0 0.4 0.8 1.2 1.6 20
0.024
0.048
0.072
0.096
0.12.12
0
V
Zo
Ifct V( )
V
Zob1
V
Zob2
20 V
Solve for next voltage and current at Rx
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I
V
Vcc
Example: Under-damped Case with Diode
Multiple I/V curves can be overlaid to estimate performance
In this case an ideal diode’s I-V characteristics gives a feel for what to expect
20 ohms
Vcc = 2V
60 ohms
Pull-upI-V curve
DiodeI-V curve
1/Z0
t=0 TD
1V
2TD
2V
3TD 4TD 5TD 6TD
-1/Z0
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Linear vs. Non-linear
The accuracy of a linear approximation can be determined with a Bergeron diagram:
1/Zo
I
NMOS curvePMOS curve
Voltages from thereflections are close to linear approximation
1/Zo
Voltages from thereflections are NOT close to linear approximationI
V
V
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Summary: We now understand
What is a model? Importance of accurate models Types of buffer models IBIS and the portions of an IBIS model How model data is generated How to calculate VOL and VOH from a model On-die termination Package modeling in IBIS Bergeron diagrams