Class D Audio Using the PE29102 · Page 2 of 16 DOC-88118-2 – (11/2018) Application Note 72 Class...

Class D Audio Using the PE29102

Application Note 72

SummaryThe objective of this application note is to provide pSemi customers with a general overview of Class D audio techniques as well as to show how one or two PE29102 gallium nitride field effect transistor (GaN FET) drivers may be used to each drive a pair of GaN FET devices for audio applications.

IntroductionClass D audio amplifiers were first proposed as far back as the 1950s, though it is only relatively recently that their implementation has become increasingly commonplace. Semiconductor technology has finally come of age to meet the performance levels Class D is capable of, many decades after its conception. This is because, until GaN FETs were introduced circa 2008, most metal oxide semiconductor (MOS) devices were either too slow or had finite “on” resistance of an order that limited their uses for high-power, fast and reliable designs. The great benefit of Class D is efficiency, and achieving efficiency requires using switching devices with high specifi-cations in terms of both low loss and switching speed.

In the Class D mode of operation, the transistors are not used in their linear (triode) mode but are used instead as switches: either fully saturated or cut-off. This way, they dissipate very little heat as there is either minimum voltage or minimum current present across each device in either extreme state. The “D” in Class D is sometimes said to stand for “digital”. This is not correct because the operation of the Class D amplifier is based on analog principles, and there is no digital coding of the signal.

Pulse Width Modulation In its basic form, an audio signal is fed into a fast comparator, whose other input is referenced to a free-running, highly linear ramp or triangle waveform of ultrasonic frequency (that is to say, the frequency of the ramp/triangle wave must be at least two times higher than that of the highest frequency in the sampled input audio signal). The comparator samples the audio precisely against the ramp/triangle wave, resulting in an output square wave whose frequency is the same as the carrier but whose pulse width (duty cycle) is modulated by the amplitude of the audio signal. The quality of the pulse width modulation (PWM) depends upon the linearity of the encoding system used. PWM quality is of paramount importance to the degree of audio quality that can be achieved and will limit the performance achievable with the subsequent Class D amplifier.

More sophisticated implementations may be found using delta-sigma modulators and/or pulse density modulation (PDM). In some designs, the PWM high frequency carrier is produced by self-oscillation owing to positive feedback (this self-oscillating Class D amplifier topology is known as “SODA”), yet the audio signal may be further linearized with another negative feedback loop operating in the relatively lower frequency audio band. With the latter approach, the Class D amplifier becomes a self-contained, free-running, high frequency astable multivibrator, nominally resonating at just below 400 kHz. The audio signal is used to modulate this oscillation by injecting it into the oscillator’s integrating feedback node. This technique works very well and is popular in commercial designs as it is also relatively simple and does not require a highly linear, high frequency triangle wave oscillator, which is both difficult and costly to implement. The results are quite respectable and not offensive to the ear, even when operated open loop where total harmonic distortion + noise (THD+N) is typically around <1.5%. THD+N maybe reduced using carefully applied negative feedback, an established technique

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Application Note 72Class D Audio Using the PE29102

which is often used to improve circuit performance by proportionally canceling and reducing non-linearities, by feeding back a proportion of the output signal, mixed out of phase with the input signal.

High FidelityHigh fidelity—or its better-known contraction, “hi-fi”—is a term that generally refers to high-quality reproduction of sound. This term is applicable to sound-reproducing equipment that gives a realistic recreation of the original sound. The human ear is said to be barely able to perceive a distortion level below one percent; since the advent of hi-fi, distortion levels of 0.1 percent have been achievable with good design. This percentage has been advertised as a “very good” level of distortion and, therefore, a benchmark of sorts. Today, we can expect levels an order of magnitude better than this (that is to say, 0.01 percent, which could be said to be “audiophile” quality) provided the other key requirements of a wide, flat frequency response, good transient response, and very low noise are also met and maintained throughout the audio system.

Output Stage Filtering and Audio DemodulationThe output switching devices are driven with a modulated, high frequency square wave. Think of the output devices as being an efficient switch that is behaving as a push-pull power buffer, routing the power supply proportionally into the load. The high switching frequency used in Class D amplifiers with the inherently fast rise times of square waves and resulting harmonic spectra is a potential source of radio frequency interference toward other equipment. There is a particular requirement to suppress radio frequency radiation from entering the loudspeaker cables, which would otherwise act as dipole antennas due to the fast switching. Class D ampli-fiers must also be properly shielded and grounded to prevent radiation of the switching harmonics emerging from the amplifier’s (metal) enclosure; low-pass filters must be used not only on the loudspeaker outputs but also ideally on all input and power connections.

The components used in the low-pass filter (usually a second-order/12 dB per octave type comprising an inductor and at least one capacitor) will have some impact on the audio quality. This is because the audio signal is demodulated (that is to say, recovered) by filtering out the higher frequency square wave “carrier” using the aforementioned filter network, whose electrical characteristics will, to an extent, affect the linearity of the (delib-erately) residual audio signal. The losses in the filter inductor will also affect efficiency, as the inductor is connected in series between the switching transistors and the (low-impedance) load. It is the series resistance of the inductor as well as some inherent iron (magnetic) and copper (heating) losses which contribute to this inefficiency. For this reason and also for improved audio quality purposes, it is not uncommon to see special formulation iron cores or even air cores being used in the inductors with this kind of application. High-quality capacitor dielectrics with low loss and good pulse performance (such as polypropylene) are preferable to further minimize losses in the filter network.

DistortionDistortion must be minimized, and this improvement in linearity is achieved both by reducing the switching dead-time and by using global negative feedback from the analog output right back to the PWM input.

Advantages of Both Class D and GaN FETsAn advantage of Class D circuits is that they are relatively simple to implement with modern components, require simpler power supplies for the full-bridge topology, and have at least double the efficiency of the best linear designs. GaN FETs are preferred as the switching devices because they offer significant advantages over MOSFETs. Because GaN FETs are faster, smaller and do not have a body diode, they have fewer switching losses versus conduction losses, resulting in superior linearity and efficiency.



Full BridgeA fully bridged configuration combines two identical half-bridge channels and, when operating from a unipolar supply, forms a single “floating” bridge-tied load (BTL) output. When operated as a full bridge, the load is tied to the “in phase” half-bridge output at one end and to the “out of phase” half bridge on the other end, referenced to half the unipolar supply voltage. Please note that only with a bipolar power supply (such as mirror-image +ve and –ve rails about ground) is the signal referenced about ground or zero volts. A key advantage of this technique is to increase the output power without having to increase the supply voltage.

The PWM signal modulates toward the positive rail at one end of the load and toward the negative rail at the other end, following the polarity of the PWM input signal. This is a balanced, push-pull arrangement providing full swing to the supply rail limits; a great advantage of full-bridge operation is the full use of the power supply voltage. For a given power supply voltage, the full-bridge/BTL configuration produces double the voltage swing into the load. For the same load impedance, by Ohm’s law it can be shown that four times the power is produced as is proportional to the output voltage squared. While full-bridge BTL operation is possible from a unipolar power supply, it is important to note that neither output terminal must be shorted to the supply positive or ground as there is no DC blocking capacitor; otherwise, short circuit damage can occur to the switching devices. Another way of viewing the difference between full- and half-bridge topologies is to consider that amplifiers with BTL outputs can provide twice the peak-to-peak voltage to the load as a single-ended amplifier. The squared term in Ohm’s law means that the single-ended amplifier can in fact only supply one-fourth (1/4) of the power to the load when compared with the BTL/full bridge.

A problematic phenomenon found in half-bridge configurations is what is referred to as “bus pumping”. This occurs when the stored energy of the load and output filter gets returned to the power supply rails which become temporarily modulated and undergo a variation in supply amplitude when compared with the no signal (quiescent) state.

Full-bridge/BTL mode neatly cancels out this issue, as one output stage is sourcing current while the other is sinking current, with a net result of zero disturbance to the supply rails. Additionally, this mode also offers superior rejection of power supply noise or power supply rejection ratio (PSRR). Disadvantages of the BTL topology are that it requires double the number of active components than for a half bridge in its implementation, plus double the output filter components and their attendant losses. However, these disadvantages are negated by the fourfold increase in available output power and the fact that an unsophisticated and relatively inexpensive power supply may be used and still produce good results. For details, see Figure 3 on page 5.

Shoot-Through and Dead TimeA problem called “shoot-through” can reduce the efficiency of Class D amplifiers and lead to a potential failure of the output devices. This occurs during the transition when one device is being cut off and another is beginning to conduct. During the transition, both devices are on, and a large current pulse can flow through the two. This can be eliminated by driving each device separately with a deliberate asymmetry (that is to say, a small gap) between the square wave edges so that there is a band of “dead-time” between them, thus eliminating the occurrence of shoot-through. This needs to be just enough, but not excessive, otherwise non-linearities can manifest that will have negative consequences for audio in the form of crossover distortion, so it is a trade-off.

Peak Versus Average Power in Audio ProductsAlthough not confined to Class D, manufacturers of audio products are required by various regulatory agencies to specify the average power rather than peak power for consumer audio products. The root-mean-square (RMS) voltage for an undistorted sinusoidal output is equal to the peak voltage divided by the square root of 2, so the maximum average output power for a Class D amplifier with an undistorted sinusoidal output is equal to the peak-to-peak output power divided by 2 x the square root of 2; that is to say, divided by 2.83 approximately.

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Amplifier manufacturers sometimes specify the output power at a higher level of THD in order to allow them to advertise a higher output power. For example, it may be shown that a clipped sinusoidal output waveform with 10% THD has an average output power almost 30% higher than an undistorted sine wave output from the same amplifier.

Determining Average Power Supply RequirementsConsumers rarely require more than 40% power on a continuous basis. Most will operate their amplifiers well below the maximum rated power, with full output only being required for short periods during music peaks. As a guideline, an amplifier for consumer audio use may be rated for continuous operation at one-eighth (1/8) of its full output power; however, the power supply should still be rated to comfortably provide the maximum output current, which is due to the amplifier’s peak output power rather than its (much lower) continuous power capability.

Studio-quality audio has historically aimed for an ideal overload margin (headroom) of 10x or 20 dB within the dynamic range between the average signal level and the threshold of signal clipping. This should be borne in mind when considering both the sound quality and how robust a design should be, when choosing and speci-fying a power supply for any type of audio amplifier.

Figures 1 through 4 refer to an evaluation kit that has a Class D full-bridge output stage using GaN Systems GS61004B GaN FETs driven by pSemi PE29102 drivers.

The PWM input is transistor-transistor logic (TTL) level-compatible, and the recommended maximum supply voltage is 60V. Dead times and overcurrent limit protection are fully adjustable, and various options for config-uring the PWM signal drive and inversion are made possible using jumper links.

Figure 1 • View of the EK29102-03 pSemi / GaN Systems Evaluation Kit



Figure 2 • Block Diagram of the EK29102-03

Figure 3 • Internals and Connectivity of the PE29102 Driver

GateDrive

Regulator

LogicBuffer

PE29102Gate Driver

#1

LogicPhaseSplitter

PE29102Gate Driver

#2

VIN VIN

L1 L2C

L.S.

GND

VSW1 VSW2

RDHL

GND

IN

HSB

VDD

HSGPU

HSGPD

HSSLSB

LSSRDLH

PHCTL

LSGPU

LSGPD

DeadTime

Controller

UVLO LevelShifter

OutputDriver

Logic PhaseControl

LevelShifter

OutputDriver

VDD

VIN

Q1

Q2

VSW

EN



Figure 4 • Schematic of the EK29102-03

OUT-

VCC_6V

PWM_LO

VCC_6V

VCC_6V

HV

VIN

VCC_6V

HV

EN<1>

R39DNI±1%1/4W

C3010uF100V+/-20%

R40 10K±1%1/10W

L1

10uH 20%FDSD0630

L1A10uH ±20%DFEH12060D

D3BAV99-7-F

1

3

2

CR5DFLS2100-7

21

U8PE29102

LSB14

GN

D11

HSB3

RDLH5

ENABLEL7

LSGpu9

PWM8

LSGpd12

PH

CT

L10

LSS13

HSS2

VD

D15

RDHL16

HSGpu6

HSGpd1

NC4

C25 10uF100V +/-20%

R30 1.0±5% 1/20W 0201

R54500K

1

2

3

R44

75K±1%

1/16W

C220.1uF

D2BAV99-7-F

1

3

2

CR71N4003-T

J2TSW-103-07-G-SHDR_TH100_1X3

123

CR4CZRU52C6V2

21

CR6

BAS70LP-7B

2 1

R56DNI0402

R53500K

1

2

3

JP3

PB

C01

DA

AN1

2

R41 4.7+/-5% 1/20W

J7EDZ350/2

12

R55DNI0402

C33 DNI63V 10%

C24 0.1uF100V +/-10%

C290.1uF100V+/-10%

C230.1uF

50V+/-10%

S

D

G

Q4GS61004B

3

2

1

S

D

G

Q3GS61004B

3

2

1

TP65017

TP75017

R32 1.0±5% 1/20W 0201

C27DNI

R380 Jumper

1/10W

CR9DFLS2100-7

21

R42 4.7+/-5% 1/20W

R43

75K±1%

1/16W

EN<1>

HSS<2>

OUT-

PWM_HI

VCC_6V

VCC_6V

VCC_6V

VCC_6V

VCC_6V

VCC_6V

PWM_HI

PWM_LO

HV

VCC_6V

VCC_6V

VIN

HV

EN<1>

TP25017

J101

DNI

CR

8B

ZX

84C

4V7L

T3G

13

U5MM74HC86MTCX

A14

B15

003

016

A213

B02

A01

0211

A310

B39

038

VCC14

B212

GND7

R71225%

1/8W

TP8

5017

J312

R27DNI±1%1/4W

C32 DNI63V 10%

C20

0.22uF 160V+/-5% Radial, Metalized

C14 10uF100V +/-20%

CR3DFLS2100-7

21

J1TSW-103-07-G-SHDR_TH100_1X3

123

R22

75K±1%

1/16W

R51

500K

1

2

3

DS1SML-311UTT86

AC

C12

0.1uF

R26 1.0±5% 1/20W

R310K±1%1/10W

R69DNI0603

R70DNI0603

R602.7K±5%1/8W

R21

0Jumper1/10W

C100.1uF50V+/-10%

S

D

G

Q1GS61004B

3

2

1

C21

0.47uF

R29

10

C90.1uF

CR2CZRU52C6V2

21

R591.8K±5%1/10W0603

CR10DFLS2100-7

21

CR1

BAS70LP-7B

2 1

R52

500K

1

2

3

C15100uF100V+/-20%

JP2

PB

C01

DA

AN1

2

C170.1uF

C13 0.1uF100V +/-10%

C26100uF100V+/-20%

TP35017

TP15017

P1

0022053031

PIN11

PIN22

PIN33

D4BAV99-7-F

1

3

2

R5810k5%1W2512

R723.3K±5%1/10W0603

R50DNI0402

R28 10K±1%1/10W

L2

10uH 20%FDSD0630

C340.047uF

100V10%

U6PE29102

LSB14

GN

D11

HSB3

RDLH5

ENABLEL7

LSGpu9

PWM8

LSGpd12

PH

CT

L10

LSS13

HSS2

VD

D15

RDHL16

HSGpu6

HSGpd1

NC4

J8ED120/2DS

12

D1BAV99-7-F

1

3

2TP45017

C160.33uF

C19DNI

R10 4.7+/-5% 1/20W

S

D

G

Q2GS61004B

3

2

1

R49DNI0402

C11

0.1uFR8 4.7

+/-5% 1/20W

R23

75K±1%

1/16W

GND

VCC

OUT Y

B

A

U9

NC7S08M5X

3

51

2

4

J100112538

BNC

U7UA78M06CKVURG3

OUT3

COM4

IN1

R25 1.0±5% 1/20W

Q7ZXTP2027FTA

1

23

R6810KTC33

1

2

3

J200

PBC04SAAN

PIN11

PIN22

PIN33

PIN44

R610.225%5W

L2ADNI ±20%DFEH12060D

EN<1>

OUT-

HV

OUT+

EN<1>

HSS<1>



The circuit shown in Figure 5 is for a simple, self-oscillating modulator that encodes the incoming audio as a high quality PWM signal, suitable for driving a Class D amplifier.

Figure 5 • Stereo Audio Analogue to Self-Oscillating Digital PWM/FM Circuit



Benefits to Class D

Dealing with DistortionOne of the traditional problems with Class D amplifiers is their high transient intermodulation distortion (TIM), which results in part from the characteristics of silicon MOSFETs, whose switching anomalies, high on-state resistance, and very high stored gate charge make lowering distortion difficult to achieve. To reduce distortion, Class D amplifiers use large amounts of feedback to compensate for this mediocre open-loop performance. However, the feedback introduces TIM that degrades output signal to what has been described as harsh,

colorless, or bland.1

The use of GaN FETs has a large advantage with respect to MOSFETs—in every regard described above—and facilitates a far better open-loop performance. Aside from careful choice in the output low-pass filter (especially the specification of the inductor), the reduction of jitter and dead time in the switching device, as well as carefully applied minimal negative feedback, also play a large part in achieving optimal audio quality.

1.Manz, Barry, “Automotive Applications Drive Class D Audio Amplifier Performance,” http://innovation-destination.com/2018/06/22/automotive-applications-drive-class-d-audio-amplifier-performance/, June 22,2018

Figure 6 • Causes of Distortion

Low Pass FilterModulatation

Audio

IN Output

Dead time & Rise time

Pulse widthconversion error orQuantization error

Switchingparasitics

PSRR

Filterpeaking

PE29102

P=V2/R

Inputs

Output

TON TOFF

TIN

TOUT

DISTORTION

Output

+

VIN



In Figure 7, the PE29102 is simply connected to the GaN FETs by means of small fixed resistors to tailor the on/off parasitics and a bootstrap capacitor for the high-side switching.

Figure 7 • Diagram Showing PE29102 Connectivity with GaN FETs

VIN

HSB

HSGPU

HSGPD

HSS

IN

RDHL

RDLH LSSGND

LSGPD

LSGPU

VDD

VDD

VDD

LSBEN

PHCTL

Signal input IN signal

Constant dead-timeover VCC variations

Resistor adjustable dead-timeallows design to reduce

cross-over distortion



Figure 8 shows that the relationship between the dead-time resistance value and the dead time is linear and easy to set accurately with the aid of an oscilloscope.

GaN FETs switch more cleanly than MOSFETS due to lack of body diode parasitic minimizing jitter and distortion. The jitter range for a Gan FET switched by the PE29102 is impressively narrow, with a low standard deviation figure.

Figure 8 • Diagram Showing PE29102 Dead Time Between HSG and LSG vs. Resistance

Figure 9 • Jitter Graph

0

5

10

15

20

25

0 50 100 150 200 250 300

Dea

d-tim

e be

twee

n H

SG a

nd L

SG (n

s)

Dead-time Resistance (kΩ)

RDLH RDHL



Dead time adjustments preserve the integrity of the underlying signal by not introducing skew.

The following graph shows the relationship of THD+Noise vs. jitter in Class D amplification.2

Figure 10 • PE29102 Adjustable Dead Time Signal Delays with Respect to the Input

2. Source: Kelleci, Burak, Edgar Sanchez-Sinencio, and Aydin Ilker Karsilayan, THD+Noise Estimation in Class-D Amplifiers, 2007 IEEE International Symposium on Circuits and Systems

Figure 11 • THD+Noise vs. Jitter in Class D Amplification

IN

HSG-HSS

LSG-LSS

tIN

tDLH

tHON

tDHL

tLON

1n 10n 100n0.1

1

10

100

Δt (s)

TH

D+

Noi

se (

%)

Spice SimulationCalculation

Fig. 4. THD+Noise vs. Jitter [ Vtri = 1 V, VSP = 0 .5V, Ttri = 1 µs,f in = 1 KHz , f bw = 15 KHz ]



pSemi has collaborated with EAS to produce a daughterboard using EPC2016C GaN FETs and the pSemi PE29102 driver. This plugs into the EAS motherboard (which has a power supply, filtering and DSP PWM encoding on-board). The result is a high quality, powerful stereo audio amplifier with impressive performance.

Figure 12 • EAS Motherboard with Daughterboards Removed

Figure 13 • Modular Daughterboard Using the PE29102 to Drive EPC2016C GaN FETs



.

Figure 14 • EAS Motherboard with Modular Class D Daughterboard Output Stages Fitted for Performance Evaluation



An Audio Precision© AP2700 audio analyzer was used to measure the plots shown in Figure 15 and Figure 16; namely, THD vs. input signal level and output power, and also the noise floor relative to an output level of 100W RMS into an 8Ω load vs. input level. Both plots show open-loop (yellow lines) and closed-loop (cyan lines) performance. These plots were taken from the Elegant Audio Solutions (EAS) Class D amplifier, consisting of the EAS-designed motherboard (power supply, filters and DSP PWM encoder) driving their daughterboard Class D power output stage design built around pSemi PE29102 drivers and EPC2016C GaN FETs

Figure 15 • THD+Noise vs. Level

Closed-loop Response Open-loop Response

dBFS

% W

p



Figure 16 • Noise Floor Relative to 100W RMS into 8Ω

Closed-loop Response Open-loop Response

dBFS

dBr A


Application Note 72 Class D Audio Using the PE29102

ConclusionWe have looked at the principles of Class D audio amplification with particular regard to the benefits of using GaN FET output devices driven by the pSemi PE29102 driver. We have explored the difficulties of producing a sufficiently linear PWM signal to drive a Class D output stage from a standard (linear, analog) audio input signal. We have explored techniques for addressing the attendant non-linearities in the encoding process as well as those found in the Class D circuit, namely distortion and noise, which may be reduced by using negative feedback, whereas jitter, dead time and shoot-through are issues that may be addressed or minimized by careful circuit design and the use of high quality, fast devices. We have also seen how the configuration of the output stage affects power supply requirements. All of these criteria need to be understood, applied and optimized to produce an efficient, reliable and listenable Class D audio amplifier.

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Sales ContactFor additional information, contact Sales at [email protected].

DisclaimersThe information in this document is believed to be reliable. However, pSemi assumes no liability for the use of this information. Use shall be entirelyat the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party. pSemi’sproducts are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support orsustain life, or in any application in which the failure of the pSemi product could create a situation in which personal injury or death might occur.pSemi assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications.

Patent StatementpSemi products are protected under one or more of the following U.S. patents: patents.psemi.com

Copyright and Trademark©2018, pSemi Corporation. All rights reserved. The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registeredtrademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries.

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