Circuits

CRYSTAL OSCILLATOR CIRCUITS

An oscillator circuit requires that two conditions be satis-fied: that it contains an amplifier having sufficient gain toovercome the loss due to its feedback network, and thatthe phase shift around the whole loop is zero at the wantedfrequency. It must be ensured also that the loop gain atother frequencies where the phase shift might be zero, isless than that at the wanted frequency. For example a crys-tal oscillator which is intended to operate at the crystalsthird overtone frequency could do so otherwise at its fun-damental.

When power is first applied to an oscillator the signal am-plitude builds up until it is limited by the non-linearity ofits maintaining amplifier or, by an external level-controlcircuit. In the former case, the limiting method employedby all but high-precision oscillators, the output waveformis therefore dependent upon the type of amplifier and itsmethod of limiting, and the point of signal extraction. Anypoint in the circuit can be chosen to extract the signal aslong as impedance levels are borne in mind. It is importantthat any loading be as light as possible in order to maintaina high circuit Q and, thereby, good short-term stabilityand low phase noise.

The Circuit Condition

Some of the circuits to be illustrated require crystal cali-bration at series resonance, while others require load-resonance calibration with a stated load capacitance value.The appropriate circuit condition must be stated when or-dering crystals or, while they will oscillate, they will not doso at precisely the desired and marked frequency.

Below 150.0kHz

The relatively high equivalent series resistance of crystalsin this frequency range demands a high amplifier gain.This can be provided as shown in Fig.9 by employing twocascaded common emitter bipolar stages. Component val-ues are indicated for frequencies down to 50kHz.

The diodes D1 and D2 in the collector circuit of TR1 limitthe crystal drive level to avoid damage and the tuned cir-cuit in the collector of TR2 adds some selectivity. Thecrystal should be calibrated at load resonance with the midvalue of the trimmer capacitor C2. Series-resonance cali-bration is recommended only if precise frequency trim-ming is not required as only a limited pulling range isafforded by adjustment of L1.

150.0 to 550.0kHz

DT and CT are the usual cuts for conventional crystals inthis frequency range, for which a suitable circuit for thosecalibrated at series resonance is shown in Fig. 10. Thesecuts have a strong mode at about twice the wanted fre-quency which should not cause a problem.

L1, which must be initially adjusted for oscillation nearthe crystal frequency with the crystal shorted, may be usedas a fine frequency trimmer. Series resonance crystal cali-bration should be specified but parallel resonant crystalsmay be used if C1 is replaced by a capacitor whose value is

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R 41 K 5

R 58 2 0

R 61 5 K

T R 2

C 2

R 11 5 K

T R 1

R 24 K 7

R 34 7 0

D 1 D 2R 74 K 7

R 84 7 0

X 1

C 3

L 1R 92 7 0 K

T R 3

R 1 03 3 0

C O M

O / P1 V r m s

+ 6 V

C 63 3 0 n

T R 1 , T R 2 , T R 3 : B C 1 0 8 D 1 , D 2 : 1 N 4 1 4 8 L 1 : 8 0 0 - 2 2 0 m H

C 2 : S e e T e x tC 3 : 1 0 . 0 n F 5 0 - 7 5 k H z 4 . 7 n F 7 5 - 1 0 0 H z 2 . 2 n F 1 0 0 - 1 5 0 k H z

C 1

1 0 n

C 5

1 0 n

C 4

1 0 n

Fig. 9

C 1

L 1

X 1

R 11 0 0 K( 4 7 k )

T R 1

R 32 K 2

R 23 3 K( 5 6 K )

C 3

C 2

R 42 K 2

1 n

+ 9 V

O / P1 V r m s

C 51 0 0 n

C O M

C 4

T R 1 : B C 1 0 8L 1 : 1 5 0 - 3 0 0 k H z 8 0 0 - 2 2 0 0 H 3 0 0 - 5 0 0 k H z 3 6 0 - 9 6 0 H

C 1 : 1 0 n F f o r s e r i e s r e s o n a n c eC 2 & C 3 : 1 n F 1 5 0 - 3 0 0 k H z 6 8 0 p F 3 0 0 - 5 5 0 k H z

Fig. 10

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equal to the crystal load capacitance.

0.95 to 21.0MHz

The circuit shown in Fig.11 is designed for use with highstability AT-cut fundamental mode crystals calibrated atload resonance. Specify 30pF load capacitance 950kHz to10MHz and 20pF for 10 to 21MHz.

15.0 to 105.0MHz

Figs.12 and 13 give circuits suitable for operation with 15to 63MHz third and 50 to 105MHz fifth overtone seriesresonant crystals respectively. A small positive frequencyoffset, +20ppm, will allow a wide trimming range.

When ordering an overtone crystal, reference must not bemade to its fundamental frequency since it is not an exactsub-multiple of the overtone frequency. Overtone crystalsare produced and calibrated specifically for operation attheir marked frequencies.

By including a tuned circuit at twice or three times thecrystal frequency in the collector TR1 of these circuits, it ispossible to extract, from the collector, harmonics of thecrystal frequency. Such an approach offers an easy andeconomical solution to VHF crystal oscillator design.

Above 105.0MHz

The low reactance of stray circuit capacitances at thesehigh frequencies can make a reliable oscillator design diffi-cult to achieve. To help prevent oscillation not controlledby the crystal, the static capacitance Co of the crystal is of-ten tuned out with a small parallel inductance L2 inFig.14. L1 in the circuit is tuned for maximum output butit can also serve a fine frequency trimmer. Alternatively,the frequency can be trimmed by inserting variable reac-tance in series with the crystal.

At these frequencies, it may be necessary to obtain correla-tion of the oscillator frequency with crystal frequency asmeasured by the crystal manufacturer. If high accuracy isrequired therefore, it is important to experiment with asample crystal on which the manufacturers precise fre-quency reading is known. Any discrepancy between thecrystal and oscillator frequencies can then be remedied by


T R 1 : B C 1 0 8

R 3

C 5

O / P0 . 5 V r m s

R 11 0 0 K( 4 7 k )

T R 1

R 23 3 K( 5 6 K )

1 n

+ 9 V( + 5 V )

C 61 0 n

C O M

C 3

C 4

X 1

C 16 0 p C 2

f ( M H z ) R 3 C 2 ( p F ) C 3 ( p F ) C 4 ( p F )0 . 9 5 - 3 3 K 3 n o t u s e d 2 2 0 2 2 0 3 - 6 3 K 3 3 3 1 5 0 1 5 0 6 - 1 0 2 K 2 3 3 1 5 0 1 5 0 1 0 - 1 8 1 K 2 n o t u s e d 1 0 0 1 0 0 1 8 - 2 1 6 8 0 n o t u s e d 6 8 3 3

Fig. 11

R 21 0 K

C 2

C 3

C 4

C 1

R 34 K 7 R 44 7 0

O / P0 . 5 V r m s

T R 1

+ 9 V

C 51 n

C O M

f ( M H z ) C 1 ( p F ) C 2 ( p F ) C 3 ( p F ) C 4 ( p F ) 1 5 - 1 0 1 0 0 1 0 0 6 8 3 3 2 0 - 2 6 1 0 0 1 0 0 6 8 3 3 2 6 - 4 8 1 0 0 6 8 4 7 3 3 4 8 - 6 3 6 8 3 3 1 5 1 5

L 1

X 1R 15 6 0

T R 1 : B C 1 0 8L 1 : 0 . 5 m H - 3 . 0 m H

Fig. 12

R 1

R 24 7 0

L 1

X 1 C 21 8 p

C 11 2 p

T R 1

R 44 7 0

C O M

C 51 n

O / P0 . 3 V r m s

+ 9 V

R 33 3 0C 3

3 3 0 p

T R 1 : B F 1 8 0 R 1 : 2 K 7 5 0 - 8 0 M H zL 1 : 0 . 3 m H - 1 . 5 m H 1 K 2 8 0 - 1 0 5 M H z

Fig. 13

R 13 K 3

R 21 K 2

L 1

C 42 2 p

C 2

C 3

+ 9 V

O / P

L 2X 1T R 1

R 33 3 0

C O M

C 11 n

C 51 n

T R 1 : B F 1 8 0C 2 . C 3 A d j u s t t h e r a t i o t o s u i t 1 1C 2 + C 3 f o l l o w i n g c i r c u i t w 2 . 7 p F w 2 . C o

= 1 0 p F L 1 = L 2 =

Fig. 14

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calling for an offset calibration tolerance for further crystalsupplies.

TTL Clock Oscillators

Many circuits have appeared over the years that use TTLinverters and gates as the active elements. Often, such de-signs are prone to oscillate at unwanted frequencies or, fora variety of reasons, do not operate properly. Even certainintegrated circuits which have been designed specificallyfor the purpose can be troublesome. As a general rule, ex-tensive testing should be done on these circuits to makesure that the design is not marginal and will not result inbelated problems.

Figs.16 to 18 illustrate some possible arrangements foruse with the 7400, 7402, 7404 etc. Unused inputs ofNAND gates should be connected to the positive supplyand those of NOR types, to earth. The approximate fre-quency ranges shown apply only to standard TTL ICs; al-though with higher value bias resistors in Figs.16 and 17,the low power families can be used to advantage. In thesetwo circuits, the value of C1 and C2 if found to be neces-sary, should be determined experimentally. For the fre-quency range 4 to 14MHz, the circuit of Fig.18 will givegood results.

TTL gate circuits cannot be fully recommended if thehighest stability is required. Random phase shift withinthe IC will cause jitter and the relatively high crystal drivelevel does not make for good long-term stability.

A conventional discrete component oscillator such as onealready described, followed by a buffer amplifier providesa better way of obtaining a stable design. A suitable bufferis shown in Fig.15 in which the resistor R2 decouples thesupply to the oscillator. The insert shows a Complimen-tary version of the buffer amplifier which can be used for afaster rise time when feeding capacitive loads. For opera-tion of the circuits of Figs. 10 and 11 from a 5V supply, thevalues for R1 and R2 shown in brackets should be used. Inorder to reduce the output to a level suitable for the logicbuffer, reduce R3 in Fig.9; and increase C3 and C4 inFig.11. For the latter circuit, crystals calibrated for 30pFload capacitance can now be specified for use up to about15MHz.


R 2

R 3 R 4

+ V

O / P

C 11 0 n

C O M

R 11 0 K

T R 2

T R 1I / P

0 . 0 9 - 0 . 2 V r m s

R 1

R 1

R 3

1 2 0

T R 1 : 2 N 3 9 0 6R 3 : T T L : 3 K 3 C M O S : 1 5 kT R 2 : 2 N 2 3 6 9 AR 4 : T T L : 1 k C M O S : 2 K 7R 2 : S e e t e x t

Fig. 15

1 K 8 1 K 8

C 1< 1 M H ZO / P

C 2

Fig. 16

C 1 O / P

C 24 7 04 7 0

Fig. 17

R F C 1 R 1O / P

C 2

C 3

C 1

f 1 ( M H z ) C 1 ( p F ) C 2 ( p F ) R F C 1 ( m H )

4 3 0

6 0 p

4 . 0 - 6 . 0 3 3 0 2 2 0 1 0 0 6 . 0 - 9 . 0 3 3 0 1 8 0 6 8 9 . 0 - 1 1 . 5 2 2 0 1 5 0 3 91 1 . 5 - 1 4 . 0 3 3 0 1 2 0 2 2

Fig. 18

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CMOS Clock Oscillators

Fig.19 shows the circuit of a typical CMOS inverter oscil-lator in which the crystal is connected in a pi-network andoperates at load resonance. Again, only one gate input isconnected to the crystal; unused inputs are tied to the ap-propriate supply rail. Simple formulae for calculating thevalues of Ca, Cb and R are given which will result in a reli-able 4000UB-series design for use up to about 3MHz.However, the actual values used may differ slightly owingto variations in the stray capacitances of individual lay-outs. If frequency trimming is required, a trimmer capaci-tor can be fitted in parallel with Cb and the fixed capacitorreduced accordingly.

If connections to the sources of each FET in the inverterare available, as in a 4007, the resistor value calculated forR may be inserted at these points, the single series resistorbeing no longer used. This arrangement, which is illus-trated in Fig.20 gives better stability than the standardconfiguration due to negative feedback.

For operation above 3MHz, the resistor R is omitted andthe crystal connected directly between the inverter inputand output. The two pi-network capacitors will now havethe same value and their series combination plus invertercapacitances and strays will be equal to CL. Low values ofCL, for example 12pF, and/or a high supply voltage maybe necessary for reliable operation.

If preferred, a discrete component oscillator together withthe logic buffer of Fig.16 can be used. The power con-sumption however will be considerably greater than thatof a CMOS inverter oscillator.

Frequencies 20.0 to 200.0MHz

The schematic of this VHF overtone oscillator is shown inFigs.21 & 22. The crystal operates at its overtone and istapped into the capacitive side of the LC tank circuit. Thecircuit has no parasitic effects of any kind.

There are no 2.6V zener diodes available, so four signal di-odes are cascaded in series for base biasing. The emittersoutput resistance that drives the crystal is 25ohms. Thecrystal load impedance is mostly capacitive and is one ortwo times the impedance of C2 (35ohms), depending on


1 5 MR

O / P

C bC a

Fig. 19

R V d d

C bR

C a

C a = 1 . 1 C LC b = 4 C L R = 1 w . C b

Fig. 20

+ 5 V + 5 V

+ 5 V

R 2 1 k

1 N 5 7 1 1

2 N 5 1 7 9

2 N 5 1 7 9

E o = 0 . 8 V p p

1 0 0

5 1+ 1 . 9 V D C

B

A

R 0 = 2 5

1 m H

100n

L 1

D 5

D 6

2 0 M H z3 r d O v e r t o n e

1N4148

D1- D4

R 11 k

C 17 5 - 8 5 p F

C 24 2 0 p F

R 36 8

Fig. 21

B u t l e r e m i t t e r f o l l o w e r a t 2 0 M H zc a p a c i t a t i v e t a p

E

E

E

E

A

B

0 . 0 1 m i c r o s e c o n d / d i v i s i o n

0 . 2 V / d i v

0 . 2 V / d i v

0 . 2 V / d i v

Fig. 22

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the value of C. The crystals internal series resistance R1 isbetween 30 and 40ohms.

The circuit works very well and the absence of parasitics isa big help. By tuning C, the oscillation frequency can beset either at or slightly above (2ppm) the series resonance.

Figs.23 & 24 show typical values for 50MHz and 100MHzoperation.

Integrated Circuits as Oscillators

A large number of integrated circuits are available for useas an oscillator or include a crystal oscillator. Many exist-ing ICs require only the attachment of an external crystalwhile some require other components as well. There arethree main types of oscillator, the first provides a single bi-polar or field effect transistor to which the external crystaland feedback network can be attached. For this class ofcircuit the designs shown for transistor oscillators are di-rectly applicable and the frequency stability is generallygood.

The second class of circuit, often using MOS technology,provides a gate which can be used as a crystal oscillator.The frequency stability is generally equivalent to that ofoscillators using discrete gates of the same type.

The third class of circuit is designed with a multi-stageamplifier on the chip and the external crystal either closesthe feedback path from the amplifier output to its input orit serves as a frequency-selective by-pass at some point inthe amplifier. Many of these circuits are used as clock driv-ers for microprocessors, as frequency synthesizers, mo-dems, TV circuits, phase-locked loops and the like. Asmight be expected, the frequency stability varies greatlywith the design and while some are good, others are verypoor indeed.

While it is desirable in the design of integrated circuit os-cillators to use a set of analytical tools, the detailed equa-tions for oscillation are generally too complex to be useful.Two approaches are presented here based on the terminalparameters of the integrated circuit. In those circuitswhere the crystal acts as a frequency-selective by-pass inthe amplifier which is internally cross-coupled, it may beconvenient to think of the circuit as a negative-resistiveelement in series with an inductance and a series compen-sating capacitor C in series with the crystal. For on-frequency operation with a series resonant crystal, Cshould be resonant with Lo at the nominal frequency ofthe crystal. The resistance Rn is a negative value and mustbe larger in magnitude than the equivalent resistance ofthe crystal for oscillation to take place.

It is possible to determine the magnitude of Rn in severalways. Perhaps the most obvious is to place a crystal be-tween the appropriate terminals of the IC and add seriesresistance until oscillation will no longer occur. The mag-nitude of the negative resistance is then given by the sumof the crystal resistance and the additional series resis-tance. The magnitude of the oscillator inductance can befound by noting the difference between the frequency ofoscillation and the series resonant frequency of the crystal(without C or the series resistance) and calculating.


+ 5 V + 5 V

+ 5 V

R 2 1 k

1 N 5 7 1 1

2 N 5 1 7 9

2 N 5 1 7 9

E o = 0 . 8 V p p

1 0 0

5 1+ 1 . 9 V D C

B

A

0 . 4 7 m H

100n

L 1

D 6

R 1 = 3 0

Z o = 2 9 5 0 M H z3 r d O v e r t o n e

R 41 k

C 19 - 1 8 p F

C 28 2 p F

1n4148

D1-D4

D 5

R 36 8

Fig. 23

+ 5 V + 5 V

+ 5 V

E 0 = 0 . 8 V p p

1 0 0

5 1+ 1 . 9 V D C

B

A

0 . 2 2 m H

100n

R 1 = 7 0

0 . 4 1 m H

M R F 9 0 4

Z 0 = 2 5

M R F 9 0 4

1 N 4 1 4 8

1 0 0 M H z5 t h O v e r t o n e

R 2 1 k

L 1

D 6

R 41 k

C 19 - 1 8 p F

C 23 3 p F

1n4148

D1-D4

D 5

R 31 0 0

Fig. 24

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It can also be found experimentally by selecting C to ob-tain the series resonant frequency of the crystal. Then:

LC

O

fs

=

1

2 2( )p

Since the equivalent inductance will in general vary as afunction of frequency it should be computed near thenominal frequency of the crystal used.

It is desirable to minimize the equivalent inductance of anoscillator for several reasons. First the equivalent induc-tance of an oscillator will change with temperature andsupply voltage, causing the oscillator frequency to drift.Secondly, it may result in free-running oscillationsthrough Co of the crystal.

The equivalent inductance is a result of phase shift in theamplifier and can be minimized in the design by using asfew stages as possible and by increasing bandwidth of theamplifier. The negative resistance will of course be a func-tion of the gain of the amplifier and the impedance levelwhere the crystal is placed.

Test data on several ICs of the cross-coupled type showsa wide variation in the equivalent inductance, from ap-proximately 1- 2 m H to greater than 250 m H over the fre-quency range from 1 to 20MHz. Therefore, while someICs operate with the crystal near series resonance, othersoperate as much as 1% low in frequency.

Frequencies 1 to 20MHz

The schematic circuit for this series resonant oscillator at1MHz is shown in Fig. 25. The circuit waveforms areshown in Fig.26. This circuit has outstanding perform-ance and works very nicely off a 5V supply. Waveforms atthe crystal are very good. The frequency changes very littlewhen power supply voltage or temperature are changed.The low ECL drive voltage keeps crystal dissipation lowand the low ECL drive resistance RL, which gives verygood frequency stability. The ECL receiver format is welladapted to high frequency oscillator circuits. At high fre-quencies crystals are low impedance devices and ECL cir-cuits can drive low impedance loads down to 50 W easily.Input resistances of ECL circuits are high and they arealso linear over the ECL voltage range. As shown in Fig.26the crystals square wave drive waveform at Pin 3 has adefinite slope during transition between binary states, in-dicating the ECL unit is operating as a linear amplifierduring the transition interval.

Fig.27 shows the circuit at 20MHz. The crystals internalseries resistance R1 is 7W ; the crystals load resistance RL is10W . At 20MHz the ECL receiver has to be able to drive a17W load (R1+RL=12 W ), a very low value. The receiversoutput resistance is controlled by the ECL emitters outputcurrent, which is in turn controlled by the emitters pull-down resistor R3. R3=510 W works well at 1MHz but hasto be decreased to 100 W at 20MHz to get the ECL outputresistance down low enough to provide a reasonable drivewaveform to the crystal.

There are three ECL receivers in one DIP. One of the twounused ones could be used as a no-cost buffer between the


1 M H z

+ 5 V2 7 0

E o ( T T L )

9 1R 35 1 0

R 35 1 0

R 1 = 2 4 0

R L R 4 4 k 7

1 1 62

3

54

8

1 0 0 n

R 2

5 K 1

1 0 1 1 41 0 1 1 6 o r1 0 2 1 6

M P S 6 5 9 5

Q 3Q 2Q 1

B U F F E R

2 0 0

2N 4957(2)

1 0 0 n

+ 5 V

Fig. 25

0 . 5 V / d i v

2 V / d i v

0 . 2 m i c r o s e c o n d s / d i v i s i o n

0 . 5 V / d i v

0 . 5 V / d i v

0 . 5 V / d i v E 3

Fig. 26

+ 5 V 2 7 0

E o ( T T L )

9 1R 35 1 0

1 1 62

3

5

48

1 0 0 n

R 2

5 k 1

Q 3Q 2Q 1

B U F F E R

2 0 0

2N 4957(2)

1 0 0 n

+ 5 V

R L = 1 0 4 . 7 k

R 1 = 7

M P S 5 5 9 5

2 0 M H z

R 31 0 0

1 0 1 1 6o r1 0 2 1 6

Fig. 27

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oscillator and the two transistor buffer, but the circuit willoscillate spuriously when the crystal is removed. Becauseof this the ECL receiver should not be used as a buffer.

Frequencies up to 500kHz (CMOS)

Each inverter in Fig.28 has negative feedback round it toensure that it is biased in the middle of its linear region, sothat oscillation will always start when power is applied.The feedback resistor round the first inverter is dividedinto two series resistors and the centre point is bypassed toground. RL is used as the crystals load resistor and is setequal to or somewhat less than the crystals internal seriesresistance R1. Figs.29 & 30 shows good waveform at thecrystal. The spikes on the crystal sine wave output appearto be due to sharp edges of the crystals square wave drivefeeding through on the crystals shunt terminal capacitanceCO.

The overall performance of this oscillator is average withon/off times of 2.45 m sec to 2.55 m secs. This is due to itsfrequency sensitivity to power supply voltage changes be-ing higher than it should be. This high sensitivity to powersupply voltage changes seems to be characteristic of mostCMOS ICs.


7 4 C 0 4 7 4 C 0 4 7 4 C 0 4E o ( C M O S )

+ 5 V4 7 k

1 0 0 n

1 0 0 n

2 0 0 k H z C r y s t a lR 1 = a p p r o x . 3 k

1 4

67

54321

R L

N o t e : N o t s u i t a b l e f o r m i n i a t u r e c r y s t a l s

Fig. 28

2 V / d i v

2 V / d i v

E

E 3

1

1 . 0 m i c r o s e c o n d / d i v i s i o n

Fig. 29

2 V / d i v

2 V / d i v

E

E 6

4

1 . 0 m i c r o s e c o n d / d i v i s i o n

Fig. 30

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