Circuitos Digitales II The General Computer Architecture The MIPS single-cycle datapath Semana No.8...

Circuitos Digitales IICircuitos Digitales II

The General Computer ArchitectureThe MIPS single-cycle datapath

Semana No.8Semana No.8Semestre 2008-2Semestre 2008-2

Prof. Eugenio DuqueProf. Eugenio [email protected]

Prof. Gustavo PatiñoProf. Gustavo Patiñ[email protected]

Departamento de Ingeniería ElectrónicaDepartamento de Ingeniería Electrónica

Facultad de IngenieríaFacultad de Ingeniería

The General Computer Architecture

An overview of the cpu’s Datapath unit: The single-cycle datapath as an introduction to the

multicycle (pipeline) datapath.

Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia

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General Computer Architecture Having studied numbers, combinational and

sequential logic, and assembly language programming, we begin the study of the overall computer system.


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The ALU or DataPathThe ALU or DataPath


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The Central Processor Unit (CPU)


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The ALU


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The MIPS computer : An example of “Bit-Slicing”

The MIPS 32-bit ALU processing unit is simply an amalgam 0f 32 1-bit processors.


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ALU components


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ALU components (…cont)


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The Program Counter Architecture


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More ALU components


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ALU Arquitecture for Processing


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More ALU components – Data Memory


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The Sign Extender


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Data Bus Connection in a Load Instruction


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Data Bus Connection in a Store Instruction


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Branch Instructions


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Conditional Branch Circuit


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Jump Instruction


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Jump ALU Path


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Combining the Elements to Make a Complete ALU


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Data Buses and ALU Register/Register Functions


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Load/Store Functions (Read or Write)


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Adding the Instruction Fetch Circuit


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Completing ALU Design


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The “Single-Cycle” ALU

What we have accomplished in this “ALU design” is to come up with all the processing hardware necessary to implement the MIPS instruction set.

Note that we have NOT considered the control circuits (that tell the ALU what to do), and will cover those next lecture.

This basic MIPS processor design is referred to as the “single cycle ALU” (or sometimes the “single cycle CPU”). Why is this?

The reason is that this MIPS CPU (more or less the original implementation of the MIPS instructions) is designed so that ANY instruction can be processed in one cycle of the CPU clock.

Lets consider how this “single cycle” CPU works.


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The “Single-Cycle” ALU (…cont)

Consider what happens when the clock “ ticks.” The PC is already updated. The instruction at memory location [PC] is retrieved. [PC] →[PC+4] Instruction is decoded/registers are identified (operands). Register output buses send data into ALU; ALU function is identified. Register data “flows through” the ALU and is processed. (In loads/stores, data memory is accessed for load or store.) The memory or ALU results are stored back in a register, if necessary.

Since the ALU is basically combinational logic, the “ tick” of the clock governs ALU register behavior, which times the process.

A single clock cycle is from rising to rising or falling to falling edge of the clock. Let us use falling to falling as the reference (remember: a master-slave ff’s output changes on the falling edge of the lock).


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Single Cycle Timing


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Single Cycle Timing (…cont)


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ALU Design Summary

Circuitos Digitales II The General Computer Architecture The MIPS single-cycle datapath Semana No.8...

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