Datapath and Control
description
Transcript of Datapath and Control
Datapath and Control
Address Instruction
InstructionMemory
Write Data
Reg Addr
Reg Addr
Reg Addr
Register
File ALU
DataMemory
Address
Write Data
Read DataPC
Read Data
Read Data
The control architecture can be treated as a Moore State Machine, with output depending only on the current state. States change at every clock cycle.
Instructions need different number of cycles (3-5) depending on the number of steps they have.
Some steps are common for all instructions. Example - Instruction Fetch step Also common is Instruction Decode and Register Fetch
step R-type Instruction Execution, Memory Read/Write
Address Computation, Branch Completion, or Jump Completion are different
Memory Read Access, Memory Write Completion or R-type Instruction Completion
Memory Read Completion (Write Back)
Five Instruction Steps
Use PC to get instruction from the memory and put it in the Instruction Register MemoryRead=1, IRWrite=1,
Increment the PC by 4 and put the result back in the PC IorD=0 (to select PC), ALUSrcA=0, ALUSrcB=01, ALUOp=00 (add), PCWrite=1
Can be described succinctly using RTL "Register-Transfer Language“
IR = Memory[PC]; PC = PC + 4;
Step 1: Instruction Fetch
Datapath Activity During Instruction Fetch
Address
Read Data(Instr. or Data)
Memory
PC
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
Write Data
IRM
DR
AB
AL
Uo
ut
SignExtend
Shiftleft 2 ALU
control
Shiftleft 2
ALUOpControl
IRWriteMemtoReg
MemWriteMemRead
IorD
PCWrite
PCWriteCond
RegDstRegWrite
ALUSrcAALUSrcB
zero
PCSource
1
1
1
1
1
10
0
0
0
0
0
2
2
3
4
Instr[5-0]
Instr[25-0]
PC[31-28]
Instr[15-0]
Instr[3
1-2
6]
32
28
Fetch Control Signals Settings
StartInstr Fetch
IorD=0MemRead;IRWrite
ALUSrcA=0ALUsrcB=01
PCSource,ALUOp=00PCWrite
State 0
Don’t know what the instruction is yet, so can only– Read registers rs and rt in case we need them– Compute the branch address in case the instruction is a
branch ALUSrcB=11, ALUOp=00 (add), ALUSrcA=0 (select PC)
RTL:
A = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC +(sign-extend(IR[15-0])<< 2);
We aren't setting any control lines based on the instruction (since we are busy "decoding" it in our control logic)
Step 2: Instruction Decode and Register Fetch
Datapath Activity During Instruction Decode
Address
Read Data(Instr. or Data)
Memory
PC
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
Write Data
IRM
DR
AB
AL
Uo
ut
SignExtend
Shiftleft 2 ALU
control
Shiftleft 2
ALUOpControl
IRWriteMemtoReg
MemWriteMemRead
IorD
PCWrite
PCWriteCond
RegDstRegWrite
ALUSrcAALUSrcB
zero
PCSource
1
1
1
1
1
10
0
0
0
0
0
2
2
3
4
Instr[5-0]
Instr[25-0]
PC[31-28]
Instr[15-0]
Instr[3
1-2
6]
32
28
Decode Control Signals Settings
Unless otherwise assigned
PCWrite,IRWrite, MemWrite,RegWrite=0 others=X
Start
IorD=0MemRead;IRWrite
ALUSrcA=0ALUsrcB=01
PCSource,ALUOp=00PCWrite
Instr Fetch
Decode
ALUSrcA=0ALUsrcB=11ALUOp=00
ALU is performing one of four functions, based on instruction type
Memory reference (lw and sw):
ALUop=00, ALUSrcB=10, ALUSrcA=1
ALUOut = A + sign-extend(IR[15-0]); R-type:
ALUop=10 (use function field), ALUSrcA=1, ALUScrB=00
ALUOut = A op B;
Step 3 (instruction dependent)
Branch:
ALUSrcB=00, ALUSrcA=1, ALUop=01 (force subtraction), PCSource=01 (use ALUout), PCwritecond=1 (in case zero=1)
if (A==B) PC = ALUOut; Jump:
PCWrite=1, PCsource=10
PC = PC[31-28] || (IR[25-0] << 2);
Step 3 (instruction dependent)
Datapath Activity During Instruction Execute
Address
Read Data(Instr. or Data)
Memory
PC
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
Write Data
IRM
DR
AB
AL
Uo
ut
SignExtend
Shiftleft 2 ALU
control
Shiftleft 2
ALUOpControl
IRWriteMemtoReg
MemWriteMemRead
IorD
PCWrite
PCWriteCond
RegDstRegWrite
ALUSrcAALUSrcB
zero
PCSource
1
1
1
1
1
10
0
0
0
0
0
2
2
3
4
Instr[5-0]
Instr[25-0]
PC[31-28]
Instr[15-0]
Instr[3
1-2
6]
32
28
Execute Control Signals Settings
Execute
Start
Instr Fetch
DecodeUnless otherwise assigned
PCWrite,IRWrite, MemWrite,RegWrite=0 others=X
ALUSrcA=0ALUSrcB=11ALUOp=00
PCWriteCond=0
IorD=0MemRead;IRWrite
ALUSrcA=0ALUsrcB=01
PCSource,ALUOp=00PCWrite
(Op = lw or
sw)
ALUSrcA=1ALUSrcB=10ALUOp=00
PCWriteCond=0
(Op = R-
type)
ALUSrcA=1ALUSrcB=00ALUOp=10
PCWriteCond=0
(Op =
beq)
ALUSrcA=1ALUSrcB=00ALUOp=01
PCSource=01PCWriteCond
(Op = j)
PCSource=10PCWrite
Memory reference: MemoryRead=1, IorD=1 MDR = Memory[ALUOut]; -- lw
or MemoryWrite=1, IorD=1 Memory[ALUOut] = B; -- sw R-type instruction completion RegDst=1, RegWrite=1, MemtoReg=0 Reg[IR[15-11]] = ALUOut; Remember, the register write actually takes place at the
end of the cycle on the clock edge
Step 4 (instruction dependent)
Datapath Activity During Memory Access
Address
Read Data(Instr. or Data)
Memory
PC
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
Write Data
IRM
DR
AB
AL
Uo
ut
SignExtend
Shiftleft 2 ALU
control
Shiftleft 2
ALUOpControl
IRWriteMemtoReg
MemWriteMemRead
IorD
PCWrite
PCWriteCond
RegDstRegWrite
ALUSrcAALUSrcB
zero
PCSource
1
1
1
1
1
10
0
0
0
0
0
2
2
3
4
Instr[5-0]
Instr[25-0]
PC[31-28]
Instr[15-0]
Instr[3
1-2
6]
32
28
Memory Access Control Signals Settings
Start
Instr Fetch
Decode
Memory Access
Execute
(Op = R-
type)
(Op =
beq)
(Op = lw or
sw) (Op = j)
(Op = lw)(Op = sw)
Unless otherwise assigned
PCWrite,IRWrite, MemWrite,RegWrite=0 others=X
IorD=0MemRead;IRWrite
ALUSrcA=0ALUsrcB=01
PCSource,ALUOp=00PCWrite
ALUSrcA=0ALUSrcB=11ALUOp=00
PCWriteCond=0
ALUSrcA=1ALUSrcB=10ALUOp=00
PCWriteCond=0
ALUSrcA=1ALUSrcB=00ALUOp=10
PCWriteCond=0
ALUSrcA=1ALUSrcB=00ALUOp=01
PCSource=01PCWriteCond
PCSource=10PCWrite
RegDst=1RegWriteMemtoReg=0
PCWriteCond=0
MemWriteIorD=1
PCWriteCond=0
MemReadIorD=1
PCWriteCond=0
All we have left is the write back into the register file the data just read from memory for lw instruction
RegDst=0, RegWrite=1, MemtoReg=1
Reg[IR[20-16]]= MDR;
Step 5: Memory Read Completion (Write Back)
Datapath Activity During Write Back
Address
Read Data(Instr. or Data)
Memory
PC
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
Write Data
IRM
DR
AB
AL
Uo
ut
SignExtend
Shiftleft 2 ALU
control
Shiftleft 2
ALUOpControl
IRWriteMemtoReg
MemWriteMemRead
IorD
PCWrite
PCWriteCond
RegDstRegWrite
ALUSrcAALUSrcB
zero
PCSource
1
1
1
1
1
10
0
0
0
0
0
2
2
3
4
Instr[5-0]
Instr[25-0]
PC[31-28]
Instr[15-0]
Instr[3
1-2
6]
32
28
Write Back Control Signals Settings
Start
Instr Fetch
Decode
RegDst=0RegWriteMemtoReg=1
Write Back
Memory Access
Execute
(Op = R-
type)
(Op =
beq)
(Op = lw or
sw) (Op = j)
(Op = lw)(Op = sw)
Unless otherwise assigned
PCWrite,IRWrite, MemWrite,RegWrite=0 others=X
IorD=0MemRead;IRWrite
ALUSrcA=0ALUsrcB=01
PCSource,ALUOp=00PCWrite
ALUSrcA=0ALUSrcB=11ALUOp=00
PCWriteCond=0
ALUSrcA=1ALUSrcB=10ALUOp=00
PCWriteCond=0
ALUSrcA=1ALUSrcB=00ALUOp=10
PCWriteCond=0
ALUSrcA=1ALUSrcB=00ALUOp=01
PCSource=01PCWriteCond
PCSource=10PCWrite
RegDst=1RegWriteMemtoReg=0
PCWriteCond=0
MemWriteIorD=1
PCWriteCond=0
MemReadIorD=1
PCWriteCond=0
Step R-type Mem Ref Branch JumpInstr fetch IR = Memory[PC];
PC = PC + 4;
Decode A = Reg[IR[25-21]];B = Reg[IR[20-16]];
ALUOut = PC +(sign-extend(IR[15-0])<< 2);
Execute ALUOut = A op B;
ALUOut = A + sign-
extend (IR[15-0]);
if (A==B) PC =
ALUOut;
PC = PC[31-28] ||(IR[25-0] << 2);
Memory access
Reg[IR[15-11]]
= ALUOut;
MDR = Memory[ALUOut]
; or
Memory[ALUOut] = B;
Write-back Reg[IR[20-16]] = MDR;
RTL Summary
Add addi to the classes of instructions supported - what influence on number of states of the machine?
Instruction fetch and Instruction decode states are unchanged.
ALUout = A+ sign-exte.(IR[15-0])Completion Reg(IR[20-16])=ALUout
Exercise 5.15
Instr FetchIorD=0
MemRead;IRWriteALUSrcA=0ALUsrcB=01
PCSource,ALUOp=00PCWrite
Op = addi Op = addiRegDst=0RegWrite=1ALUOp=00MemtoReg=0
State 12State 0
Decode
ALUSrcA=0ALUSrcB=11ALUOp=00
PCWriteCond=0
State 1
Exercise 5.15 - Cont. The finite state machine with the addition of the state to handle addi
RegDst=0RegWrite=1ALUOp=00MemtoReg=0
State 12
OP: addi
Multi-cycle datapath control signals are not determined solely by the bits in the instruction– e.g., op code bits tell what operation the ALU should
be doing, but not what instruction cycle is to be done next
We’ll use a finite state machine for control– a set of states (current state stored in State Register)– next state function (determined
by current state and the input)– output function (determined by
current state and the input)
Multi-cycle Control
Combinationalcontrol logic
Finite State Machine Implementation
NextStateState Reg
Inputs
Out
puts
Inst[31-26]
Op0
Op1
Op2
Op3
Op4
Op5
PCWritePCWriteCondIorDMemReadMemWriteIRWriteMemtoRegPCSourceALUOpALUSourceBALUSourceARegWriteRegDst
System Clock
We’ll use a Moore machine (control signals based only on current state)
Datapath Control Outputs Truth TableOutputs Input Values (Current State[3-0])
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
PCWrite 1 0 0 0 0 0 0 0 0 1
PCWriteCond X 0 0 0 0 0 0 0 1 X
IorD 0 X X 1 X 1 X X X X
MemRead 1 X X 1 X X X X X X
MemWrite 0 0 0 0 0 1 0 0 0 0
IRWrite 1 0 0 0 0 0 0 0 0 0
MemtoReg X X X X 1 X X 0 X X
PCSource 00 XX XX XX XX XX XX XX 01 10
ALUOp 00 00 00 XX XX XX 10 XX 01 XX
ALUSrcB 01 11 10 XX XX XX 00 XX 00 XX
ALUSrcA 0 0 1 X X X 1 X 1 X
RegWrite 0 0 0 0 1 0 0 1 0 0
RegDst X X X X 0 X X 1 X X
Current State [3-0]
Inst[31-26] (Op[5-0])000000 (R-type)
000010 (jmp)
000100 (beq)
100011 (lw)
101011 (sw)
Any other
0000 0001 0001 0001 0001 0001 0001
0001 0110 1001 1000 0010 0010 illegal
0010 XXXX XXXX XXXX 0011 0101 illegal
0011 XXXX XXXX XXXX 0100 XXXX illegal
0100 XXXX XXXX XXXX 0000 XXXX illegal
0101 XXXX XXXX XXXX XXXX 0000 illegal
0110 0111 XXXX XXXX XXXX XXXX illegal
0111 0000 XXXX XXXX XXXX XXXX illegal
1000 XXXX XXXX 0000 XXXX XXXX illegal
1001 XXXX 0000 XXXX XXXX XXXX illegal
Next State Truth Table