Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing...

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Circuit Level Modeling of Extra CombinationalDelays in SRAM-Based FPGAs Due to

Transient Ionizing RadiationMostafa Darvishi, Student Member, IEEE, Yves Audet, Member, IEEE, Yves Blaquière, Member, IEEE,Claude Thibeault, Senior Member, IEEE, Simon Pichette, Student Member, IEEE, and Fatima Zahra Tazi

Abstract—This paper presents circuit level models that explainthe extra combinational delays in a SRAM-based FPGA (Virtex-5)due to Single Event Upsets (SEUs). Several scenarios of extracombinational delays are simulated based on the circuit architec-ture of the FPGA core, namely Configurable Logic Blocks (CLBs)and routing. It is found that the main delay contribution origi-nates from extra interconnection lines that are unintentionallyconnected to the main circuit path via pass transistors activatedby SEUs. Moreover, longer delay faults observed on Input/OuputBlocks (IOBs) due to SEU were investigated through simulations.In all cases, results are in close agreement with the ones obtainedexperimentally while exposing the FPGA to proton irradiation.

Index Terms—Configurable logic element, extra combinationaldelays, IBIS model, Input/Ouput Blocks (IOBs), observed delaychange (ODC), single event upset (SEU), SRAM-based FPGA.

I. INTRODUCTION

F IELD Programmable Gate Arrays (FPGAs) are semicon-ductor devices that are based around an array of Con-

figurable Logic Blocks (CLBs) connected via a hierarchy ofconfigurable interconnects [1]. FPGAs have become the pre-ferred common solution to implement digital systems targetingdifferent applications [2]. The SRAM-based FPGA comprisessome I/O blocks (IOBs), memory modules, logic blocks androuting resources controlled by SRAM cells, called configura-tion bits [1]. The sensitivity to radiation of SRAM-based FPGAshas been studied over the years [3]–[7]. The first report on extracombinational delays due to transient ionizing radiations wasrecently presented in [8] where their existence due to Single-Event-Upsets (SEUs) induced by proton radiation was experi-mentally observed.

Manuscript received July 11, 2014; revised September 05, 2014; acceptedNovember 05, 2014. This paper was supported by the Natural Sciences andEngineering Research Council of Canada (NSERC), and MITACS.M. Darvishi and Y. Audet are with the Electrical Engineering Depart-

ment, École Polytechnique, Montreal, QC H3C 3A7, Canada (e-mail:[email protected]; [email protected]).Y. Blaquière is with the Computer ScienceDepartment, Université duQuébec

à Montréal, Montreal, QC H3C 3P8, Canada (e-mail: [email protected]).C. Thibeault, S. Pichette, and F. Z. Tazi are with the Electrical Engineering

Department, École de Technologie Supérieure, Montreal, QCH3C 1K3, Canada(e-mail: [email protected]; [email protected];[email protected]).Digital Object Identifier 10.1109/TNS.2014.2369424

The main contribution of this paper is the validation of theroot causes of extra combinatorial delays, also called ObservedDelay Changes (ODCs), on SRAM-based FPGA through circuitlevel simulations of the internal circuitry of Configurable Logicand I/O Blocks [9]–[11] and their interconnections.This paper presents circuit models created to understand and

simulate the source of extra combinational delays experimen-tally observed, which are ranging from 22 ps to as much as422 ps in the core logic of FPGA [8]. To our knowledge, the pro-posed model and methodology represent the first work ever onthe simulation of extra combinational delays due to SEU occur-ring in FPGAs. The models are accurate enough to obtain closecorrelation with the experimental results. The proposedmethod-ology can also be used to predict the probable delay values dueto radiation in any design implemented on FPGA.The effects of SEUs on delay faults affecting the Virtex-5

IOBs were investigated and some substantially larger delaychanges were observed while exposing the FPGA to irradiation[12]. The root cause of these large observed delay changes wasverified in this paper with, circuit level simulations employingthe Input/Output Buffer Information Specification model (IBIS)[13]. FPGA irradiation experiments were also performed at theTRIUMF laboratory using a variable energy and fluence protonbeam [12].This paper is structured as follows. Some background infor-

mation regarding the previous work is presented in Section II.Section III describes FPGA’s circuit level models for observeddelay change root cause validation. Typical circuit-level config-urations that could induce ODCs in the core of SRAM-basedFPGA are presented in Section IV. Simulations of SEU effecton delay faults affecting the Virtex-5 IOBs are presented inSection V. Comparison between simulation results and exper-imental ones observed by proton irradiation for both core-basedand IOB-based Ring Oscillator (RO) circuits are discussed inSection VI, and finally, conclusions are drawn in Section VII.

II. BACKGROUND ON EXTRA COMBINATIONAL DELAYS INSRAM-BASED FPGAS

Configuration memory cells in SRAM-based FPGA are sen-sitive to radiation that causes a bit flip of the stored values[14]–[16]. These SRAMs are mainly used to configure inter-connects, look-up tables and I/O blocks. The two impacts ofa bit-flip on configuration bits related to interconnections areopen, a disappearing link between two nodes; or short, usually

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Fig. 1. Experimental setup at TRIUMF to measure extra delays in FPGA.

defined as an undesired connection between two routed signals.While SEU can modify logic behavior in SRAM-based FPGA,it was conjectured in [8] that delays could be induced by a shortbetween a routed path and an unused wire.Fig. 1 illustrates the experimental setup that was utilized at

the TRIUMF laboratory to demonstrate the induced extra de-lays in SRAM-based FPGA. Extra combinational delays wereobserved while the board was bombarded by protons of energyranging from 35.4MeV to 105MeV for several runs. The XilinxVirtex-5 FPGA (XC5VLX50T) was used to implement two ringoscillators, RO1 and RO2, made of look-up tables (LUTs) con-figured as inverters in the core of Virtex-5 operating at sim-ilar frequencies. The output of each ring oscillator was con-nected to an external inverter (7404). The outputs of the two7404 inverters were shorted by a k resistor while one in-verter output is monitored by a spectrum analyzer. The resistiveshorted outputs provide a signal with a frequency spectrum con-taining the frequency difference between the two RO frequen-cies ( ). This difference is mainly due to the parametervariation in fabrication process and slight difference in the os-cillator’s routing. The measurement of the frequency difference( ) instead of the individual frequency or , led to abetter resolution. The ring oscillators were adjusted to the lengthof 1799 inverters giving MHz and a frequencydifference of about 12.4 kHz. The supply voltage ( ) for in-verter chip (7404) was 1.2 V, while the supply voltage for thecore and the inputs/outputs of the FPGA was 1.0 V and 3.3 Vrespectively. Other experiments were performedwith ring oscil-lators implemented in IOB and will be described in Section V.

III. FPGA CIRCUIT-LEVEL MODELS FOR ODC ROOT CAUSEVALIDATION

A set of 48 experiments were performed in [8] with the protonsource bombarding the top side of the FPGA. Each delay mea-surement was stopped when the oscillation of one RO ceaseddue to a functional failure triggered by an SEU. Twenty threeof those experiments came with one or cumulative ODCs. Thedelay change could produce either a reduction or an increase ofthe measured frequency difference depending on which of thetwo ring oscillators was affected.

Fig. 2. Model of a two configurations of slice to slice interconnection inVirtex-5.

A. Circuit Level Models

One contribution of this paper is to present circuit levelmodels of the FPGA that takes into account the CLB along withtheir interconnection modules in order to simulate SEU induceddelays. The Virtex-5 is based on an array of configurable logicblocks with 2 slices each [1]. The circuit is modeled as a twodimensional array comprising slices and switch boxes/switchmatrices (SB) interconnected by a network of routing wires asshown in Fig. 2. Xilinx does not formally provide any detailon internal Virtex-5 FPGA circuitries. However according to[9], [10], SBs are made of an array of nMOS pass transistorswith some vertical and horizontal interconnects inside. A sliceincludes a Configurable Logic Element (CLE) and 8:1 inputmultiplexers (IMUX). Also, the CLE is comprised of a LUT[17].Fig. 2 presents the top level view of two adjacent CLBs,

where two different configurations of slice-to-slice inter-connection are shown as examples. The first configuration,path A-to-B, is introduced to simulate the behavior of directslice-to-slice link of the ring oscillator (RO) between two adja-cent CLBs. The second configuration, path C-to-A, representsthe other possible interconnection between two slices in a sameCLB. Both configurations are reported by the Xilinx FPGAEditor tool [18]. In the first configuration, the CLB-to-CLBinterconnection length, , is longer than the Slice-to-SBinterconnection length, , in the second configuration. Theseconfigurations are introduced as models for ring oscillatorsimplemented on FPGA enabling the prediction of the probableODCs.

B. Model Configuration Tuning

Fig. 3 represents our circuit model for the main switch matrixstructure used by ROs, as reported by the Xilinx FPGA Editortool. The model includes the location of pass transistors (PIP)and the Pass-transistor to Pass-transistor interconnection, ,(bounce model) for nodes C-to-A configuration of Fig. 2.A signal crosses the switch box SB from their input to output

pins (circles in Fig. 3) via vertical and horizontal interconnectsand through Programmable Interconnection Point (PIP) made ofpass transistors. Indeed, based on the Xilinx FPGA Editor tool,an input signal can be routed directly to one or more output pins


DARVISHI et al.: CIRCUIT LEVEL MODELING OF EXTRA COMBINATIONAL DELAYS IN SRAM-BASED FPGAs 3

Fig. 3. Switch matrix structure reported by Xilinx FPGA Editor including ourequivalent circuit for the second configuration.

Fig. 4. Structure of slice-to-slice interconnection (a) between two adjacentCLBs, (b) in a single CLB.

through a single PIP, named direct route. Also, it is possible tobounce the input signal indirectly through an intermediate inter-connect and PIP and then fed to an output pin, named indirectbounced route. Two bounced routes are shown in Fig. 3. An in-direct bounced route would be typically used for a C-to-A routewhile a direct bounced route is used for A-to-B configurationshown in Fig. 2.The circuit models employed to simulate both interconnect

configurations of the RO implementation used in the experi-ments are detailed in Fig. 4(a) (path A-to-B) and Fig. 4(b) (pathC-to-A), respectively. A signal shaping filter comprised of fourinverters generates a realistic pulse signal waveform. Accordingto Fig. 4(a), any interconnection between two slices located intwo adjacent CLBs has to pass through two switch boxes withan interconnection length of . In Fig. 4(b), the interconnec-tion between two slices located in a same CLB passes through aswitch box with two interconnections of length . The switchbox is comprised of an array of pass transistors and very shortinterconnections shown as in Fig. 4(b). Our simulationsshow that the effect of on propagation delays is negligiblecompared to the one of a pass transistor along the path.The proposed models have been adjusted to match the delay

extracted from the Xilinx ISE Static Timing Analysis (STA-

Fig. 5. Delay variation as a function of short interconnection length for theconfigurations used to define in Fig. 4(a) and in Fig. 4(b).

TRACE) tool [19] run on the place and route netlist and used forthe proton irradiation experiments. Simulations were performedwith Cadence Spectre circuit simulator [20] having the intercon-nect lengths and configured as the sweeping variablesfor both configurations using the Taiwan Semiconductor Man-ufacturing Company (TSMC) 1.2 V 65 nm CMOS technology[21], similar to the 65 nm triple-oxide technology node used tobuild Xilinx Virtex-5 FPGA. Simulations were performed withminimum size transistors and the metal3 layer for interconnects.Fig. 5 presents the propagation delay results from Slice-to-SB

(node C to node A) and Slice-to-Slice (node A to node B) as afunction of the interconnection length to adjust and inthe first and second configurations. We found that an intercon-nection length of m in the second configuration(node C to node A) matches the inverter and net delay of 138 psthat was extracted by Xilinx STA-TRACE. The same procedurewas performed to match the value of in the first configura-tion (node A to node B) and the corresponding value amounts to

m, which matches the net delay of 484 ps. Our simulationresults showed that the effect of on the delay is negligiblecompared to PIP’s effect, so its value was neglected. As shownin the following section, the adjusted lengths and andour circuit models provided sufficient accuracy to reproduce theODCs observed experimentally.

IV. CIRCUIT LEVEL CONFIGURATIONS INDUCING ODCS INFPGA CORE

An SEU in SRAM-based FPGA can affect a configured cir-cuit by creating a short, an open or a modification in the prop-agation delay. Indeed, it is assumed in this paper as in [8] thatthe experimentally observed delay change is caused by an SEUthat increases the interconnect load parasitic capacitance. Underthese circumstances, three circuit scenarios of delay changeswere investigated, as explained in the following:Models for Delay Change Due to Extra Parasitic Intercon-

nects: An SEU affecting an SRAM-cell controlling a PIP (Pro-grammable Interconnection Point) could create a short, for ex-ample, between a vertical line and the main horizontal routingline, as shown in the simplified schematic view of Fig. 6(a). This



Fig. 6. Effect of an SEU on a Programmable Interconnection Point (PIP) inSB, adding a combinational delay: (a) 1 ODC case (1 SEU), (b) 2 ODC case (2SEUs).

model is valid for both inter-slice routing configurations pre-sented in Fig. 3. According to our simulation results, the maincontributor to the delay is the PIP pass-transistor that is turned‘on’ and increases the parasitic capacitance by connecting anundesired vertical unused interconnection to the main routingpath.While Fig. 6(a) is an example of a single interconnect para-

sitic (1-SEU case), Fig. 6(b) shows that cumulative SEUs cancreate larger parasitic load than the 1-SEU case on the mainrouting path. In Fig. 6(b), it is assumed that a primary SEU af-fected the configuration bit of the SRAM-cell and turned on thecorresponding PIP pass transistor and made a permanent con-nection between one horizontal and one vertical interconnectthat are not yet connected to the main routing path. The extra ca-pacitance is added on the main routing path when another SEUflips the configuration bit of the SRAM-cell that connects the

Fig. 7. A sequence of three SEUs connecting three interconnects of length1 to the main routing path.

Fig. 8. Examples of various interconnection lengths in Virtex-5 FPGA [11],[22].

two former parasitic lines to the main routing path and there-fore creates an extra parasitic delay.Fig. 7 illustrates a 3-SEU case where an even larger combina-

tional delay is created by a sequence of three consecutive SEUs.The first two SEUs enabled and , and then anotherSEU activated to create a combinational delay larger thanthe one observed in the 2-SEU case.It is noticeable that the presented structures can be applied

for both configurations introduced in Fig. 3. In our convention,for the configuration presented in Fig. 4(b), the (1) case wassimulated, which means 1 SEU has shorted a parasitic intercon-nect to the main routing path while its length is 1 . The (1),(2) and (4) cases were simulated for the configuration presentedin Fig. 4(a), while an SEU has connected a parasitic intercon-nect to the main routing path with the lengths of 1 , 2or 4 , respectively. Notice that regarding the probable inter-connection lengths in Virtex-5, direct CLB-CLB connections inVirtex-5 FPGA can be 1 , 2 or 4 [11], [22], asshown in Fig. 8. More scenarios have been simulated for theconfiguration of Fig. 4(a) that includes 2-SEU and 3-SEU cases.The nomenclatures of (1,1), (1,2), (1,4), (2,1), (2,2), (2,4), (4,1),(4,2) and (4,4) are defined while the main routing path is af-fected by 2 SEUs. For instance, the case (1,1) identifies a cumu-lative case where two parasitic interconnects with the length of1 due to two consecutive SEUs are connected to the mainrouting path as shown in Fig. 6(b). Also, the case (1,2) impliestwo parasitic interconnects with the length of 1 and 2respectively connected to the main routing path. The case (4,4)represents two parasitic interconnects both with the length of 4

linked to the main routing path.



Fig. 9. Mechanism of delay change creation in IMUX circuit.

In addition, different scenarios were simulated for a sequenceof three SEUs where the equivalent of three interconnects oflengths (1, 2 or 4) become connected to the main routingpath between two slices located in two adjacent CLBs. The pro-posed nomenclatures for the sequence of three SEUs are as thefollowing: (1,1,1), (1,1,2), (1,1,4), (1,2,1),…, (4,4,4) for a totalamount of 27 cases. For instance, the (1,1,1) case introduces thecase where three parasitic interconnects due to three consecu-tive SEUs are connected to the main routing path, while theirlength equals to 1 , as illustrated in Fig. 7. Notice that thedelay change created by the (4,4,4) case is quite larger than thedelay change due to (1,1,1) case. It is noticeable that the hori-zontal interconnect length for both configurations presented inFig. 4 is the unit length that is kept constant at mor m.Models for Delay Change due to SEU Effect on IMUX: As

stated in Section III, the IMUX circuit couples the input ter-minals of CLE to the general interconnect. The assumption fordelay change due to pass transistors in IMUX is illustrated withthe example in Fig. 9. In this case, the main routing path passesthrough pass transistors M1 and M2 while M4 is off and its con-figuration bit is ‘0’.Once an SEU affects the configuration bit of the SRAM-cell

MC2 that controls the pass transistor M4, it creates a bit flip thatmakes M4 ‘on’. Since M3 was previously driven by activatedconfiguration bit MC0, a parasitic path (dotted) is created viaM1, M2, M4 and M3 back to the general interconnect that isassumed to be . This SEU on MC2 produced a noticeabledelay change of 26 ps found by our circuit level simulation.Models for Delay Change Due to Extra Stuck-at Parasitic

Interconnect: Furthermore, another phenomenon observedin FPGA is caused by an extra parasitic interconnect that isstuck-at logic state ‘0’ or ‘1’ [23], [24]. This situation canoccur when a logic node is tied to a specific logic value (by

Fig. 10. Extra stuck-at parasitic interconnect.

Fig. 11. Delay change mechanism in ring oscillator by additional cross linesstuck at ‘0’ or ‘1’ induced by SEU.

the synthesis tool or the designer). Indeed, examinations ofsome XDL files describing existing routed designs revealedthat the tied specific logic value could pass through up to 5 PIPsbefore reaching its final destination. On a main routing path,this parasitic stuck-at interconnect can create a stuck-at faultor induce an extra combinational delay. This phenomenon isshown in Fig. 10. The stuck-at fault or extra combination delayeffect mainly depends on the number of PIPs between the mainrouting path and the parasitic stuck-at interconnect. Section VIpresents the simulation results that demonstrate these twoeffects. It shows that there exists a threshold on the number ofPIPs that generates a delay instead of a stuck-at fault.Assume a ring oscillator implemented in an FPGA as shown

in Fig. 11. An SEU can affect the SRAM-cell that controlsthe pass transistor linking a parasitic interconnect to the mainrouting path between two consecutive inverters. Under somecircumstances, the end of parasitic line could be stuck at ‘0’or ‘1’; and may produce a delay change in the main routingpath that would change the frequency of the ring oscillator orwould cease the oscillation. Our circuit model started with onecross line added into the main routing path via a pass transistorenabled by an SEU, while the end of the line was stuck at ‘0’or at ‘1’. This additional cross line broke the ring oscillatorfor both cases. Then for both cases, additional lines with passtransistors were added in series of the first one until the ringoscillator started ringing.Simulation results obtained with these 3models are compared

to bombardment results in Section V.



Fig. 12. Histogram of measured delays at TRIUMF [8] and simulated delaysfor the ring oscillators implemented in the core of FPGA.

TABLE ISIMULATED CONFIGURATIONS THAT PROVIDED THE RESULTS IN FIG. 12

V. COMPARISON OF SIMULATED AND MEASURED DELAYS

Delay fault results in Virtex-5 FPGA core: Circuit-level sim-ulations of ODCs were performed for the three proposed sce-narios presented in Section IV and illustrated in Fig. 6, 7, 9and 10 for a total of three different scenarios. The simulated de-lays correlate fairly well with the ODCs measured at TRIUMF.The histogram of Fig. 12 shows all the delay changes observedduring all the experiments at TRIUMF. In the case where morethan one ODC was observed during an experiment; each indi-vidual ODC was measured independently and included in thehistogram.The number on top of each bin in Fig. 12 refers to number

of configurations that provide a delay change within the delayspan represented by bin as listed in Table I. Notice also thatthe index ‘2nd’ stated in Table I corresponds to the second con-figuration shown in Fig. 4(b) that connects a parasitic intercon-nect to the main routing path while its length could be 1 .

Recall that 1 represents the unit length extracted whentuning our model for the first configuration in Section III, equalto m. The three introduced scenarios in Section IV due toExtra Parasitic Interconnects were simulated according to thepossible interconnection lengths defined in Fig. 8.For example, a simulation delay of 39.2 ps was obtained with

the 1 ODC case (1-SEU) shown in Fig. 6(a), which is stated inas the configuration (1) in bin number of Table I. This valueis a close match with the 38 ps measured value at TRIUMF.Regarding the delay change due to SEU effect on IMUX cir-

cuit (defined in Sec. IV B) in bin , a small simulation delaychange of 25.8 ps was observed.In the case of extra stuck-at parasitic interconnects

(Sec. IV-C), our simulations for the stuck at ‘0’ case showedthat the first four cross lines break the ring oscillator while witha fifth line, the ring oscillator started ringing and produced adelay change of 148.9 ps, as reported in bin . For the stuckat ‘1’ case, the first eight cross lines stopped the oscillation ofthe ring oscillator while with the ninth one, the ring oscillatorwas functional and produced a delay change of 135.2 ps asreported in bin . These results are explained by the fact thatan nMOS pass transistor is able to pass a ‘0’ better that a ‘1’ inits ‘on’ state.The histogram of the simulated ODCs shows a trend indi-

cating that the most probable delay changes are ranging from40 ps to 100 ps, as observed also experimentally at TRIUMF. Itconfirms that the proposed scenarios and configurations for sim-ulation were sufficient to detect those delay changes and conse-quently the histogram of simulated results is in good agreementwith the experimental one.Delay Fault Results in Virtex-5 FPGA IOB: This section

investigates the delay faults affecting I/O blocks (IOBs) ofVirtex-5 FPGA due to transient ionizing radiation [12]. Theexperimental setup is the same as shown in Fig. 1 but thetwo ring oscillators are made of IOBs rather than LUT in-verters in the FPGA core as shown in Fig. 13. The two ROsoscillate at slightly different frequencies, kHz and

kHz. The first ring oscillator occupies 179 IOBs con-figured as a long delay chain connected to one inverter, whilethe second one occupies 160 IOBs with one inverter. Overall,the two ring oscillators occupy 71% of the 480 available IOBsin Virtex-5 with FF1136 package [25].The FPGA including the implemented design was bombarded

with proton source irradiation under different energy levels (63,50 and 35 MeV). On some experiments, the one RO oscillationceased before observing any delay change. The experimentalresults [12] clearly provided larger delay changes than thoseobtained with RO in the FPGA core (Section II). Our hypothesisbehind the origin of these large delay changes is that an SEUevent modifies the drive and/or the buffer standard of IOBs. Thebias voltage for FPGA IOBs was 3.3 V.To validate this hypothesis, SPICE simulations were per-

formed with the Input/Output Buffer Information Specification(IBIS) models [13] extracted from Xilinx ISE tool. IBISmodels are generally used to perform various board level signalintegrity simulations and timing analysis especially for highspeed signals.



Fig. 13. Implementation of two ring oscillators created by Virtex-5 IOBs.

Fig. 14. Histogram of measured delays at TRIUMF [12] and simulated de-lays for the ring oscillators implemented inside the FPGA utilizing the Virtex-5IOBs.

For each IBIS model simulation, the difference betweentwo consecutive rise times/fall times of the output signal withthe ones of the 12 mA LVCMOS25 I/O standard was mea-sured while changing the I/O standard and/or drive strengthof intended IOBs in the ROs. Each measurement was alsoperformed for Maximum, Typical and Minimum cases of theintended output signal while the measurement threshold levels,called and in the IBIS model, were varied accordingto each I/O standard. These Max, Typ and Min output voltagestake into account the worst cases and typical combinations ofvarying temperature, voltage and process population sample[13].The histograms of experimental and simulation results cor-

responding to delay faults affecting IOBs of the Virtex-5 FPGAare shown in Fig. 14. It is worth mentioning that some largedelay values in the range of nano-seconds (2.3 nsec to 3.9 nsec)that would appear as outliers on the histogram were measuredand also obtained by simulations. These longer delay values

have been created by some I/O standards such as LVTTL,LVCMOS18, LVCMOS33 and PCI.All the measured delays at TRIUMF were divided into single

ODCs. Note that there was also a 6.2 nsec observed at TRIUMF.This particular case is still under investigation in order to repro-duce it through simulations.The simulation results employing the SPICE IBIS model are

also presented and show a good agreement with experimentalresults, which indicates the usefulness of the IBISmodel to eval-uate delay change due to irradiation affecting the IOBs. Indeed,the simulation results show a trend for the most probable delaychanges while bombarding the board with proton source. Thistrend is similar to delay changes trend observed experimentallywhich supports the hypothesis of I/O standard change due toproton irradiation.Notice that the blank bins observed on the simulation his-

togram correspond to blank bins on the experimental histogramas well, whereas the other experimental blank bins are mostlikely due to delay configurations having a low probability ofoccurrence and have not been observed since the limited amountof 97 measured ODCs.

VI. CONCLUSION

This paper presents results supporting the assumption thatextra combinational delays in SRAM FPGAs due to radiationsare caused by bit flip of SRAM-cells configuring FPGA inter-connections and switch boxes. The simulation results are closelycorrelated to those observed during proton irradiation experi-ments. Several delay causing scenarios have been simulated.Regarding delay changes affecting the I/O blocks of Virtex-5

FPGA, an experimental setup was also tested at TRIUMF in-cluding two ring oscillators inside the FPGA created directly inthe IOBs.The hypothesis of I/O standard alteration while bombarding

the FPGA board performed in [12] was verified through cir-cuit level simulations. IBIS models of I/O blocks were used tocompare delays of the primarily implemented design to that ofsupported I/O standards and drive strengths in Xilinx Virtex-5FPGA. Each measurement was performed for Maximum, Typ-ical andMinimum levels of the intended output signal. The sim-ulation results are in good agreement with the ones obtained atTRIUMFwhich supports the I/O standard alteration hypothesis.

ACKNOWLEDGMENT

The authors would like to thank CMC Microsystems forproviding tools and technologies used for this project.

REFERENCES

[1] Virtex-5 Family Overview Feb. 2009, DS100 (ver. 5.0), Xilinx.[2] J. J. Rodriguez-Andina, M. J. Moure, and M. D. Valdes, “Features,

design tools, and application domains of FPGAs,” IEEE Trans. Ind.Electron., vol. 54, no. 4, pp. 1810–1823, Aug. 2007.

[3] A. Lesea, S. Drimer, J. J. Fabula, C. Carmichael, and P. Alfke, “Therosetta experiment: Atmospheric soft error rate testing in differing tech-nology FPGAs,” IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp.317–328, Sep. 2005.



[4] H. Helstrup, V. Lindenstruth, S. Martens, L. Musa, J. Nystrand, E.Olsen, and D. Röhrich, “Irradiation tests of the ALTERA SRAM basedFPGA and fault tolerant design concepts,” in Proc. 9th Workshop Elec-tron. for LHC Experiments, Amsterdam, The Netherlands, 2003.

[5] P. S. Ostler, M. P. Caffrey, D. S. Gibelyou, P. S. Graham, K. S. Morgan,B. H. Pratt, H. M. Quinn, and M. J. Wirthlin, “SRAM FPGA reliabilityanalysis for harsh radiation environments,” IEEE Trans. Nucl. Sci., vol.56, no. 6, pp. 3519–3526, Dec. 2009.

[6] P. Bernardi, M. S. Reorda, L. Sterpone, and M. Violante, “On the eval-uation of SEUs sensitiveness in SRAM-based FPGAs,” in Proc. 10thIEEE Int. On-Line Testing Symp, 2004, pp. 115–120.

[7] M. Alderighi, F. Casini, S. D’Angelo, A. Gravina, V. Liberali, M.Mancini, P. Musazzi, S. Pastore, M. Sassi, and G. Sorrenti, “A prelim-inary study about SEU effects on programmable interconnections ofSRAM-based FPGAs,” J. Electron. Test., vol. 29, no. 3, pp. 341–350,Jun. 2013.

[8] C. Thibeault, S. Pichette, Y. Audet, Y. Savaria, H. Rufenacht, E.Gloutnay, Y. Blaquiere, F. Moupfouma, and N. Batani, “On extracombinational delays in SRAM FPGAs due to transient ionizingradiations,” IEEE Trans. Nucl. Sci., vol. 59, no. 6, pp. 2959–2965,Dec. 2012.

[9] S. P. Young, K. Chaudhary, and T. J. Bauer, “Interconnect structure fora programmable logic device,” U.S. Patent 6 448 808, Sep. 10, 2002.

[10] S. P. Young, T. J. Bauer, M. Chirania, and V. M. Kondapalli, “Pro-grammable logic block with dedicated and selectable lookup table out-puts coupled to general interconnect structure,” U.S. Patent 7 375 552,May. 20, 2008.

[11] M. Chirania and V. M. Kondapalli, “Lookup table circuit optionallyconfigurable as two or more smaller lookup tables with independentinputs,” U.S. Patent 6 998 872, Feb. 14, 2006.

[12] F. Z. Tazi, C. Thibeault, Y. Savaria, S. Pichette, and Y. Audet, “Onextra delays affecting I/O blocks of SRAM FPGAs due to transientionizing radiations,” presented at the RADECS Conf., 2014 [Online].Available: http://arxiv.org/abs/1409.0736

[13] IBIS Open Forum, 1995-2014 [Online]. Available: http://www.vhdl.org/ibis/, Oct. 21, 2014

[14] M. Ceschia,M. Violante,M. S. Reorda, A. Paccagnella, P. Bernardi,M.Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, and A. Candelori,“Identification and classification of single-event upsets in the configu-ration memory of SRAM-based FPGAs,” IEEE Trans. Nucl. Sci., vol.50, no. 6, pp. 2088–2094, Dec. 2003.

[15] M. Wirthlin, E. Johnson, and N. Rollins, “The reliability of FPGAcircuit designs in the presence of radiation induced configuration up-sets,” in Proc. IEEE Symp. Field-Programmable Custom ComputingMachines, Napa, CA, USA, Apr. 2003, pp. 133–142.

[16] H. Asadi, M. B. Tahoori, B. Mullins, D. Kaeli, and K. Granlund, “Softerror susceptibility analysis of sram-based fpgas in high-performanceinformation systems,” IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp.2714–2726, Dec. 2007.

[17] P. B. Minev and V. S. Kukenska, “The virtex-5 routing and logic ar-chitecture,” Annu. J. Electron., vol. 3, pp. 107–110, 2009, TechnicalUniversity of Sofia.

[18] FPGA Editor Guide, Xilinx Inc., San Jose, CA, USA [Online].Available: http://www.xilinx.com/support/sw_manuals/2_1i/down-load/fpedit.pdf, Oct. 21, 2014

[19] Timing Analyzer Guide Xilinx Inc., San Jose, CA, USA [Online].Available: http://www.xilinx.com/support/sw_manuals/2_1i/down-load/timing.pdf, Oct. 21, 2014

[20] Spectre Circuit Simulator, Cadence Inc., Staunton, VA, USA [On-line]. Available: http://www.cadence.com/products/cic/spectre_cir-cuit/pages/default.aspx, Oct. 21, 2014

[21] TSMC Ltd., 65 nm Technology Hu, Taiwan [Online]. Available:http://www.tsmc.com/english/dedicatedFoundry/technology/65nm.htm, Oct. 21, 2014

[22] Virtex-5 FPGA Configuration Users Guide, Oct. 2012, ver. 3.11,Xilinx, UG191.

[23] Virtex-5 FPGA User Guide, Mar. 2012, ver. 5.4, Xilinx, UG190.[24] M. Węgrzyn and J. Sosnowski, “Tracing fault effects in FPGA sys-

tems,” Int. J. Electron. Telecommun., vol. 60, no. 1, pp. 103–108, 2014.[25] Virtex-5 FPGA Packaging and Pinout Specification, Jun. 2012, ver.

4.8.1, Xilinx, UG195.

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