Chapter 8 VLSI Design Methods
Transcript of Chapter 8 VLSI Design Methods
Chapter 8 VLSI Design Methods
Jin-Fu Li
Department of Electrical Engineering
National Central University
Jungli, Taiwan
2Jin-Fu Li, EE. NCUFall, 2004
Outline
• Introduction
• VLSI Design Flows & Design Verification
• Design Strategies
• VLSI Design Styles
• System-on-Chip Design
3Jin-Fu Li, EE. NCUFall, 2004
Trend of IC Complexity
4Jin-Fu Li, EE. NCUFall, 2004
Complexity & Productivity Growth
Complexity and Productivity Growth
10
100
1,000
10,000
100,000
1,000,000
10,000,000
1980 1985 1990 1995 2000 2005 2010
Com
plex
ityTr
ansi
stor
s pe
r Chi
p (K
)
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Prod
uctiv
ityTr
ansi
stor
s/St
aff M
onth
Complexity
Productivity
[Source: MITRE]
Complexity grows 58%/yr (doubles every 18 mos)Productivity grows 21%/yr (doubles every 31/2 yrs) unless methodology is updated
5Jin-Fu Li, EE. NCUFall, 2004
VLSI Design Methodologies• Design methodology
− process for creating a design
• Methodology goals− Design cycle− Complexity− Performance− Reuse− Reliability
6Jin-Fu Li, EE. NCUFall, 2004
IC Community
Siliconfoundry
ICdesign
CAD tool
provider
Design rules
Simulation models and parameters
Mask layouts
Integrated circuits
Process information Software tools
[M. M. Vai, VLSI design]
7Jin-Fu Li, EE. NCUFall, 2004
System to Silicon Design
[Source: MITRE]
System Requirements Hardware Architecture
Σ
Synthesis
Design For Test
Control
Observe
PhysicalFabricate and TestSystem Integration
Algorithm
X[k] = Σ x[n]e-j2 πk/N
x[n] = Σ X[k]e+j2 πk/N
System Requirements Hardware Architecture
Σ
Synthesis
Design For Test
Control
Observe
PhysicalFabricate and TestSystem Integration
Algorithm
X[k] = Σ x[n]e-j2 πk/N
x[n] = Σ X[k]e+j2 πk/N
8Jin-Fu Li, EE. NCUFall, 2004
Simplified VLSI Design Flow
Processor
RegisterALU
Leaf Cell
Transistor
Algorithm
FSM
ModuleDescription
BooleanEqu.
Mask
CellPlacement
ModulePlacement
ChipFloorplan
BehavioralDomain
StructuralDomain
PhysicalDomain
9Jin-Fu Li, EE. NCUFall, 2004
VLSI Design Flow
Concept
Behavior Specification
Designer
Behavior Synthesis
RTL Design
Logic Synthesis Netlist (Logic Gates)
Layout Synthesis
Layout (Masks)
Manufacturing
Final ProductDesignValidation
RTLVerification
Layout Verification
LogicVerification
ProductVerification
10Jin-Fu Li, EE. NCUFall, 2004
Behavioral Synthesis & RTL Synthesis
Vary clock period1 clock cycle
Vary clock periodVary # clock cycles
Multiple Architectures
Single ArchitectureSource: Synopsys
4 cycles=16 ns
3 cycles=15 ns
2 cycles=20 ns
1 cycle=50 ns
Behavioral Synthesis
RTL Synthesis
HDL
fkdcibiaz +×−×= )()()(
11Jin-Fu Li, EE. NCUFall, 2004
Behavioral Synthesis (Resource Allocation)• Source code defines the functionality
y_real := a_real * b_real - a_imag * b_imagy_imag := a_real * b_imag + a_imag * b_real
• Constraints allow designer to explore different architectures, trading off speed vs. area
• Two possible implementations for a complex multiplier:
Fast, but large(4 mult, 1 add, 1 sub)
Small, but slow(1 mult, 1 add/sub)
a_real
a_imag
b_real
b_imag
y_real := (a_real * b_real)- (a_imag * b_imag)
a_real * b_real
a_imag * b_imag
a_real * b_imag
a_imag * b_real
y_imag := (a_real * b_imag)+ (a_imag * b_real)
+/-
MULTIPLEXOR
MULTIPLEXOR
a_real
a_imag
b_real
b_imag
y_real := (a_real * b_real)- (a_imag * b_imag)
a_real * b_real
a_imag * b_imag
a_real * b_imag
a_imag * b_real
y_imag := (a_real * b_imag)+ (a_imag * b_real)
+
-
+
+
[Source: MITRE]
12Jin-Fu Li, EE. NCUFall, 2004
Behavioral Synthesis (Retiming)
[Source: MITRE]
• Allows designer to trade off latency for throughput by adding and moving registers in order to meet timing constraints
• Specification needs to include registers at functional boundaries, without regard to register-to-register timing: software takes care of optimizing register placement
Compiled FunctionalDescription
Circuit After Behavioral Retiming
Max. Speed= 1/23.0 nSec = 43 MHz
Latency = 1 clock cycleMax. Speed= 1/10 nSec = 100 MHzLatency = 3 clock cycles
tp=23.0
register tp = 0.5
> create_clock clk -period 10
> pipeline_design -stages 3
> optimize_registers
tp=9.5
tp=5 tp=8.7
13Jin-Fu Li, EE. NCUFall, 2004
Verification• The four representations of the design
− Behavioral, RTL, gate level, and layout
• In mapping the design from one phase to another, it is likely that some errors are produced− Caused by the CAD tools or human mishandling of the
tools
• Usually, simulation is used for verification, although more recently, formal verification has been gaining in importance
• Two types of simulations are used to verify the design− Functional simulation & timing simulation
14Jin-Fu Li, EE. NCUFall, 2004
Functional & Timing Simulation• Functional simulation
− No delays (or, at most, constant delay) of the functional units are included
− The primary concerns∗ To check if each block performs intended function∗ To modify the design to evaluate alternatives before
finalizing the design
• Timing simulation− The delays associated with the various gates are assigned− Usually, nominal delays are assigned to the gates− Actual verification of the prototype gives more
assurance, since it embodies the process-dependent parameters
15Jin-Fu Li, EE. NCUFall, 2004
Simulation• Circuit-level simulation – SPICE
− High accuracy− Long simulation times − Basic sources of error
∗ Inaccuracies in the MOS model parameters∗ An inappropriate MOS model∗ Inaccuracies in parasitic capacitances and resistancies
• Logic-level simulation− Deal with simulation at the logic level− Timing
∗ Specified with an intrinsic delay and a load dependent delay
16Jin-Fu Li, EE. NCUFall, 2004
Simulation− An event-driven simulator− Timing is specified with Tgate=Tintrinsic+CloadxTload
• Switch-level simulation− Switch simulators merge logic-simulator techniques
with some circuit simulation techniques by modeling transistors as switches
− Modeling CMOS gates as either pull-up or pull-down structures
• Mixed-mode simulators− Simulators that merge the good points of functional
simulation, logic simulation, switch simulation, timing simulation, and circuit simulation
17Jin-Fu Li, EE. NCUFall, 2004
Formal Verification• Formal method
− The application of logic to the development of “correct”systems
− Mathematically-based languages, techniques, and tools for specifying and verifying systems
• Correctness is classically viewed as two separate problems− Validation & Verification
• Validation− Answers “are we building the right system?”
• Verification− Answers “are we building the system right?”
18Jin-Fu Li, EE. NCUFall, 2004
Formal Validation & Verification• Formal validation
− Can we use logic to help ensuring that the specification is complete, consistent, and accurately captures the customer’s requirement
• Formal verification− Can we use logic to help ensuring that the system built
faithfully implements its specification
• Specification− Properties: enumeration of assumptions & requirements− Functions: desired behavior or design descriptions− State machines: desired behavior or design descriptions− Timing requirements, etc.
19Jin-Fu Li, EE. NCUFall, 2004
Formal Verification Methods• Formal validation methods major consist of
− Theorem proving∗ Prove that an implementation satisfies a specification by
mathematical reasoning− Equivalence checking
∗ Compare high level (RTL) with gate level− Model checking
∗ Determine the validity of formulas written in some temporal logic with respect to a behavioral model of a system
∗ E.g., Symbolic Model Checking◊ Represent transition/output relations and sets of states
symbolically using reduced ordered binary decision diagram (ROBDD)
◊ Problem: state explosion (max~400 Boolean variables)
20Jin-Fu Li, EE. NCUFall, 2004
DFT Flow
Behavioral Description
Behavioral DFT Synthesis
RTL Description
Logic DFT Synthesis
Gate Description
Test Pattern Generation
Fault Coverage ?
Gate
Technology Mapping
Layout
Parameter Extraction
Test Application
Good Product
Manufacturing
Product
HighLow
21Jin-Fu Li, EE. NCUFall, 2004
Fabrication
[Source: MITRE]
22Jin-Fu Li, EE. NCUFall, 2004
Design Strategies – Design Parameters
• Performance− Speed, power, function, flexibility
• Size of die (cost of die)
• Time to design (cost of engineering and schedule)
• Ease of test generation and testability (cost of engineering and schedule)
23Jin-Fu Li, EE. NCUFall, 2004
Design Strategies – Hierarchy
• Hierarchy− Dividing a module into submodules and then
repeating this operation on the submodules
• Structural hierarchy− Reflect functionality, such as the adding, multiplexing,
or storing state
• Physical hierarchy− An n-bit component is built with n identical bit-slices
24Jin-Fu Li, EE. NCUFall, 2004
Design Strategies – Example
ci+1
ai bi
ci
si
FA0 FA1 FA2 FA3
x
y
ci+1
x y
x
y Structural Hierarchy
25Jin-Fu Li, EE. NCUFall, 2004
Design Styles – Full Custom
AB
Z
z
VddVss
A
B
26Jin-Fu Li, EE. NCUFall, 2004
Design Styles – Programmable Logic Array
Buffering Buffering
Inputs Outputs
AND array OR array
27Jin-Fu Li, EE. NCUFall, 2004
Design Styles – Gate Array
Cell 1
Cell 2
Cell 3
Cell4
Cell5
Cell6
Cell7
Cell8
Cell9
Cell10
Cell11
Cell12
Cell13
Cell14
Cell15
Cell16
Cell17
Cell18
Cell19
Cell20
Cell21
Cell22
Cell23
Cell24
28Jin-Fu Li, EE. NCUFall, 2004
Standard-Cell Design Styles
Cell 1
Cell 2
Cell 3
Cell4
Cell5
Cell6
Cell7
Cell8
Cell9
Cell10
Cell11
Cell12
Cell13
Cell14
Cell15
Cell16
Cell17
29Jin-Fu Li, EE. NCUFall, 2004
Standard-Cell Design Styles• Design entry
− Enter the design into an ASIC design system, either using a hardware description language (HDL) or schematic entry
• An example of Verilog HDLmodule fadder(sum,cout,a,b,ci);output sum, cout;input a, b, ci;reg sum, cout;
always @(a or b or ci) beginsum = a^b^ci;cout = (a&b)|(b&ci)|(ci&a);
endendmodule
ci
a b
cout
sum
fadder
30Jin-Fu Li, EE. NCUFall, 2004
Design Styles – Comparison
Design Styles Advantages Disadvantages
Full-custom - Compact designs;- Improved electricalcharacteristics;
- Very time consuming;- More error prone;
Semi-custom
Gate array
-Well-tested standard cells which can be shared between users;-Good for bottom-up design;
-Can be time consuming tobuilt-up standard cells;
-Expensive in the short termbut cheaper in long-term costs;
-Fast implementation;-Easy updates;-Only two layers of metalrequire customization;
-Can be wasteful of spaceand pin connections;
-Relatively expensive in large volumes;
31Jin-Fu Li, EE. NCUFall, 2004
Emergence of SOC Idea
• Motivation:− Transistor density− Moor's law
• Integration with analog parts− AMS specification, synthesis,
simulation
• SoC Design Methodology and Tools− Filling the Gap through
∗ Reuse∗ Design Automation∗ System Specification
Methodology
Source: Synopsys
32Jin-Fu Li, EE. NCUFall, 2004
What’s a System?
System
[Source: M. Gudarzi]
33Jin-Fu Li, EE. NCUFall, 2004
What’s a System?
[Source: M. Gudarzi]
• Customer’s view:System = User/Customer-specified functionality + requirements in terms of: Cost, Speed, Power, Dimensions, Weight, …
• Designer’s view:System = HW components +SW modules
34Jin-Fu Li, EE. NCUFall, 2004
HDL’s & SDL’s: Requirements
• HDL’s
• HardwareC
• Verilog
• AHDL
• VHDL
SDL’sC
Pascal
ADA
[Source: M. Gudarzi]
35Jin-Fu Li, EE. NCUFall, 2004
HDL’s & SDL’s: Realization
[Source: M. Gudarzi]
Operating System
SoftwareProgram
HardwareProgram
CompilationSynthesis
36Jin-Fu Li, EE. NCUFall, 2004
HDL’s & SDL’s: Features
[Source: M. Gudarzi]
• Hardware Realization− Speed− Energy Efficiency− Cost Efficiency (in
high volumes)
• Software Realization− Flexibility− Ease of Development− Ease of Test and Debug− Cost = SW + Processor
Any SW-realizable algorithm is HW-realizable as well.
37Jin-Fu Li, EE. NCUFall, 2004
HW-SW Co-design• How much SW + how much HW?
• Objectives:− Power− Speed− Area− Memory space− Time-to-market
• Implementation platform:− Collection of chips on a board (MCM)− …
38Jin-Fu Li, EE. NCUFall, 2004
HW/SW Co-Design Methodology
• Must architect hardware and software together:− provide sufficient resources;− avoid software bottlenecks.
• Can build pieces somewhat independently, but integration is major step.
• Also requires bottom-up feedback
39Jin-Fu Li, EE. NCUFall, 2004
HW/SW Co-design Main TopicsSynthesis
VerificationSpecification
System H S
OS
System
[Source: M. Gudarzi]
40Jin-Fu Li, EE. NCUFall, 2004
[Source: M. Gudarzi]
Co-Synthesis
SystemSpecification
Partitioning
HW ParameterEstimation
SW ParameterEstimation
SystemIntegration
Verification
Verification
Verification
Verification
Final Verification
SW SynthesisHW Synthesis
ASIC OS
EXE Code
41Jin-Fu Li, EE. NCUFall, 2004
SOC Design Essentials• Realization strategy:
− Automated HW-SW Co-design + Reusable Cores− Intellectual Property: IP Cores
• IP Core Examples:− Processors: PowerPC, 680x0, ARM− Controllers: PCI, SCSI, IDE− DSP Processors: TI− ...
• IP Core Categories:− Soft Cores: HDL, SW/HW Cores− Firm Cores: Synthesized HDL− Hard Cores: Layout for a specific fabrication process
42Jin-Fu Li, EE. NCUFall, 2004
SOC Design Future• Co-design and SoC technology trends
− Enabling Technology∗ Fabrication of chemical, mechanical, optical, other sensors
and actuators∗ More transistor density
− Aimed at virtually any digital system∗ Multimedia, Network, Automotive∗ Home appliances, Network appliances, Connected Home∗ ...
• Limiting Factors− Power Consumption− Paradigm shift from gate delay to interconnect delay− Nanometer dimensions in coming decades
43Jin-Fu Li, EE. NCUFall, 2004
SOC Design Future• Future work
− Design Automation Tools (CAD Tools)∗ Algorithms: Estimation, Synthesis∗ User-friendly interface
− Verification methodology∗ Formal Verification
− Testing methodology∗ Test quality improvement ∗ ….
− Design for manufacturability issues∗ Yield improvement∗ …
− ….
44Jin-Fu Li, EE. NCUFall, 2004