Chapter 2jhuang/JCH/LD/chapter2.pdf · J. C. Huang, 2003 Digital Logic Design 24 Weighted decimal...
Transcript of Chapter 2jhuang/JCH/LD/chapter2.pdf · J. C. Huang, 2003 Digital Logic Design 24 Weighted decimal...
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Chapter 2
Number Systems, Arithmetic, and Code
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J. C. Huang, 2003 Digital Logic Design 1
Positional number systems
• What is the underlying principle?• Can you find an example of a number
system that is not positional?• What are the reasons for using different
bases?
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J. C. Huang, 2003 Digital Logic Design 2
Notational convention
• 234.16= 2 × 100 + 3 × 10 + 4 × 1 + 1 × 0.1 + 6 × 0.01= 2 × 102 + 3 × 101 + 4 × 100 + 1 × 10-1 + 6 × 10-2
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J. C. Huang, 2003 Digital Logic Design 3
Basic arithmetic operations
• The basic operations are addition, subtraction, multiplication, and division.
• They are very similar for positional number systems with different bases.
• Solutions to any computational problems to be solved on a computer must be expressed in terms of these operations.
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J. C. Huang, 2003 Digital Logic Design 4
Methods of number conversion
• Polynomial method• Iterative method• Special conversion method
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J. C. Huang, 2003 Digital Logic Design 5
Signed numbers
• sign and magnitude• r’s-complement• (r-1)’s complement
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J. C. Huang, 2003 Digital Logic Design 6
Graphicalinterpretationofsign-magnitudenumbers
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J. C. Huang, 2003 Digital Logic Design 7
Graphical interpretation of complements
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J. C. Huang, 2003 Digital Logic Design 8
Subtraction
• Shown below are the steps involved in performing M-N through complementation and addition.
• Here M and N are unsigned numbers.
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J. C. Huang, 2003 Digital Logic Design 9
(r-1)’s vs. r’s complement
rn - N(rn - 1) - NDefinition:
given N with n digits
r's complement(r-1)'s complement
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J. C. Huang, 2003 Digital Logic Design 10
(r-1)’s vs. r’s complement
digitwise (bitwise) complementation + 1
digitwise (bitwise) complementation
Computation involved in
obtaining the complement
r's complement(r-1)'s complement
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J. C. Huang, 2003 Digital Logic Design 11
(r-1)’s vs. r’s complement
onetwo (+0 and -0)Number of zero
r's complement(r-1)'s complement
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J. C. Huang, 2003 Digital Logic Design 12
(r-1)’s vs. r’s complement
M - N → M + rn - N = rn + M - N= rn - (N - M)
M - N → M + (rn-1) - N = rn + M - N - 1= (rn - 1) - (N - M)
Subtraction operation
r's complement(r-1)'s complement
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J. C. Huang, 2003 Digital Logic Design 13
(r-1)’s vs. r’s complement
M - N → M + rn - N What will happen?There is a carry.How to produce M-N?Subtract rn by discarding the carry.
M-N → rn + M - N - 1 What will happen?There is a carry.How to produce M-N?(1) Subtract rn by discarding the carry.(2) Add 1 to it.
If M > N
r's complement(r-1)'s complement
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J. C. Huang, 2003 Digital Logic Design 14
(r-1)’s vs. r’s complement
M - N → rn - (N-M)What will happen? There is no carry.
How to produce M-N (in sign-and-magnitude)?The result is negative and in r's complement.(1) Perform r's complement (i.e., (r-1)'s complement plus 1) to obtain (N-M).(2) Prefix it with a minus sign to indicate that it is negative.
M - N → (rn-1) - (N -M)What will happen? There is no carry.
How to produce M-N (in sign-and-magnitude)?The result is negative and in (r-1)'s complement.(1) Perform (r-1)'s complement to obtain (N-M).(2) Prefix it with a minus sign to indicate that it is negative.
if M < N
r's complement(r-1)'s complement
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J. C. Huang, 2003 Digital Logic Design 15
(r-1)’s vs. r’s complement
M - N → M + rn - NWhat will happen?There is a carry. How to produce M-N?It is treated as if M>N, producing a "0" as the result.
M-N → rn + M - N - 1 What will happen?There is no carry. How to produce M-N?It is treated as if M<N, producing a "-0" as the result.
if M = N
r's complement(r-1)'s complement
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J. C. Huang, 2003 Digital Logic Design 16
Interpretation of four-bit signed binary integers
b3b2b1b0 sign and mag. 1's complement 2's complement
0111 +7 +7 +70110 +6 +6 +60101 +5 +5 +50100 +4 +4 +40011 +3 +3 +30010 +2 +2 +20001 +1 +1 +10000 +0 +0 +01000 -0 -7 -81001 -1 -6 -71010 -2 -5 -61011 -3 -4 -51100 -4 -3 -41101 -5 -2 -31110 -6 -1 -21111 -7 -0 -1
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J. C. Huang, 2003 Digital Logic Design 17
The use of 2’s complement
• In practice, signed numbers are always represented by 2’s complements because then there is only one zero.
• Existence of more than one zero leads to complication in programming.
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J. C. Huang, 2003 Digital Logic Design 18
25–( )
Examples of 1’s complement addition
+ 0 0 1 01 0 1 0
+ 0 0 1 00 1 0 15+( )
2+( )+ +( )+0 1 1 1 1 1 0 0-( 3)7+( )
+ 1 1 0 1+ 1 1 0 10 1 0 1 1 0 1 05+( )
25–( )
7–( )2)
0 1 1 111
0 0 1 011
0 0 1 1 1 0 0 0
+ –(+ –( )3+( )
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J. C. Huang, 2003 Digital Logic Design 19
5+( )2+
7+( )
5+( )2–( )
2+5–( )
3–( )
5–( )+ 2–( )
1 0 1 1
Examples of 2’s complement addition
++ 0 0 1 00 1 0 1
1 1 0 1
0 0 1 0
0 1 1 1
++ 1 1 1 0
1 0 0 1
1 0 1 11 1 1 0
0 0 1 1
0 1 0 1
11
ignore
( )+ ( )+
+
–( 7)3+( )
ignore
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J. C. Huang, 2003 Digital Logic Design 20
5+( )2+( )
3+( )
–
–
5+( )–
5–( )
7–( )
2+( )
2–( )
Examples of 2’s complement subtraction 1 1 0 13–( )
– 0 0 1 00 1 0 1
+ 1 1 1 00 1 0 1
1 0 0 1 1
ignore
– 0 0 1 01 0 1 1
+ 1 1 1 01 0 1 1
1 1 0 0 1
ignore
– 1 1 1 00 1 0 1
+ 0 0 1 00 1 0 1
0 1 1 17+( )
– 1 1 1 01 0 1 1
– 2–( )5–( )
+ 0 0 1 01 0 1 1
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J. C. Huang, 2003 Digital Logic Design 21
Overflow
• In adding two binary numbers, an overflowcondition is said to occur if the resulting sum requires more bits than are available.
• Let x be the carry into the sign-bit position and y be the carry from the sign-bit position, then there is an overflow if and only if x ⊕ y = 1.
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J. C. Huang, 2003 Digital Logic Design 22
1 0 0 1
Examples of determination of overflow
++ 0 0 1 00 1 1 1
1 0 1 1
0 0 1 0
1 0 0 1
72
+( )+ 2+
7–( )( )+ ( )+
5)–(9+( )c4c3
==
01
c4c3
==
00
++ 1 1 1 00 1 1 1 1 0 0 1
0 1 1 1
1 1 1 0
0 1 0 1
72
+( )–
7–( )–( )
5+( )
+ ( ) + 2
1 1–( 9)c4c3
c4c3
==
11
==
10
There is an overflow if c3 ⊕ c4 = 1
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J. C. Huang, 2003 Digital Logic Design 23
Decimal codes
• Weighted decimal codes• Non-weighted decimal codes• Bar codes
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J. C. Huang, 2003 Digital Logic Design 24
Weighted decimal codes
0100001010001001001000101000011000010000011000010100010010010001010000
0000100101110010101101001101100001101111
0000000100100011010010001001101010111100
0000000100100011010010111100110111101111
0000000100100011010001010110011110001001
0123456789
biquinarycode
5043210
7536 code
5421 code
2421 code
8421 code
(BCD)
decimal digit
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J. C. Huang, 2003 Digital Logic Design 25
Nonweighted decimal codes
11000000110010100110010010101001100100011001010100
0011010001010110011110001001101010111100
0123456789
2-out-of-5 codeexcess-3 codedecimal digit
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J. C. Huang, 2003 Digital Logic Design 26
US Postal Service bar code (2 out of 5)
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J. C. Huang, 2003 Digital Logic Design 27
Gray code (a unit distance code)
000001011010110111101100
01234567
Gray codedecimal number
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J. C. Huang, 2003 Digital Logic Design 28
Angular position encoders
Gray codeconventional binary
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J. C. Huang, 2003 Digital Logic Design 29
The effects of misaligned sensors on the encoders
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J. C. Huang, 2003 Digital Logic Design 30
Alphanumeric Codes
• ASCII code• Unicode Standard
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J. C. Huang, 2003 Digital Logic Design 31
Error detection
• A parity bit can be used to detect single-bit errors.
• Additional parity bits can be used to detect multiple errors.
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J. C. Huang, 2003 Digital Logic Design 32
Examples of ASCII code with parity bit
.
.
.10000011100001011000011010001001
.
.
.
.
.
.10000010100001001000011110001000
.
.
.
.
.
.ABCD...
with odd paritywith even paritycharacters
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J. C. Huang, 2003 Digital Logic Design 33
Error correction
• Hamming code• Use of check-sum digits
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J. C. Huang, 2003 Digital Logic Design 34
Hamming code
• Hamming code is an error-detection and error-correction binary code.
• A single-bit error can be automatically corrected if we can determine which bit is in error.
• A single-bit error can be detected by using a parity bit.
• Multiple parity bits can be used to pinpoint the bit in error.
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J. C. Huang, 2003 Digital Logic Design 35
Hamming code
Bit position 1 2 3 4 5 6 7 8 9 10 11 12
Use P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
Scope of P1 √ √ √ √ √ √
Scope of P2 √ √ √ √ √ √
Scope of P4 √ √ √ √ √
Scope of P8 √ √ √ √ √
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J. C. Huang, 2003 Digital Logic Design 36
Example
For example, to cons truct the Hamming code of 00101110
Use P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
0 0 1 0 1 1 1 0
Scope of P1 √ √ √ √ √ √
Scope of P2 √ √ √ √ √ √
Scope of P4 √ √ √ √ √
Scope of P8 √ √ √ √ √
Bit position 1 2 3 4 5 6 7 8 9 10 11 12
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J. C. Huang, 2003 Digital Logic Design 37
Example (continued)
Choose 0 for P1 (assuming the use of even parity)
Use P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
0 0 0 1 0 1 1 1 0
Scope of P1 √ √ √ √ √ √
Scope of P2 √ √ √ √ √ √
Scope of P4 √ √ √ √ √
Scope of P8 √ √ √ √ √
Bit position 1 2 3 4 5 6 7 8 9 10 11 12
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J. C. Huang, 2003 Digital Logic Design 38
Example (continued)
Choose 1 for P2
Use P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
0 1 0 0 1 0 1 1 1 0
Scope of P1 √ √ √ √ √ √
Scope of P2 √ √ √ √ √ √
Scope of P4 √ √ √ √ √
Scope of P8 √ √ √ √ √
Bit position 1 2 3 4 5 6 7 8 9 10 11 12
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J. C. Huang, 2003 Digital Logic Design 39
Example (continued)
Choose 1 for P4
Use P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
0 1 0 1 0 1 0 1 1 1 0
Scope of P1 √ √ √ √ √ √
Scope of P2 √ √ √ √ √ √
Scope of P4 √ √ √ √ √
Scope of P8 √ √ √ √ √
Bit position 1 2 3 4 5 6 7 8 9 10 11 12
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J. C. Huang, 2003 Digital Logic Design 40
Example (continued)
Choose 1 for P8
Use P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
0 1 0 1 0 1 0 1 1 1 1 0
Scope of P1 √ √ √ √ √ √
Scope of P2 √ √ √ √ √ √
Scope of P4 √ √ √ √ √
Scope of P8 √ √ √ √ √
Bit position 1 2 3 4 5 6 7 8 9 10 11 12
![Page 42: Chapter 2jhuang/JCH/LD/chapter2.pdf · J. C. Huang, 2003 Digital Logic Design 24 Weighted decimal codes 0100001 0100010 0100100 0101000 0110000 1000001 1000010 1000100 1001000 1010000](https://reader031.fdocuments.us/reader031/viewer/2022011918/6003d5e90a0ba37802417a5e/html5/thumbnails/42.jpg)
J. C. Huang, 2003 Digital Logic Design 41
General properties of Hamming code
• It can be used for any code words with m information bits. It uses k parity bits such that m ≤ 2k - k - 1.
• By adding an additional parity bit to a Hamming code, we will be able to achieve single-error correction and double-error detection.
![Page 43: Chapter 2jhuang/JCH/LD/chapter2.pdf · J. C. Huang, 2003 Digital Logic Design 24 Weighted decimal codes 0100001 0100010 0100100 0101000 0110000 1000001 1000010 1000100 1001000 1010000](https://reader031.fdocuments.us/reader031/viewer/2022011918/6003d5e90a0ba37802417a5e/html5/thumbnails/43.jpg)
J. C. Huang, 2003 Digital Logic Design 42
Check sum digit is inserted to satisfy the relation:ZIP digit sum + check sum digit = 0 modulo 10
to make error correction possible. (Error detection is achieved by using the 2-out-of-5 code of individual digit)