Chapter 1 : Introduction to Interconnection Networks · · 2006-02-16Chapter 1 : Introduction to...

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Vladimír Guzma / Introduction to Interconnection Networks 2/15/2006Institute of Digital and Computer Systems / TKT-9636

Chapter 1 : Introduction to Interconnection Networks

What are we going to talk about this semester?“Three Questions About Interconnection Networks”

What is interconnection network?Where can we find them?Why are they important?

Uses of Interconnection NetworksProcessor-Memory InterconnectI/O InterconnectPacket Switching Fabric

Network BasicsTopologyRoutingFlow ControlRouter ArchitecturePerformance of Interconnection Networks

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What?

Digital systems are build from basic blocksLogic, Memory, CommunicationThis course deals with communication component

• More specifically, interconnection networks

What limits performance of digital systems?Not a memoryNot a logicCommunication!

Time is wasted on wire delay, not on gate delayAll the time, we hear about new technologies, with smaller and smaller numbers (130nm, 90nm, 65nm, 45nm, 32nm, …)Speed of light remains unchangedWiring density scales slower then componentsFrequency of communication is far lower then frequency of processors

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Interconnection bandwidth is scarce, how can we use it effectively?Interconnection networks were originally developed for multicomputersNow, they replace buses as system-level interconnection

Routing packets is more economical then routing wires

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Three Questions About Interconnection Networks

What is interconnection network?Where do you find them?Why are they important?

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What is interconnection network?

“Interconnection network is programmable system that transports data between terminals.” (Fig 1.1)The network is programmable in sense that it makes different connections at different points of time

On-chip networks deliver data between memory arrays, registers, arithmetic unitsLocal-area and wide-area networks connect systems together within a location, or whole planet(s).

• “Did you hear about that Internet thing?”

This course is restricted to smaller scales, chip-level to system level.

For courses on larger-scale networks, there is whole “Institute of Communications Engineering” to askAt system and chip-level, the channels are short and data rates very high, this brings lot of differences from large scale networks

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Where do you find interconnection networks?

Almost all digital systems large enough to have two components to connect

Computer systems• Processors to memories• Input/output devices to I/O controllers

Communication switches• Input ports and output ports of network routers

Anywhere where bits are transferred between two components of system, it is likely there is interconnection network

Simple (old style) interconnection networkMulti-drop bus (Chapter 22 is about buses)

Buses are unable to keep up with bandwidth demand of silicon scaling (50% per year?)

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Why are interconnection networks important?

Communication is often limiting factor in performanceInterconnection network determines memory latency and memory bandwidth

Interconnection network allows to SHARE scarce wiring resources

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Uses of Interconnection Networks

Network parameters:The number of terminalsThe peak bandwidth of each terminalThe average bandwidth of each terminalThe required latencyThe message size or a distribution of message sizesThe traffic patterns expectedThe required quality of servicesThe required reliability and availability

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Number of terminals – number of components that must be connected to networkBandwidth (bits/s)

We assume it is symmetric – input and output bandwidth are equalPeak bandwidth – maximum data rate terminal will request over short period of timeAverage bandwidth – average data rate terminal will require

Time required to deliver individual message – latencyIdeal case: network supports high bandwidth and low latencyRealistic case: there is tradeoff between these two parameters

• High bandwidth keeps network resource busy, causing contention of resources

• Contention – two or more messages want to use same shared resource

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Message size – length of message in bitsIf messages are small, overhead of network can have large impacton performanceIf messages are large, overhead is almost zeroThere may be several possible message sizes in system

How are messages from each terminal distributed to all possible destination terminals defines traffic pattern

Each terminal sends message to all other terminals with equal probability – random traffic patternTerminal sends messages only to neighbor terminals

QOS – Quality Of ServicesIt involves fair allocation of resources under some policyContention can be resolved in several ways, first-come first-served, how long have message been in network, …

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ReliabilityMeasures of how often network correctly perform delivery of message100% is often needed

• Can be done by adding hardware for error detection and correction, high level software protocol, …

Sometimes, packet dropping is allowed

AvailabilityFraction of time network is available and operating correctly

• Internet router – 99.999% - 5 minutes per year downtime

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Processor-Memory Interconnect

Example:Dance hall architecture, M memory banks connected to P processorsIntegrated node architecture, processor and memories are combined in integrated node – processor access local memory without interconnection network

There is difference between message and pocket Message is of transfer from network clients to the networkSimple message can create one or more packets

• Message may need to be split to several packets

QOS – not neededMechanism is self-throttlingProcessors can have only limited number of requests for memory the will be idle, waiting for repliesBecause they are not creating new request while idle, the congestion is reduced

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I/O Interconnect

I/O devices attached to processors and/or memoriesArray of disk drives and set of host adaptersVarying peak to average bandwidth

• Random read requires reposition of head• Consecutive read offers higher data rate

Also inter-processor communication networks for message passing in clustered parallel computers are in this group

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Packet Switching Fabric

Interconnection network is element of router for large scale network

Array of line-cards are connected to large scale network channelsThey process each packet to determine destinationForward packet to switching fabricFabric delivers packet from source line card to destination line card

Not self-throttlingLine card sends steady stream of packetsFabric must provide guaranteed bandwidth for certain class of pocketsExcess of traffic for line card a should not interfere or steal bandwidth from traffic destined for line card b

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Network Basics

Key to efficiency of interconnection networks is in sharing resourcesInstead of creating dedicated channel between each terminal pair, interconnection network is created with shared router nodes

Connection pattern of these nodes defines network’s topologyMessage is delivered by making several hops across shared channels and nodes

There may be several paths that message could take from source to destination in given topology

Routing determines which of these possible paths message takesGood choice minimizes the length while balancing demand placed on shared nodes

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If one resource becomes overloaded while others are unused total bandwidth is reduced

Flow control dictates which messages get access to network resources over a time

This becomes critical with high utilization of resources

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Topology (Chapters 8 to 10)

It may be seen as analogy to roadmapChannels (like roads) carry packets (cars) from one router node (intersection) to anotherFig. 1.6 torus topologyTopology should utilize packaging technology of components (fig.1.7)Another example can be ring topology (1.8)

Distance between nodes (hop count) is number of channels and nodes message must traverse on average

To reduce it we can increase node degree – number of channels entering and leaving each node (compare fig 1.6 and 1.8)

With varying message sizes, serialization become issueMessage of size X needs to be send as a sequence of packets of size Y (Y < X)Latency of message is then hop latency plus serialization latency

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Routing (Chapters 8 to 10)

It determines the path taken by packet from source terminal node to destination terminal node

Route or path is ordered set of channelsIn some network there may be only single router from each source to each destinationIn other (torus) there may be severalIn case of several paths, routing balances load across channelsRouting steers cars on our roadmap at each intersectionFig 1.9 – two routes from 01 to 22Dimension-order routing, first in x-dimension then in y-dimensionDimension-order routing creates load imbalance (imagine another route from 11 to 20, same channel between 11 and 21 – double load

Routing algorithms that choose single fixed path between each source destination pair (deterministic routing) creates load imbalance and have low bandwidth

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Flow Control (Chapters 12 and 13)

Manages allocation of resource to packets as they move along routeKey resources are channels and buffers

Buffers are storage implemented within nodes (registers, memories) and allow packets to be held temporarily at nodesAnalogy: flow control controls traffic lights, determining when packet can advance to next stretch of road and when it must pull off (buffer) and allow other car pass

Flow control must avoid resource conflicts that can hold channel idle

Flow control strategy should be fair and avoid deadlockTime-space diagram (fig 1.10) describes flow control

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Performance of Interconnection Networks (Chapters 23 to 25)

Primary description is latency vs. offered traffic curveAverage latency of a packet as a function of offered traffic – average amount of traffic generated by each source terminal of networkThere is no simple expression to get thoseNeeds discreet even simulation

Zero-load latencyLower bound on average latency of packet through the networkAssumes that packet never contends for network resources with other packetsUsing this assumption, average latency is serialization latency plus hop latencyEXAMPLE: packet length L = 512bits, bandwidth b=16Gbits/s

• Serialization latency L/b = 32ns• With minimal routing, hop count Hmin= 2• Router latency tr = 10ns• Lover bound on latency is then 32 + 20 = 52ns

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Using average hop count, number is higherHavg >= Hmin

The actual zero-latency has constraints of topology along with performance, routing flow control

Similar approach gives upper bound on throughput of network

Throughput – accepted traffic is rate that traffic is delivered to destination terminalsWith limitations of topology, routing flow control we can see how each decision affects performance

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History

Three parallel threads:Telephone switching networksInter-processor communicationProcessor-memory interconnect

Inter-process communication was influenced by packaging Early: 2-D arrays, no routingTorus network, physical regularityN-cube, hyper-cube – low diameterRealistic packaging constrains caused low-dimensional networks to outperform hypercube

Three threads of networks mergedThere is almost no difference between inter-processor and processor-memory networks

Routing and flow control evolved also

Chapter 1 : Introduction to Interconnection Networks · · 2006-02-16Chapter 1 : Introduction to...

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