Chap. 12 Memory Organization

Computer System Architecture© Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.Chap. 12 Memory OrganizationChap. 12 Memory Organization

12-1Chap. 12 Memory Organization

12-1 Memory Hierarchy Memory hierarchy in a computer system : Fig. 12-1

Main Memory : memory unit that communicates directly with the CPU (RAM) Auxiliary Memory : device that provide backup storage (Disk Drives) Cache Memory : special very-high-speed memory to increase the processing

speed (Cache RAM)

Multiprogramming enable the CPU to process a number of independent program concurrently

Memory Management System : sec. 12-7 supervise the flow of information between auxiliary memory and main memory

Magnetictapes

Magneticdisks

I/ O processor

C PU

Mainmemory

C achememory

Auxiliary memory


12-2

12-2 Main Memory Bootstrap Loader

A program whose function is to start the computer software operating when power is turned on

RAM and ROM Chips Typical RAM chip : Fig. 12-2

» 128 X 8 RAM : 27 = 128 (7 bit address lines) Typical ROM chip : Fig. 12-3

» 512 X 8 ROM : 29 = 512 (9 bit address lines)

×

128× 8RAM

C S1

AD7

WR

RD

C S2

C hip selec t 1

C hip selec t 2

Read

Write

7 bit address

8 bit data bus

(a) Block diagram

C S1 WRRDC S2 Memory func tion State of data bus

0×

××

00 0

0 0

01 11

1

1

1

×

0×

×

0

11

Inhibit

InhibitInhibit

WriteReadInhibit

High- impedance

High- impedanceHigh- impedance

Input data to RAMOutput data from RAMHigh- impedance

(b) Function table

512× 8ROM

C S1

AD9

C S2

C hip selec t 1

C hip selec t 2

9 bit address

8 bit data bus

P ower- ON

FFFF :0000(Reset P oint)

P OST

System Init.

INT 19

Load Bootstrap Record(Track 0, Sector 0)

Load Operating System(IO .SYS, MSDOS.SYS, C OMMAND.C OM)

Bootstrap LoaderBootstrap ROMBoot ROM


12-3

Memory Address Map Memory Configuration : 512 bytes RAM + 512 bytes ROM

» 1 x 512 byte ROM + 4 x 128 bytes RAM Memory Address Map : Tab. 12-1

» Address line 9 8 RAM 1 0 0 : 0000 - 007F RAM 1 0 1 : 0080 - 00FF RAM 1 1 0 : 0100 - 017F RAM 1 1 1 : 0180 - 01FF

» Address line 10 ROM 1 : 0200 - 03FF

Memory Connection to CPU : Fig. 12-4» 2 x 4 Decoder : RAM select (CS1)

» Address line 10 RAM select : CS2 ROM select : CS2 의 Invert

» 참고 RD : ROM 의 CS1 은 보통 OE(Output Enable) 로 사용

128× 8RAM 1

C S1

AD7

WR

RD

C S2

128× 8RAM 2

C S1

AD7

WR

RD

C S2

128× 8RAM 4

C S1

AD7

WR

RD

C S2

128× 8RAM 3

C S1

AD7

WR

RD

C S2

128× 8ROM

C S1

C S2

AD9

Data

Data

Data

Data

Data

C PU

WRRD16 - 11 10 9 8 7 - 1

Address bus

Data bus

Decoder

3 2 1 0

1- 7

8

9


12-4

12-3 Auxiliary Memory Magnetic Disk : Fig. 12-5, FDD, HDD Magnetic Tape : Backup or Program 저장 Optical Disk : CDR, ODD, DVD

12-4 Associative Memory Content Addressable Memory (CAM)

A memory unit accessed by content Block Diagram : Fig. 12-6

texttexttexttext

Sec

tor

Read/ Writehead

Tracks

A Register 101 111100K Register 111 000000

Word 1 100 111100 M = 0Word 2 101 000011 M = 1

Argument register (A)

Key register (K)

Assoc iative memoryarray and logic

m words n bits per word

M

Matchregister

Input

Write

Read

Output

이름 주소

Argument

Key (Mask)

Match Logic

Memory 내용

M = 1 일때 출력


12-5

m word x n cells per word : Fig. 12-7

Match Logic One cell of associative memory : Fig. 12-8

» Input = 1 or 0 에 따라 Write 신호와 동시에 F/F 에 저장» A 와 K 에 의해 Match Logic 에서 M=1 이면 (M 을 READ 에 직접 연결 가능함 )

» Read 신호에 따라 F/F 에서 데이터를 읽는다

A 1

C 11

A nA j

K 1 K nK j

C 1j C 1n

C i1 C ij C in

C m1 C mj C mn

M1

Mm

M i

Bit 1 Bit nBit j

Word 1

Word m

Word i

R S Matchlogic

Input

Read

Write

Output

To M i

K jA i

F ij


12-6

Match Logic : Fig. 12-9» Aj = Argument, Fij = Cell ij 번째 bit

» j 번째 1 bit match 조건 xj = Aj Fij (1 AND 1)+ Aj’ Fij’ (0 AND 0)

» 1 - n 까지 n bits match 조건 Mi = x1x2…..xn

» Key bit Kj : xj + Kj’ Kj = 0 : Aj 와 Fij 는 no comparison ( Kj : xj + 1 = 1 )

Kj = 1 : Aj 와 Fij 는 comparison ( Kj : xj + 0 = xj )

» Match Logic for word I :

Mi = (x1 + K1’) (x2 + K2’)…. (xn + Kn’)

= (xj + Kj’)

= (Aj Fij + Aj’ Fij’ + Kj’)

n

j 1

n

j 1

F 'i1 F i1

A 1K 1

F 'i2 F i2

A 2K 2

F 'in F in

A nK n

M i


12-7

12-5 Cache Memory Locality of Reference

the references to memory tend to be confined within a few localized areas in memory

Cache Memory : a fast small memory keeping the most frequently accessed instructions and data in the fast cache

memory Cache 의 설계 요소

cache size : 보통 256 K byte ( 최대 512 K byte) mapping method : 1) associative, 2) direct, 3) set-associative replace algorithm : 1) LRU, 2) LFU, 3) FIFO write policy : 1) write-through, 2) write-back

Hit Ratio the ratio of the number of hits divided by the total CPU references (hits + misses)

to memory» hit : the CPU finds the word in the cache ( 보통 0.9 이상 )» miss : the word is not found in cache (CPU must read main memory)

예제 : cache memory access time = 100 ns, main memory access time = 1000 ns, hit ratio = 0.9

» 1 회 miss : 1 x 1000 ns» 9 회 hit : 9 x 100 ns

총 10 회 Memory 참조

1900 ns / 10 회 = 190 nsCache 가 없으면 1000 ns,따라서 약 5 배 성능 향상


12-8

Mapping The transformation of data from main memory to cache memory

» 1) Associative mapping

» 2) Direct mapping

» 3) Set-associative mapping

Example of cache memory : Fig. 12-10

main memory : 32 K x 12 bit word (15 bit address lines)

cache memory : 512 x 12 bit word» CPU sends a 15-bit address to cache

Hit : CPU accepts the 12-bit data from cache Miss : CPU reads the data from main memory (then data is written to cache)

Associative mapping : Fig. 12-11 Cache memory 로 고가의 associative memory 사용 Address 와 Data 가 직접 Cache memory 에 사용됨

Direct mapping : Fig. 12-12 Cache memory 로 저가의 일반 memory 사용 Tag field (n - k) 와 Index field (k) 를 사용

» 2k words cache memory + 2n words main memory Tag = 6 bit (15 - 9), Index = 9 bit

Cache Coherence (Sec. 13-5)

Main memory32K× 12

C PUC ache memory

512× 12

Argument register

0 1 0 0 0

2 2 3 4 5

0 2 7 7 7

3 4 5 0

1 2 3 4

6 7 1 0

Address Data

C PU address(15 bits)


12-9

Direct mapping cache organization : Fig. 12-13

» 예제 : 02000 번지를 읽는 경우 1) 우선 Index 000 을 cache 에서 찾는다 2) 다음은 Tag 를 cache 에서 비교한다 3) 000 Index 에 있는 cache tag 는 00 이다 (02 가 아니다 ) 4) 따라서 miss 5) 그러므로 main memory 에서 data read

(address 02000 = 5670 read)

32K× 12

Main memory

Address = 15 bitsData = 12 bits

Tag Index

6 bits 9 bits

HexAddress

00 000

3F 1FF

512× 12C ache memory

Address = 9 bitsData = 12 bits

000

1FF

Octaladdress

1 2 2 0

2 3 4 0

3 4 5 0

4 5 6 0

5 6 7 0

6 7 1 0

Memory dataMemory address

000000

02777

02000

01777

01000

00777

00 1 2 2 0

02 6 7 1 0

Tag DataIndex

address 000

777

(a) Main memory

(b) C ache memory

Tag (6 bit)00 - 63

Index (9 bit)000 - 511


12-10

Direct mapping cache with block size of 8 words : Fig. 12-14» 64 block x 8 word = 512 cache words size

8 word 를 1 개의 block 단위로 update

Set-associative mapping : Fig. 12-15 (two-way) Direct mapping ( Fig. 12-13(b)) 에서 같은 Index 에 다른 tag 를 자주 읽으면 속도가

저하됨 ( 예제 02777, 01777 ) 따라서 set 의 개수를 증가시키면 속도가 향상된다 .

000

007

010

017

0 1

0 1

770

777

0 2

0 2

3 4 5 0

6 5 7 8

6 7 1 0

Index Tag Data

Block 0

Block 1

Block 63

Tag Block Word

6 36

Index

0 1 3 4 5 0 0 2 5 6 7 0

0 2 6 7 1 0 0 0 2 3 4 0

000

777

Index Tag Data Tag Data


12-11

Replacement Algorithm : cache miss or full 일때 1) LRU (Least Recently Used) : 최근에 가장 적게 사용된 block 교체 2) LFU (Least Frequently Used) : 사용 빈도가 가장 적은 block 교체 3) FIFO (First-In First-Out) : 가장 오래된 block 교체

Writing to Cache : Cache Coherence(Sec. 13-5) Cache 에 있는 내용이 변경된 (WRITE) 경우 , Cache 의 block 이 교체되기 전에

main memory 에 내용도 update 해야 함

» 1) Write-through : Cache write 와 동시에 main memory 도 항상 동시에 write 한다 .

» 2) Write-back : Cache write 시에 내용이 변경되었다는 flag 만 set 해 놓고 나중에 block 이 교체되기 전에 flag 를 검사하여 변경된 부분만 나중에 write 한다 .

따라서 Write-back 방식은 main memory 가 무효한 상태에 빠져 있을 수 있다 .

Cache Initialization Cache is initialized : 이때 cache 는 empty 상태이고 invalid data 를 갖을 수 있다 .

» 1) when power is applied to the computer

» 2) when main memory is loaded with a complete set of programs from auxiliary memory

valid bit» indicate whether or not the word contains valid data

Main memory 와 Cache memory 의 내용이 동일해야 함 : 통일성 ( 일관성 ) 유지

Cache READ 는 문제 없음


12-12

12-6 Virtual Memory Virtual Memory : Auxiliary memory Main memory

Translate program-generated (Aux. Memory) address into main memory location » Give programmers the illusion that they have a very large memory, even though the

computer actually has a relatively small main memory 예제 : Intel Pentium Processor

» Physical Address Lines = A0 - A31 : 232 = 230 X 22 = 4 Giga

» Logical Address = 46 bits address : 246 = 240 X 26 = 64 Tera

Address Space & Memory Space Address Space : Virtual Address

» Address used by a programmer Memory Space : Physical Address(Location)

» Address in main memory

예제 : Fig. 12-16 address space (N) = 1024 K = 220

» Auxiliary Memory memory space (M) = 32 K = 215

» main Memory

Program 1

Data 1,1

Data 1,2

Program 2

Data 2,1

Program 1

Data 1,1

Auxiliary memory

Main memory

Address spaceN = 1024K =

Memory spaceM = 32K = 215

220


12-13

Memory table for mapping a virtual address : Fig. 12-17 Translate the 20 bits Virtual address into the 15 bits Physical address

Address Mapping Using Pages : Fig. 12-18 Address mapping 을 간단하게 하기 위하여 사용

» Address space 와 memory space 를 fixed size 로 분할하여 사용함

Address space : 1 K page 로 분할 Memory space : 1 k block 으로 분할

» Address space 의 4 개 page 가 memory space 에 block 에 들어 갈수 있다 .

Virtualaddressregister(20 bits)

Memorymaping

table

Memory tablebuffer register

Main memoryaddressregister(15 bits)

Mainmemory

Main memory buffer register

Virtual address

Page 0

Page 7

Page 6

Page 5

Page 4

Page 3

Page 2

Page 1

Block 0

Block 3

Block 2

Block 1

Address spaceN = 8K = 213

Memory spaceM = 4K = 212


12-14

Memory table in a paged system : Fig. 12-19

1 0 1 0 1 0 1 0 1 0 0 1 1

0

0011

1001

1

0

110

1110

01 1

000

111110101100011010001

Tableaddress

Presencebit

Page no. Line numberVirtual address

01 0101010011

Block 0Block 1Block 2Block 3

MBR

Main memory address register

Memory page table

Main memory


12-15

Associative memory page table : Fig. 12-20 Associative memory 를 이용하여 block number(01) 를 곧바로 찾는다

Page(Block) Replacement Page Fault : the page referenced by the CPU is not in main memory

» a new page should be transferred from auxiliary memory to main memory Replacement algorithm : FIFO 와 LRU 주로 사용

1 0 1 Line number

1 1 1 0 0

0 0 1 1 1

1 1 0 1 01 0 1 0 10 1 0 0 0

Argument register

Key register

Assoc iative memory

Page no.

Page no. Bloc k no.

Virtual memory


12-16

12-7 Memory Management Hardware Basic components of a Memory Management Unit

1) Address mapping 2) Common program sharing 3) Program protection

MMU : OS 에서 지원 해야 함 1) CPU 에 내장된 형태 2) 별도의 memory controller 형태

Segment A set of logically related instruction or data elements associated with a given

name 예제 : a subroutine, an array of data, a table of symbol, user’s program

Logical Address the address generated by a segmented program similar to virtual address

» Virtual Address : fixed-length page

» Logical Address : variable-length segment


12-17

Segmented-page MMU Fig. 12-21(a) : 2 개의 table(segment, page) 을 사용함

» 따라서 2 개의 table 을 읽는데 많은 시간이 소모됨 Fig. 12-21(b) : Associative memory 를 이용한 1 개의 table 을 사용함

» 따라서 속도가 빠르다» TLB (Translation Look-a-side Buffer)

associative memory 를 이용한 most recently reference table

Numerical Example 예제 : Logical address & Physical address (Fig. 12-22)

» Logical Address : 4 bit segment : 16 segments 8 bit page : 256 pages 8 bit word : 256 address field

» Physical Address : 12 bit block : 4096 blocks 8 bit word : 256 address field

(a) Logical address format : 16 segments of 256 pages each,each page has 256 words

× 32Physical memory

2 20

Block Word

12 8

(b) Physical address format : 4096 blocks of 256 word each,each word has 32 bits

Segment Page Word

4 8 8

Addressor Index


12-18

Page 0

Page 4

Page 3

Page 2

Page 1

Page number6 00 006 00 FF

Hexadec imaladdress

Segment Page Block

6

6666

00

04030201

012

A61053019000

(a) Logical address assignment (b) Segment- page versus memory block assignment

6 01 006 01 FF

6 02 006 02 FF

6 03 006 03 FF

6 04 006 04 FF

예제 : Logical & Physical address assignment (Fig. 12-23)

Logical Address

Page Table

Block number 019 를 찾는다

Word

Segment

Page


12-19

35

A3

0

6

F

Segment table

012

A61

053

019

000

012

00

35

38

37

36

39

A3

Page table

Block 0

6 02 7E

Logical address (in haxadec imal)

Block 12

32 bit word

Physical memory000 00

000 FF

012 00

012 FF

019 00

019 FF019 7E

(a) Segment and page table mapping

6 02 019

6 04 A61

Segment Page Block

(b) Assoc iative memory (TLB)

Segment Page Word

+

Segment table Page table

Logical address

Block Word

Physical address

(a) Logical to physical address mapping

Segment Page Block

Argument register

(b) Assoc iative memory translation look- aside buffer (TLB)

+


12-20

Memory Protection Typical segment descriptor : Fig. 12-25

Access Rights : protecting the programs residing in memory» 1) Full read and write privileges : no protection

» 2) Read only : write protection

» 3) Execute only : program protection

» 4) System only : operating system protection

Base address Length Protec tionsegment

Base address

Length


12-21

128× 8RAM 1

C S1

AD7

WR

RD

C S2

128× 8RAM 2

C S1

AD7

WR

RD

C S2

128× 8RAM 4

C S1

AD7

WR

RD

C S2

128× 8RAM 3

C S1

AD7

WR

RD

C S2

128× 8ROM

C S1

C S2

AD9

Data

Data

Data

Data

Data

C PU

WRRD16 - 11 10 9 8 7 - 1

Address bus

Data bus

Decoder

3 2 1 0

1- 7

8

9

Chap. 12 Memory Organization

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