Ch 4. Combinational Logic Design Principles
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Transcript of Ch 4. Combinational Logic Design Principles
Ch 4. Combinational Logic Design Principles
• Combinational Logic Circuit– Outputs depend only on its current inputs– No feedback loop
• Sequential Logic Circuit– Outputs depend on its current inputs and present states– Feedback loop
4.1 Switching Algebra
‘+’ : ‘OR’
‘’ : ‘AND’
& are obvious (by perfect induction)
is identical to the distributive law for integers and reals
Switching-algebra theorems
NAND
DeMorgan’s Th.
NOR
DeMorgan’s Th.
Black box Representation with Truth table
Active Low
Active Low
Black box Representation with Truth table
DualityPositive Negative 𝑭 (𝑿𝟏 ,𝑿𝟐 ,… 𝑿𝒏 )⇒ 𝑭 𝑫 (𝑿𝟏
′ , 𝑿𝟐′ ,…𝑿𝒏′ )
𝑭 (𝑿𝟏 ,𝑿𝟐 ,… 𝑿𝒏 )=[𝑭 𝑫 (𝑿𝟏′ ,𝑿𝟐
′ ,…𝑿𝒏′ ) ]′
[𝑭 (𝑿𝟏 ,𝑿𝟐 ,…𝑿𝒏 ) ]′=[𝑭 𝑫 (𝑿𝟏′ , 𝑿𝟐
′ ,… 𝑿𝒏′ ) ]❑
→𝑮𝒆𝒏𝒆𝒓𝒂𝒍𝒊𝒛𝒆𝒅 𝑫𝒆𝑴𝒐𝒓𝒈𝒂𝒏′ 𝒔𝑻𝒉 .
𝑫𝒖𝒂𝒍𝒊𝒕𝒚
Function with 3 inputX, Y, Z
𝑭 (𝑿 ,𝒀 ,𝒁 )
𝑪𝒂𝒏𝒐𝒏𝒊𝒄𝒂𝒍 𝑺𝒖𝒎−𝑨𝒔𝒖𝒎𝒐𝒇 𝒎𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝒕𝒐𝒑𝒓𝒐𝒅𝒖𝒄𝒆𝒐𝒖𝒕𝒑𝒖𝒕𝒔 ′ 𝟏 ′
DeMorgan’s Th.
4.2 Combinational-Circuit Analysis
F(X, Y, Z)
F(X, Y, Z)
¿ 𝑿𝒁+𝒀 ′ 𝒁+𝑿 ′𝒀𝒁 ′
Three-level without considering inverter
(𝑽 ∙𝑾 ∙𝐗 )+ (𝐘 ∙𝒁 )=(𝑽 +𝒀 ) ∙ (𝑽 +𝒁 ) ∙ (𝑾 +𝒀 ) ∙(𝑾 +𝒁 )∙(𝑿+𝒀 ) ∙(𝑿+𝒁 )
“Add-out” to obtain a product of sums by T8’
T8’
Sum of products
Product of sums
(Figure 4-12)
(Figure 4-13)
Same
4.3 Combinational-Circuit Synthesis
Prime number detector
¿𝑷𝒂𝒏𝒊𝒄+𝑬𝒏𝒂𝒃𝒍𝒆 ∙𝑬𝒙𝒊𝒕𝒊𝒏𝒈 ′ ∙𝑺𝒆𝒄𝒖𝒓𝒆 ′
𝒏𝒐𝒏𝒔𝒕𝒂𝒏𝒅𝒂𝒓𝒅𝒈𝒂𝒕𝒆
𝒆𝒍𝒎𝒊𝒏𝒂𝒕𝒆𝒔 𝒏𝒐𝒏𝒔𝒕𝒂𝒏𝒅𝒂𝒓𝒅𝒈𝒂𝒕𝒆
NAND
NOR
𝐹= ∑𝑁3𝑁2𝑁1𝑁0
❑
(1,3,5,7,2,11,13 )
𝑮𝒓𝒂𝒚 𝑺𝒆𝒒𝒖𝒆𝒏𝒄𝒆
𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝑮𝒓𝒂𝒚 𝑺𝒆𝒒𝒖𝒆𝒏𝒄𝒆
𝒅𝒊𝒔𝒕𝒊𝒏𝒈𝒖𝒊𝒔𝒉𝒆𝒅𝟏−𝒄𝒆𝒍𝒍𝒔
𝑬𝑷𝑰
𝑬𝑷𝑰
4.4 Timing Hazards
𝑿𝒁𝑷=𝟏𝑿=𝟏
𝐘 𝒁=𝟎
Unwanted Output
Static-1 Hazard : Momentary output ‘0’ to occur during a transition in the differing input variable
Static-0 Hazard : Momentary output ‘1’ to occur during a transition in the differing input variable
Unwanted Output
𝑻𝒐𝒆𝒍𝒊𝒎𝒊𝒏𝒂𝒕𝒆 𝒔𝒕𝒂𝒕𝒊𝒄𝟏−𝒉𝒂𝒛𝒂𝒓𝒅