CENG 241Digital Design 1

Lecture 5

Amirali Baniasadi

amirali@ece.uvic.ca

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This Lecture

� Lab

� Review of last lecture: Gate-Level Minimization

� Continue Chapter 3:XOR functions, Hardware Description Language

� HW 2: Due Thursday May 31st.

� FIRST MIDTERM: THURSDAY JUNE 14, IN CLASS.

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Midterm 1

� CENG 241 Digital Design 1 Midterm #1 (sample)

� Important Note: Show your work for all sections.

� Consider the following Boolean function:

� F(A, B, C, D, E) = Σ (8,10,13,15,16,18,21,23,25,27) and d(A, B, C, D, E) = Σ (0,2,5,7,29,31)

� Use the 1’s in the map to find the simplest Boolean function and implementit using only NAND gates. Draw the logic.(10 points)

� Use the 0’s in the map to find the simplest Boolean function and implementit using only NOR gates. Draw the logic. (10 points)

� NOTE: Each gate may have up to 3 inputs.

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� Sum of Products and Product of Sums result in two level designs

� Not all designs are two-level e.g., F=A.(C.D+B)+B.C’

� How do we convert multilevel circuits to NAND circuits?

� Rules

� 1-Convert all ANDs to NAND gates with AND-invert symbol

� 2-Convert all Ors to NAND gates with invert-OR symbols

� 3-Check the bubbles, insert bubble if not compensated

Multilevel NAND circuits

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Multilevel NAND circuits

BC’

B’

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Multilevel NAND circuits

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Exclusive-OR Function

X XOR Y = X’.Y+X.Y’

two input XOR IS 1 if both inputs are not similar

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Three-input XOR Function

F = A XOR B XOR C

Multiple input XOR is 1 only if the number of 1 variables is odd: ODD function

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ODD Function Implementation

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Four-input XOR Function

F detects odd number of 1s, F’ detects even number of 1’s

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Parity Generation and Checking

� Parity bit: extra bit to ensure correct transmission of data

� Parity bit is included in the message to make the number of 1s either odd (odd parity) or even (even parity).

� We can use XOR to see if the number of 1’s is odd.

� We can use XOR-invert to see if the number of 1’s is even.

� We include the XOR output in the message

� Later at receiver we check the number of 1 bits to see if the transmission is correct.

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Parity Generation and Checking circuits

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� Hardware Description Language explains hardware in textual form

� Represents digital circuits

� HDL has two applications:

1-Simulation: represents structure and behavior of digital circuits

2-Synthesis:Derives a list of components and interconnections from HDL.

Two examples of HDL: VHDL, Verilog

We use verilog since its easier to learn.

Hardware Description Language

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Hardware Description Language-example

//HDL Example 3-1

//--------------------------

//Description of the simple circuit of Fig. 3-37

module smpl_circuit(A,B,C,x,y);

input A,B,C;

output x,y;

wire e;

and g1(e,A,B);

not g2(y, C);

or g3(x,e,y);

endmodule

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//HDL Example 3-2

//---------------------------------

//Description of circuit with delay

module circuit_with_delay (A,B,C,x,y);

input A,B,C;

output x,y;

wire e;

and #(30) g1(e,A,B);

or #(20) g3(x,e,y);

not #(10) g2(y,C);

endmodule

Hardware Description Language-example

How do we take into account gate delays?

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Test bench

� To simulate circuits we need input signals.

� The HDL description that provides the input/stimulus is called a test bench

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//HDL Example 3-3

//----------------------

//Stimulus for simple circuit

module stimcrct;

reg A,B,C;

wire x,y;

circuit_with_delay cwd(A,B,C,x,y);

initial

begin

A = 1'b0; B = 1'b0; C = 1'b0;

#100

A = 1'b1; B = 1'b1; C = 1'b1;

#100 $finish;

end

endmodule

//Description of circuit with delay

module circuit_with_delay (A,B,C,x,y);

input A,B,C;

output x,y;

wire e;

and #(30) g1(e,A,B);

or #(20) g3(x,e,y);

not #(10) g2(y,C);

endmodule

Test bench example

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Test bench example simulation output

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Combinational Logic

Combinational Logic: Output only depends on current input

Sequential Logic:Output depends on current and previous inputs

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Design Procedure

� 1.The number of inputs and outputs?

� 2.Derive the truth table

� 3.Obtain the Boolean Function

� 4.Draw the logic diagram, verify correctness

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Design Procedure example

� Binary Adder-Subtractor

� Basic block is a half adder.

� Half Adder Design:

� 1.needs 2 inputs 2 outputs

� 2. Truth Table:

x y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

� 3. S=x’y+xy’ C=xy

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Half Adder circuit

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Full Adder?

� Truth Table:

� x y z C S

� 0 0 0 0 0

� 0 0 1 0 1

� 0 1 0 0 1

� 0 1 1 1 0

� 1 0 0 0 1

� 1 0 1 1 0

� 1 1 0 1 0

� 1 1 1 1 1

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Full Adder Map

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Full Adder Circuit

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Full Adder Circuit

Half adder ?

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4-bit Adder Circuit

But this is slow...

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Summary

� Implementation, XOR, Parity Checking, HDL

� Reading up to page 121-end of chapter 3

� Homework 2: problems 3-11, 3-15, 3-20, 3-23 and 3-24 from textbook