CEI-56G-VSR Project Start Proposal - Parallax · PDF fileContribution Number: oif2012.088.03...
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Contribution Number: oif2012.088.03
Working Group: PLL
Title: CEI-56G-VSR Project Start Proposal
Meeting: Q2 2012
Source: Chris Cole
Finisar Corp
Sunnyvale, CA, USA
408 400-1043
Date: 26 April 2012
Abstract: Single lane electrical I/O data rates beyond 28Gb/s will be needed for future chip-to-
module applications, including single lane 40Gb/s, single and multi-lane 64G FC (Fibre Channel),
and ten or eight lane 400Gb/s modules. The proposed project will develop a single
Implementation Agreement with one or more electrical specifications for operation across a
single lane for data rates from 39 to 56 Gb/s. The project will determine the optimum modulation
format(s) based on measurements, verification, and CMOS Switch ASIC I/O capability.
Notice: This contribution has been created to assist the Optical Internetworking Forum (OIF). This document is offered to the OIF solely as a basis for discussion and is not a binding proposal on the companies listed as resources above. Each company in the source list, and the OIF, reserves the rights to at any time to add, amend, or withdraw statements contained herein. This Working Text represents work in progress by the OIF, and must not be construed as an official OIF Technical Report. Nothing in this document is in any way binding on the OIF or any of its members. The document is offered as a basis for discussion and communication, both within and without the OIF.
For additional information contact: The Optical Internetworking Forum, 39355 California Street,
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© 2012 Optical Internetworking Forum
2 26 April 2012 oif2012.088.03
CEI-56G-VSR Project Proposal
Supporters
Ghani Abbas, Ericsson
Jon Anderson, Opnext
Chris Bergey, Luxtera
Sudeep Bhoja, Inphi
Graeme Boyd, PMC-Sierra
Ralf-Peter Braun, DT
Paul Brooks, JDSU
Jeremy Buan, Hirose
Zeljko Bulut, NSN
Jean-Michel Caia, Cortina
Juan-Carlos Calderon, Cortina
Frank Chang, Vitesse
Kai Cui, Huawei
Dan Dove, Applied Micro
Katsumi Fukumitsu, Fujitsu
Contributors
Pete Anslow, Ciena
Chris Cole, Finisar
John D’Ambrosia*, Dell
Mike Dudek*, QLogic
Ali Ghiasi, Broadcom
Mark Gustlin, Xilinx
Scott Kipp, Brocade
Ryan Latchman, Mindspeed
Mike Li, Altera
Jeff Maki, Juniper
Steve Trowbridge, ALU
* Supports exploring 39 to 56 Gb/s
modulation formats in OIF Next Gen
Interconnect Framework Project
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CEI-56G-VSR Project Proposal
Hirokazu Hamada, Anritsu
Ziad Hatab, Vitesse
Kiyohisa Hiramoto, Opnext
Hideki Isono, Fujitsu
Toshiyasu Ito, Yamaichi
Jonathan King, Finisar
Monica Lazer, ATT
Zeng Li, Huawei
Arlon Martin, Kotura
Beck Mason, JDSU
Greg McSorley, Amphenol
Andy Moorwood, Infinera
Emmerich Mueller, Agilent
Yasunori Nagakubo, Fujitsu
Ed Nakamoto, Spirent
David Ofelt, Juniper
Petar Pepeljugoski, IBM
Jerry Pepper, Ixia
Sergio Prestipino, Exfo
Mike Shahine, Ciena
Song Shang, SemTech
Siddharth Sheth, Inphi
Vishnu Shukla, Verizon
David Sideck, FCI
Ted Sprague, Infinera
Atul Srivastava, NTT Electronics
Peter Stassar, Huawei
Nathan Tracy, TE
Francois Tremblay, SemTech
Eddie Tsumura, Sumitomo
John Wang, Broadcom
Chengbin Wu, ZTE
Pavel Zivny, Tektronix
4 26 April 2012 oif2012.088.03
Introduction
CEI-28G-VSR increased electrical lane data rate by 2.5x from CEI-
11G-SR, which increased CMOS Switch ASIC bandwidth and front
panel port density by 2.5x
In the future, CEI-28G-VSR electrical lane data rate will become a
limiting factor for CMOS Switch ASIC bandwidth and front panel port
density
The CEI-56G-VSR specification(s) will increase electrical lane data
rate by 2x from CEI-28G-VSR, which will increase CMOS Switch
ASIC bandwidth and front panel port density by 2x
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Fibre Channel Speed Roadmap
Towards
Bezel
FCIA Official Roadmap, v13, 2010, p.2
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40Gb/s Gen3 Serial Module I/O Support
Towards
Bezel
2016/2017 potential Gen3
40G Module (ex. CFP4)
40Gb/s single electrical lane
I/O (modulation TBD)
http://www.ieee802.org/3/ba/public/sep08/cole_02_0908.pdf, p.5
802.3ba Sept. 2008
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CFP MSA 40G & 400G Support Options
Towards
Bezel
http://www.cfp-msa.org/Documents/cole_EAb_OFC12.pdf , p.8
CFP4x4 electrical I/O: 16x25G (NRZ)
CFP4x4 electrical I/O: 10x40G (modulation TBD)
CFP2 electrical I/O: 8x50G (modulation TBD)
CFP4 electrical I/O: 1x40G (modulation TBD)
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Future OIF 400G IA Module I/O Support
Towards
Bezel
Possible future 400G IA Modules for OTU5 applications
Gen 1: CEI-28G-VSR (N = 16 lanes)
Gen 2: CEI-56G-VSR (N = 10 or 8 lanes)
Potential availability: 2016/2017
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Modulation Format Investigation
The optimum modulation format(s) for CEI-56G-VSR will be defined
based on the chip-to-module channel and implementation feasibility
The parameters that drive the definition(s) are:
• Loss
• Cross-talk
• Ripple
• Implementation power and complexity
CEI-28G-VSR channel has <11dB loss at 14GHz (NRZ Nyquist)
The ideal CEI-56G-VSR channel (dielectric and skin loss only, no
significant ripple) has <22dB loss at 28GHz (NRZ Nyquist)
Salz SNR bounds for ideal AWGN and X-talk channels are shown on
the following two pages
Ripple and other non-idealities significantly change Salz SNR bounds
Implementation power and complexity constrain what is realistic
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Salz SNR Bound for AWGN Channel
Towards
Bezel
www.ieee802.org/3/bj/public/mar12/cole_01a_0312.pdf, p.8
10
15
20
25
30
35
40
45
50
0 10 20 30 40 50
Sa
lz S
NR
(d
B)
IL at NRZ Nyquist (dB)
NRZ Dielectric Loss
PAM4 Dielectric Loss (-7dB)
NRZ Skin Loss
PAM4 Skin Loss (-7dB)
56G VSR NRZ Nyquist IL ideal limit
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Salz SNR Bound for X-talk Channel
Towards
Bezel
www.ieee802.org/3/bj/public/mar12/cole_01a_0312.pdf, p.11
10
15
20
25
30
35
40
45
50
0 10 20 30 40 50
Sa
lz S
NR
(d
B)
IL at NRZ Nyquist (dB)
NRZ Dielectric Loss
PAM4 Dielectric Loss (-7dB)
NRZ Skin Loss
PAM4 Skin Loss (-7dB)
56G VSR NRZ Nyquist IL ideal limit
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Measurement/Verification Challenges
NRZ requires channel measurements up to 3rd harmonic
• 40Gbaud → 60GHz
• 56Gbaud → 84GHz
V/1.8 mm connector bandwidth is limited up to 70 GHz
A new 1 mm connector with bandwidth up to 110 GHz is required
110GHz VNAs are costly
Current oscilloscope bandwidth is limited to 70 GHz
Current compliance test methodology may not scale to 56GBaud
because of PCB material non-idealities
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ITRS CMOS Process Technology Roadmap
The capability of CMOS Switch ASIC I/O will be an important factor in
modulation format(s) selection
CMOS International Technology Roadmap for Semiconductors, 2010
Update Overview:
www.itrs.net/Links/2010ITRS/2010Update/ToPost/2010_Update_Overview.pdf , p.3
ITRS Sponsoring Industry Associations (IAs): European
Semiconductor IA, Japan Electronics and Information
Technology Association, Korea Semiconductor IA,
Taiwan Semiconductor IA, (US) Semiconductor IA
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ITRS CMOS Functionality Roadmap
www.itrs.net/Links/2010ITRS/2010Update/ToPost/2010_Update_Overview.pdf , p.12
Projected
>2013 MPU
increases:
= 2x/3yrs
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Project Start Justification 1
Project name • CEI-56G-VSR
Problem statement
• By 2014, 28Gb/s per lane electrical I/O data rate will limit CMOS
Switch ASIC bandwidth and front panel port density, in some
applications
Scope • The Project will leverage CEI-28G-VSR material • The IA shall define electrical I/O lane(s) that support data rates
from 39 to 56Gb/s for chip-to-module interfaces • The IA will define the channel model based on the chip-to-module
applications • The IA shall define a compliance test methodology for chip-to-
module interface including a single connector • The IA will not define the Management Interface • The IA will not define the pin assignments or select a specific
connector
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Project Start Justification 2 Output
• Single IA specifying chip-to-module interface of 1 to N lanes
• One or more electrical specifications for operation across a single lane for speeds from 39 to 56 Gb/s
• Reach 0 to ~100mm (exact max reach TBD)
• Definition of compliance test methodology including test boards
Requirements
• Shall support AC coupling
• Capable of Bit Error Ratio of 1e-15 or better
• Document constraints of the chip-to-module application(s) used to derive the channel model specifications
Benefits to OIF
• Enable 64GFC modules
• Enable single lane electrical I/O 40Gb/s modules
• Enable 10 and 8 lane electrical I/O 400Gb/s modules
• Double CMOS Switch ASIC bandwidth
• Double front panel port density
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Project Start Justification 3 Relationships with other OIF working groups
• PLUG
• CEI-28G-VSR
• Next Gen Interconnect Framework Document
Relationships with other industry groups
• IEEE 802.3
• InfiniBand Trade Association
• Fibre Channel T11.2 Physical Layer Task Group
• SFF
• CFP MSA
Proposed Timeline
• Q3’12: Project Start
• Q4’13: Last New Proposals
• Q1’14: Select Technical Approach & Adopt Baseline Text
• Q2’14: Straw Ballot
• Q3’14: 2nd Straw Ballot
• Q4’14: Principal Member Ballot