CDA 4253 FGPA System Design Xilinx FPGA Memories
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CDA 4253 FGPA System DesignXilinx FPGA Memories
Hao ZhengComp Sci & Eng
USF
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Recommended Reading• 7 Series FPGA Memory Resources: User Guide
Google search: UG473• 7 Series FPGA Configurable Logic Block: User Guide
Google search: UG474• Xilinx 7 Series FPGA Embedded Memory Advantages:
White Paper
Google search: WP377• XST User Guide for Virtex-6, Spartan-6, and 7 Series
Device
Google search: UG687
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Memory Types
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Memory Types
Memory
RAM ROM
Single port Dual port
With asynchronous read
With synchronous read
Memory
Memory
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Memory Types Specific to Xilinx FPGAs
Memory
Distributed (MLUT-based)
Block RAM-based(BRAM-based)
Inferred Instantiated
Memory
Manually Using CORE Generator
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FPGA Distributed Memory7 Series FPGAs Configurable Logic Block User Guide
UG474 (v1.7) November 17, 2014
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Location of Distributed RAMRAM blocks
Multipliers
Logic blocks
Graphics based on The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
DSP unitsRAM blocks
Logic resources
(#Logic resources, #Multipliers/DSP units, #RAM_blocks)
Logic resources(CLB slices)
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7 Series FPGA CLB Resources
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7 Series FPGA Distributed RAM Config.
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Single-Port 64x1-bit Distributed RAM
Four of these signal port 64x1 RAMs can be implemented in a single SLICEM to form a 64x4b RAM.
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Dual-Port 64x1b Distributed RAM
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7 Series FPGA ROM Configurations on LUTs
Configuration Primitives:• ROM64X1• ROM128X1• ROM256X1
LUTs are often used to implemented small memories with less than 256 bits.
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FPGA Block RAM
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Location of Block RAMsRAM blocks
Multipliers
Logic blocks
Graphics based on The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
DSP unitsRAM blocks
Logic resources
(#Logic resources, #Multipliers/DSP units, #RAM_blocks)
Logic resources(CLB slices)
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7 Series FPGA Block RAM Resources
Each 36Kb block RAM can be configured as two independent 18Kb RAM blocks.
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Block RAM Configurations (Aspect Ratios)
0
32767
1
4,095
40
16383
20
4095
8+10
1023
32+40
32k x 1
16k x 2 8k x 4
4k x (8+1)
1024 x 36
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Block RAM InterfaceTrue Dual Port
Ports A and B are fully independent.
Each port has its own address, data in/out, clock, and WR enable.
Both read/write are synchronous.
Simultaneously writing to the same address causes data uncertainty.
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Block RAM InterfaceSimple Dual Port
Independent read/write ports.
Max port width is 64+8b.
Reading & writing to the same mem location causes data uncertainty.
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VHDL Coding for Memory
XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques Sections:
RAM HDL Coding TechniquesROM HDL Coding Techniques
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Distributed vs Block RAMs
• Distributed RAM: must be used for RAM descriptions with asynchronous read.
• Block RAM: generally used for RAM descriptions with synchronous read.
• Synchronous write for both types of RAMs.
• Any size and data width are allowed in RAM descriptions.- Depending on resource availability
• Up to two write ports are allowed.
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Inferring ROM
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Distributed ROM with Asynchronous Read
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity ROM is genetic ( w : integer := 12; -- number of bits per ROM word r : integer := 3 -- 2^r = number of words in ROM
); port ( addr : in std_logic_vector(r-1 downto 0); dout : out std_logic_vector(w-1 downto 0)); end ROM;
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Distributed ROM with Asynchronous Readarchitecture behavioral of ROM is type rom_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := ( "000011000100", "010011010010", "010011011011", "011011000010", "000011110001", "011111010110", "010011010000", "111110011111"); begin dout <= ROM_array(conv_integer(addr)); end behavioral;
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VHDL Code for Dual-Port ROM with Sync. Read
can be implemented either on LUTs or
block RAMs.
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VHDL Code for Dual-Port ROM with Sync. Read
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Inferring RAM
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Distributed Single-Port RAM with Async. Readlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 3 -- 2^r = number of words in RAM
); port ( clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr;
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Distributed Single-Port RAM with Async. Readarchitecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin
process (clk) begin
if rising_edge(clk) then if (we = '1') then RAM(conv_integer(a)) <= di; end if; end if; end process; do <= RAM(conv_integer(a)); end behavioral;
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Block RAM with Sync. Read (Read-First Mode)
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Block RAM with Sync. Read (Read-First Mode)
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Block RAM with Sync. Read (Read-First Mode)
process (clk) begin if rising_edge(clk) then if (en = '1') then do <= RAM(conv_integer(addr)); if (we = '1') then RAM(conv_integer(addr)) <= di; end if; end if; end if; end process;
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Block RAM with Sync. Read (Write-First Mode)
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Block RAM with Sync. Read (Write-First Mode)
process (clk) begin
if rising_edge(clk) then if (en = '1') then if (we = '1') then RAM(conv_integer(addr)) <= di;
do <= di; else do <= RAM(conv_integer(addr)); end if;
end if; end if;
end process;
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Block RAM with Sync. Read (No-Change Mode)
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Block RAM with Sync. Read (No-Change Mode)
process (clk) begin
if rising_edge(clk) then if (en = '1') then if (we = '1') then RAM(conv_integer(addr)) <= di; else do <= RAM(conv_integer(addr)); end if; end if; end if; end process;
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Block RAM Initialization
Example 1type ram_type is array (0 to 127) of std_logic_vector(15 downto 0); signal RAM : ram_type := (others => ”0000111100110101”;
Example 2type ram_type is array (0 to 127) of std_logic_vector(15 downto 0); signal RAM : ram_type := (others => (others => ‘1’));
Example 3type ram_type is array (0 to 127) of std_logic_vector(15 downto 0); signal RAM : ram_type := (196 downto 100 => X”B9B5”,
others => X”3344”);
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Block RAM Initialization from a File
rams_20c.data:001011000101111011110010000100001111101011000110011010101010110101110111…101011110111001011111000110001010000
128
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Block RAM InterfaceTrue Dual Port
Ports A and B are fully independent.
Each port has its own address, data in/out, clock, and WR enable.
Both read/write are synchronous.
Simultaneously writing to the same address causes data uncertainty.
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Dual-Port Block RAM
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Dual-Port Block RAM