Hao Zheng Comp Sci & Eng USF CDA 4253 FPGA System Design Chapter 5 Finite State Machines.
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Transcript of Hao Zheng Comp Sci & Eng USF CDA 4253 FPGA System Design Chapter 5 Finite State Machines.
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Hao ZhengComp Sci & Eng
USF
CDA 4253 FPGA System DesignChapter 5 Finite State Machines
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Required reading
P. Chu, FPGA Prototyping by VHDL Examples Chapter 5, FSM
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Datapath vs. Controller
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Structure of a Typical Digital System
Datapath(Execution
Unit)
Controller(Control
Unit)
Data Inputs
Data Outputs
Control & Status Inputs
Control & Status Outputs
Control Signals
StatusSignals
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Datapath (Execution Unit)• Manipulates and processes data.• Performs arithmetic and logic operations,
shifting/rotating, and other data-processing tasks.• Is composed of registers, multiplexers, adders,
decoders, comparators, ALUs, gates, etc.• Provides all necessary resources and
interconnects among them to perform specified task.
• Interprets control signals from the controller and generates status signals for the controller.
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Controller (Control Unit)
• Controls data movement in the datapath by switching multiplexers and enabling or disabling resources
Example: enable signals for registersExample: select signals for muxes
• Provides signals to activate various processing tasks in the datapath.
• Determines the sequence of operations performed by the datapath.
• Follows some ‘program’ or schedule.
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Programmable vs. Non-Programmable Controller• Controller can be programmable or non-programmable• Programmable
• Has a program counter which points to next instruction• Instructions are held in a RAM or ROM• Microprocessor is an example of programmable
controller• Non-Programmable
• Once designed, implements the same functionality• Another term is a “hardwired state machine,” or
“hardwired FSM,” or “hardwired instructions”• In this course we will be focusing on non-
programmable controllers.
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Finite State Machines
• Controllers can be described as Finite State Machines (FSMs)
• Finite State Machines can be represented using• State Diagrams and State Tables - suitable for simple
controllers with a relatively few inputs and outputs• Algorithmic State Machine (ASM) Charts - suitable
for complex controllers with a large number of inputs and outputs
• All of these descriptions can be easily translated to the corresponding synthesizable VHDL code
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Hardware Design with RTL VHDL
Pseudocode
Datapath Controller
Blockdiagram
Blockdiagram
State diagramor ASM chart
VHDL code VHDL code VHDL code
Interface
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Steps of the Design Process1. Text description2. Interface3. Pseudocode to describe functionality4. Block diagram of the Datapath5. Interface divided into Datapath and Controller 6. State diagram or ASM chart of the Controller7. RTL VHDL code of the Datapath, Controller, and Top-
Level Unit8. Testbench for the Datapath, Controller, and Top-Level
Unit9. Functional simulation and debugging10. Synthesis and post-synthesis simulation11. Implementation and timing simulation12. Experimental testing using FPGA board
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Finite State MachinesRefresher
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Finite State Machines (FSMs)• An FSM is used to model a system that transits
among a finite number of internal states. The transitions depend on the current state and external input.
• The main application of an FSM is to act as the controller of a medium to large digital system
• Design of FSMs involves• Defining states• Defining state transitions• Defining output functions• Optimization / minimization
• Manual optimization/minimization is practical for small FSMs only.
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Moore FSM
• Output is a function of the present state only
Stateregister
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
clockreset
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Mealy FSM• Output is a function of the present state and the
inputs.
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
Stateregister
clockreset
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State Diagrams
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Moore Machine
state 1 /output 1
state 2 /output 2
transitioncondition 1
transitioncondition 2
Transition conditions are defined on inputs.
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Mealy Machine
state 1 state 2
transition condition 1 /output 1
transition condition 2 /output 2
Transition conditions are defined on inputs.
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Moore FSM - Example 1
• Moore FSM that recognizes sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
S2: “10”observed
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Mealy FSM - Example 1• Mealy FSM that recognizes sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
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Moore & Mealy FSMs – Example 1
clock
input
Moore
Mealy
0 1 0 0 0
S0 S0 S1 S2 S0 S0
S0 S0 S1 S0 S0 S0
state
output
state
output
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Moore vs. Mealy FSM (1)
• Moore and Mealy FSMs can be functionally equivalent.• Equivalent Mealy FSM can be derived from Moore FSM
and vice versa.• Mealy FSM has richer description and usually
requires smaller number of states• Smaller circuit area.
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Moore vs. Mealy FSM (2)
• Mealy FSM computes outputs as soon as inputs change.• Mealy FSM responds one clock cycle sooner than
equivalent Moore FSM.• Moore FSM has no combinational path between
inputs and outputs.• Moore FSM is less likely to affect the critical path of the
entire circuit.
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Which Way to Go?
Safer.Less likely to affect
the critical path.
Mealy FSM Moore FSM
Lower Area
Responds one clockcycle earlier
Fewer states
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Finite State Machinesin VHDL
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FSMs in VHDL
• Finite State Machines can be easily described with processes.
• Synthesis tools understand FSM description if certain rules are followed.• State transitions should be described in a process
sensitive to clock and asynchronous reset signals only.• Output function described using rules for combinational
logic, i.e. as concurrent statements or a process with all inputs in the sensitivity list.
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Moore FSM
StateRegister
Next Statefunction
Outputfunction
Inputs
Present State
Next State
Outputs
clockreset
process(clock, reset)
concurrent statements
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Mealy FSM
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
StateRegister
clockreset
process(clock, reset)
concurrent statements
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Moore FSM - Example 1
• Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
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Moore FSM in VHDL (1)
type state IS (S0, S1, S2); -- enumeration typesignal Moore_state: state;
U_Moore: process (clock, reset)begin
if (reset = ‘1’) thenMoore_state <= S0;
elsif (clock = ‘1’ and clock’event) thencase Moore_state is
when S0 => if input = ‘1’ then
Moore_state <= S1; else Moore_state <= S0; end if;
S0 / 0 S1 / 0
0
1
next state logic
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Moore FSM in VHDL (2)
when S1 => if input = ‘0’ then
Moore_state <= S2; else Moore_state <= S1; end if;
when S2 => if input = ‘0’ then
Moore_state <= S0; else
Moore_state <= S1; end if;
end case;end if;
end process;
Output <= ‘1’ when Moore_state = S2 else‘0’;
next state logic
-- output function
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Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence “10”.
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
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Mealy FSM in VHDL (1)
type state IS (S0, S1);signal Mealy_state: state;
U_Mealy: process (clock, reset)begin
if (reset = ‘1’) thenMealy_state <= S0;
elsif (clock = ‘1’ and clock’event) thencase Mealy_state is
when S0 => if input = ‘1’ then
Mealy_state <= S1; else Mealy_state <= S0; end if;
next state logic
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Mealy FSM in VHDL (2)
when S1 => if input = ‘0’ then
Mealy_state <= S0; else Mealy_state <= S1; end if;
end case;end if;
end process;
Output <= ‘1’ when (Mealy_state = S1 and input = ‘0’) else‘0’; -- output function
next state logic
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Algorithmic State Machine (ASM)Charts
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Algorithmic State Machine
Algorithmic State Machine – representation of a Finite State Machine suitable for FSMs with a larger number of inputs
and outputs compared to FSMs expressed using state diagrams and state tables.
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Elements used in ASM charts (1)
Output signalsor actions
(Moore type)
State name
Condition expression
0 (False) 1 (True)
Conditional outputs or actions (Mealy type)
(a) State box (b) Decision box
(c) Conditional output box
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State Box• State box represents a state.• Equivalent to a node in a state diagram or
a row in a state table.• Contains register transfer actions or output
signals• Moore-type outputs are listed inside of
the box. • It is customary to write only the name of
the signal that has to be asserted in the given state, e.g., z instead of z<=1.
• Also, it might be useful to write an action to be taken, e.g., count <= count + 1, and only later translate it to asserting a control signal that causes a given action to take place (e.g., enable signal of a counter).
Output signalsor actions
(Moore type)
State name
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Decision Box
• Decision box indicates that a given condition is to be tested and the exit path is to be chosen accordingly.The condition expression may include one or more inputs to the FSM.
Condition expression
0 (False) 1 (True)
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Conditional Output Box
• Conditional output box denotes output signals that are of the Mealy type.
• The condition that determines whether such outputs are generated is specified in the decision box.
Conditional outputs or actions (Mealy type)
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ASMs Representing Simple FSMs
• Algorithmic state machines can model both Mealy and Moore Finite State Machines
• They can also model machines that are of the mixed type.
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Generalized FSM
Based on RTL Hardware Design by P. Chu
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Moore FSM – Example 2: State diagram
C z 1 = ¤
Reset
B z 0 = ¤ A z 0 = ¤ w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
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Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
Moore FSM – Example 2: State Table
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w
w
w 0 1
0
1
0
1
A
B
C
z
Reset
w
w
w 0 1
0
1
0
1
A
B
C
z
Reset
ASM Chart for Moore FSM – Example 2
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use ieee.std_logic_1164.all ;
entity simple isport( clock : in STD_LOGIC ;
resetn : in STD_LOGIC ; w : in STD_LOGIC ;
z : out STD_LOGIC ) ;end simple ;
architecture Behavior of simple is type State_type IS (A, B, C) ;signal state : State_type ;
beginprocess( resetn, clock )begin
if resetn = '0' thenstate <= A ;
elsif (Clock'EVENT and Clock = '1') then
Example 2: VHDL code (1)
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case state is when A =>
if w = '0' thenstate <= A ;
elsestate <= B ;
end if;when B =>
if w = '0' thenstate <= A ;
elsestate <= C ;
end if;when C =>
if w = '0' thenstate <= A ;
elsestate <= C ;
end if;end case;
Example 2: VHDL code (2)
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Example 2: VHDL code (3)
END IF ; END PROCESS ;
z <= '1' when state = C else '0' ;
END Behavior;
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A
w 0 = z 0 = ¤ w 1 = z 1 = ¤
B
w 0 = z 0 = ¤
Reset w 1 = z 0 = ¤
Mealy FSM – Example 3: State diagram
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ASM Chart for Mealy FSM – Example 3
w
w 0 1
0
1
A
B
Reset
z
A
w 0 = z 0 = ¤ w 1 = z 1 = ¤
B
w 0 = z 0 = ¤
Reset w 1 = z 0 = ¤
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library ieee;use ieee.std_logic_1164.all;
entity Mealy isPORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;end Mealy ;
architecture Behavior of Mealy istype State_type is (A, B) ;signal state: State_type ;
beginprocess ( resetn, clock )begin
if resetn = '0' thenstate<= A ;
elsif (clock'EVENT and clock = '1') then
Example 3: VHDL code (1)
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Example 3: VHDL code (2)
case state is when A => if w = '0' then
state<= A ;else
state<= B ;end if;
when B =>if w = '0' then
state<= A ;else
state<= B ; end if;end case;
end if;end process;
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Example 3: VHDL code (3)
z <= '1' when (y = B) and (w=‘1’) else '0' ;
end Behavior ;
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Control Unit Example: Arbiter (1)
Arbiter
reset
r1
r2
r3
g1
g2
g3
clock
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Idle
000
1--
Reset
gnt1 g 1 ¤ 1 =
-1-
gnt2 g 2 ¤ 1 =
--1
gnt3 g 3 ¤ 1 =
0-- 1--
01- -0-
001 --0
Control Unit Example: Arbiter (2)
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r 1 r 2
r 1 r 2 r 3
Idle
Reset
gnt1 g 1 ¤ 1 =
gnt2 g 2 ¤ 1 =
gnt3 g 3 ¤ 1 =
r 1 r 1
r 1
r 2
r 3
r 2
r 3
r 1 r 2 r 3
r 1 r 2
r 1 r 2 r 3
Idle
Reset
gnt1 g 1 ¤ 1 =
gnt2 g 2 ¤ 1 =
gnt3 g 3 ¤ 1 =
r 1 r 1
r 1
r 2
r 3
r 2
r 3
r 1 r 2 r 3
Control Unit Example: Arbiter (3)
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ASM Chart for Control Unit - Example 4
r 1
r 3 0 1
1
Idle
Reset
r 2
r 1
r 3
r 2
gnt1
gnt2
gnt3
1
1
1
0
0
0
g 1
g 2
g 3
0
0
1
r 1
r 3 0 1
1
Idle
Reset
r 2
r 1
r 3
r 2
gnt1
gnt2
gnt3
1
1
1
0
0
0
g 1
g 2
g 3
0
0
1
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Example 4: VHDL code (1)
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY arbiter ISPORT ( Clock, Resetn : IN STD_LOGIC ;
r : IN STD_LOGIC_VECTOR(1 TO 3) ; g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;
END arbiter ;
ARCHITECTURE Behavior OF arbiter ISTYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;SIGNAL state: State_type ;
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Example 4: VHDL code (2)BEGIN
PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THEN state <= Idle ;ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE state ISWHEN Idle =>
IF r(1) = '1' THEN state <= gnt1 ;ELSIF r(2) = '1' THEN state <= gnt2 ;ELSIF r(3) = '1' THEN state <= gnt3 ;ELSE state <= Idle ;END IF ;
WHEN gnt1 =>IF r(1) = '1' THEN state <= gnt1 ;ELSE state <= Idle ;END IF ;
WHEN gnt2 =>IF r(2) = '1' THEN state <= gnt2 ;ELSE state <= Idle ;END IF ;
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Example 4: VHDL code (3)WHEN gnt3 =>
IF r(3) = '1' THEN state <= gnt3 ;ELSE state <= Idle ;END IF ;
END CASE ;END IF ;
END PROCESS ;
g(1) <= '1' WHEN y = gnt1 ELSE '0' ;
g(2) <= '1' WHEN y = gnt2 ELSE '0' ;
g(3) <= '1' WHEN y = gnt3 ELSE '0' ;
END Behavior ;
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ASM Summary• ASM (algorithmic state machine) chart
– Flowchart-like diagram – Provides the same info as a state diagram– More descriptive, better for complex description– ASM block
• One state box• One or more optional decision boxes:
with T (1) or F (0) exit path• One or more conditional output boxes:
for Mealy output
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ASM Chart Rules
Based on RTL Hardware Design by P. Chu
• Difference between a regular flowchart and an ASM chart:– Transition governed by clock – Transition occurs between ASM blocks
• Basic rules:– For a given input combination, there is one
unique exit path from the current ASM block– Any closed loop in an ASM chart must
include a state box
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Incorrect ASM Charts
Based on RTL Hardware Design by P. Chu
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Generalized FSM
Based on RTL Hardware Design by P. Chu
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Case Study IDebouncing Circuit
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Original & Debounced Inputs
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Debouncing Circuit – Scheme 1
sw: input from slide switches or push buttons.
m_tick: output from a timer with 10ms period.
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Debouncing Testing Circuit
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Case Study IIFibonacci Number
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Fibonacci Number
if i = 0if i = 1
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Fibonacci Number
idle/rdy <=‘1’
done/done_tick <= ‘1’
op
n=0/t1 <= 0
n/=1/t1 <= t1+t0
t0 <= t1n <= n-1
n=1
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Alternative Coding Stylesby Dr. Chu
(to be used with caution)
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Traditional Coding Style
StateRegister
Next Statefunction
Moore Outputfunction
Inputs
Present State
Next State
clockreset
process(clock, reset)
concurrent statements
Mealy Outputfunction
Mealy Outputs Moore Outputs
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Alternative Coding Style 1
StateRegister
Next Statefunction
Moore Outputfunction
Inputs
Present State
Next State
clockreset
Process(Present State, Inputs)
Mealy Outputfunction
Mealy Outputs Moore Outputs
Process(clock, reset)
Process(Present State)Process(Present State, Inputs)
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Next state logic depends on mem, rw, and burst.
Moore output: re and we.
Mealy output: we_me that depends on mem and rw.
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Next state logic depends on mem, rw, and burst.
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Moore output: re and we.
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Mealy output: we_me that depends on mem and rw.
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Alternative Coding Style 2
Process(clk, reset)
Process(Present State,Inputs)
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VHDL Variables• Variables can be declared and used within processes.• Cannot be used outside processes.
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Differences: Signals vs Variables• Variables can only be declared and used within
processes or procedures.- Used to hold temporary results.
• Signals can only be declared in architecture.- Used for inter-process communications.
• Assignment to a variables occurs immediately.• Assignment to a signal occurs after a process is
executed.• Synthesis results:
- Variables: wires- Signals: wires, registers, or latches.
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Differences: Signals vs Variablesarchitecture sig_ex of test is process (clk) begin if rising_edge(clk) then out1 <= a and b; out2 <= out1 xor c; end if; end process;end sig_ex;
architecture var_ex of test is process (clk) variable out3 : std_logic_type; begin if rising_edge(clk) then out3 := a and b; out4 <= out3 xor c; end if; end process;end sig_ex;
FF
FF
AND
XOR
ab
c
out1
out2
ANDXOR
ab
cFF
out3
out4