Carry Lookahead Adder (CLA) - · PDF filecla1 Carry Lookahead Adder Notes cla1 Carry...

cla1 cla1Carry Lookahead Adder Notes

Carry Lookahead Adder (CLA)

A fast but costly adder.

Speed due to computing carry bit i without waiting for carry bit i − 1.

These Notes

Intended to supplement other sources.

For a basic introduction see Brown & Vranesic 3rd Edition Section 3.4.

Describe an ordinary (also called flat) and hierarchical CLA.

Provide simple delay and cost estimates.

The cost analysis for the hierarchical CLAs has been omitted for now.

cla1 LSU EE 3755 Lecture Transparency. Formatted 8:33, 23 April 2014 from cla. cla1

cla2 cla2

Carry Lookahead Cell (CLC)

a b

ai bi

CLC

CLCi

p

g

pi

gi

s

si

cci

Operates on single bits.

Ports for CLC i

Operands and Carry In

a, b, c

Sum

s = a ⊕ b ⊕ c.

Propagate Signal

p = a + b

Generate Signal

g = ab


cla3 cla3

a b

ai bi

CLC

CLCi

p

g

pi

gi

s

si

cci

CLC Important Features

There is no carry out.

Signal p and g do not depend on c.


cla4 cla4Overview of CLA

Structure of n-bit Carry Lookahead Adder

a0 b0

CLC0

p0

g0

s0

c0

CLC

a1 b1

CLC1

p1

g1

s1

c1

CLC

A

B

carr

y in

S

Carry Generation Logic

a2 b2

CLC2

p2

g2

s2

c2

CLC

an-1 bn-1

CLCn-1

pn-1

gn-1

sn-1

cn-1

CLC

cn

carry

out

g-1

Types of carry generation logic (CGL): lookahead and ripple.

With lookahead CGL adder above is a CLA.

With ripple CGL adder above is equivalent to a ripple adder.

Note: g−1 is used as a synonym for c0.


cla5 cla5Carry Generation Logic

Lookahead CGL for first three cells.

a0 b0

CLC0

p0

g0

s0

c0

CLC

a1 b1

CLC1

p1

g1

s1

c1

CLC

A

B

carr

y in

S

a2 b2

CLC2

p2

g2

s2

c2

CLC

a3 b3

CLC3

p3

g3

s3

c3

CLC

g-1


cla6 cla6

a0 b0

CLC0

p0

g0

s0

c0

CLC

a1 b1

CLC1

p1

g1

s1

c1

CLC

A

B

carr

y in

S

a2 b2

CLC2

p2

g2

s2

c2

CLC

a3 b3

CLC3

p3

g3

s3

c3

CLC

g-1

Boolean expressions for carry signals c0 to c3:

c0 = g−1.

c1 = g−1p0 + g0.

c2 = g−1p0p1 + g0p1 + g1.

c3 = g−1p0p1p2 + g0p1p2 + g1p2 + g2.


cla7 cla7

Generalization of Lookahead Carry Generation

c0 = g−1.

c1 = g−1p0 + g0.

c2 = g−1p0p1 + g0p1 + g1.

c3 = g−1p0p1p2 + g0p1p2 + g1p2 + g2.

Generalizing we get

ci = g−1p0p1 · · · pi−1 + g0p1p2 · · · pi−1 + g1p2p3 · · · pi−1 + · · · + gi−2pi−1 + gi−1

=i−1∑

j=−1

gj

i−1∏

k=j+1

pk


cla8 cla8CLA Delay Analysis

Delay Models

About These Models

Intended for hand analysis.

These models for making rough comparisons of different kinds of adders.

For example, ripple adder v. carry lookahead adder.

These models too crude for choosing between adders with delays within 40% of each other. . .

. . . in such cases write HDL descriptions . . .

. . . and use synthesis program to determine delays.


cla9 cla9

Unrealistic Delay Model

Easiest to use, but exaggerates performance of CLA.

n-input XOR Gate: tg = 2 delay units.

n-input AND, OR, NAND, NOR Gates: tg = 1 delay unit.

Conservative Delay Model

More tedious, understates performance of CLA.

n-input XOR Gate: tg = 2 lg n delay units.

n-input AND, OR, NAND, NOR Gates: tg = lg n delay units.


cla10 cla10

How To Analyze Delay of Combinational Circuit—A Review

Steps

(0) Mark all inputs to the circuit with time t = 0.

(1) If all gate outputs are marked with a time then go to step (2).

Otherwise, consider gates that do not have a time marked at their outputs . . .

. . . and find one in which all inputs are marked with a time.

Mark the output of the gate with time max{t1, t2, . . . , tn} + tg . . .

. . . where t1, . . . , tn are the times marked on the gate’s inputs . . .

. . . and tg is the delay of the gate based on the model in use.

Go to step (1).

(2) The circuit delay is the largest time assigned to a wire.


cla11 cla11CLA Delay Analysis

Critical (longest) Path

Starts at inputs, flows through p0 (or any other pi), cn−1, ending at sn−1.

You can follow along by following the red path!

a0 b0

CLC0

p0

g0

s0

c0

a1 b1

CLC1

p1

g1

s1

c1

CLC

A

B

carr

y in

S

an-1 bn-1

CLCn-1

pn-1

gn-1

sn-1

cn-1

g-1

cn

gn-2

pn-2

pn-3

gn-3

carry out

t=0

0+1

1+1

2+1

3+2

1+lg n

1+lg n+ lg n

1+2lgn+ 2

Unrealistic

Delay

Conservative

Delay

0+1

t=0

Unrealistic Delay

Conservative Delay

Red Wires on Critical Path

3+2lg n

5

Delays (longest

path to output).

gn-4


cla12 cla12

Critical (longest) Path:

a0 b0

CLC0

p0

g0

s0

c0

a1 b1

CLC1

p1

g1

s1

c1

CLC

A

B

carr

y in

S

an-1 bn-1

CLCn-1

pn-1

gn-1

sn-1

cn-1

g-1

cn

gn-2

pn-2

pn-3

gn-3

carry out

t=0

0+1

1+1

2+1

3+2

1+lg n

1+lg n+ lg n

1+2lgn+ 2

Unrealistic

Delay

Conservative

Delay

0+1

t=0

Unrealistic Delay

Conservative Delay


3+2lg n

5

Delays (longest

path to output).

gn-4

Generation of p and g:

Delay 1, Total 1

Generation of c:

Unrealistic: Delay 2, Total 3

Conservative: Delay 2⌈lg n⌉, Total 1 + 2⌈lg n⌉

Computation of s:

Unrealistic: Delay 2, Total 5

Conservative: Delay 2, Total 3 + 2⌈lg n⌉

Total Delay:

Unrealistic Model Delay: 5 gate delays.

Conservative Model Delay: 3 + 2⌈lg n⌉ gate delays.


cla13 cla13

Comparison

n-bit ripple: Delay 2n.

n-bit CLA: Delay 5 or 3 + 2⌈lg n⌉.

8-bit ripple: Delay 16.

8-bit CLA: Delay 5 or 8.





CLA looks much better. . .

. . . until we compute the cost!


cla14 cla14CLA Cost Analysis

Cost Model

Cost of a-input AND Gate: a − 1.

Cost of 3-input XOR Gate: 5


cla15 cla15

n-bit CLA Cost Analysis

Cost of each CLA Cell:

Sum︷︸︸︷

5 +

Gen.︷︸︸︷

1 +

Prop.︷︸︸︷

1 = 7

Cost of logic to compute ci given p and g signals:

OR Gate︷︸︸︷

i +

AND Gates︷︸︸︷

i+1∑

j=2

j − 1 = i +i(i + 1)

2=

i(i + 3)

2

Cost of logic to compute c1 to cn:

n∑

i=1

i(i + 3)

2=

1

6n(n + 1)(n + 5)

Cost of entire n-bit CLA

CLA Cells︷︸︸︷

7n +

Carry Gen Logic︷︸︸︷

1

6n(n + 1)(n + 5) ≈

n3

6


cla16 cla16CLA v. Ripple Cost Comparison

Cost of Selected Sizes

n-bit ripple: 10n

n-bit CLA: 7n + 1

6n(n + 1)(n + 5)

8-bit ripple: 80

8-bit CLA: 212 or 2.65× cost of ripple adder.

32-bit ripple: 320

32-bit CLA: 6736 or 21× cost of ripple adder.

64-bit ripple: 640

64-bit CLA: 48288 or 75× cost of ripple adder.


cla17 cla17Hierarchical CLA

Instead of using n 1-bit carry lookahead cells . . .

. . . use m l-bit Carry Lookahead Blocks. (Note that n = l × m.)

Structure:

a0 b0

CLB-x0

P0

s0

c0

CLB-x

a1 b1

CLB-x1

P1

G1

s1

c1

CLB-x

A

B

carr

y in

S


a2 b2

CLB-x2

P2

G2

s2

c2

CLB-x

a� � � b� � �

CLB-x� � �

P� � �

G� � �

s� � �

c� � �

CLB-x

c�

carry

out

G� �

G0

l bits

l bits

l bits

lm bits

lm bits

The CLB-x blocks can contain any kind of l-bit adder, including ripple and CLA.

Carry generation logic (CGL) can be ripple or lookahead.


cla18 cla18

Benefit of Hierarchical CLA

Since CGL and the logic to generate P and G operate on fewer bits . . .

. . . cost is lower.


cla19 cla19

We will consider two kinds of CLB-x modules:

CLB-c, in which the l-bit adder is a CLA.

CLB-r, in which the l-bit adder is a ripple adder.


cla20 cla20Carry Lookhead Block (CLB-x)

CLB-x contains an l-bit adder of type x (e.g., ripple or CLA). . .

. . . and logic to compute P and G.

a0

b0

a1

b1

al-1

bl-1

al-2

bl-2

bl-3

al-3

P

G

P�

G�l-bit

type-x

adder

CLB-x

CLB-x�

cinc�

s

s

a b

a b

B[(i+1)l-1:il]A[(i+1)l-1:il]

S[(i+1)l-1:il]

l bits

l bits

l bits of B from bit # il to bit # (i+1)l-1.


cla21 cla21

a0

b0

a1

b1

al-1

bl-1

al-2

bl-2

bl-3

al-3

P

G

P�

G �l-bit

type-x

adder

CLB-x

CLB-x �

cinc �

s

s

a b

a b

B[(i+1)l-1:il]A[(i+1)l-1:il]

S[(i+1)l-1:il]

l bits

l bits

l bits of B from bit # il to bit # (i+1)l-1.

CLB Propagate and Generate Outputs

Let gi = aibi and pi = ai + bi.

P =l−1∏

j=0

pj

= p0p1 · · · pl−1

G =

l−1∑

j=0

gj

l−1∏

k=j+1

pk

= g0p1p2 · · · pl−1 + g1p2p3 · · · pl−1 + · · · + gl−2pl−1 + gl−1

Notice that logic for G is almost the same as the logic for ci . . .

. . . an important difference is that the carry in is ignored.


cla22 cla22

Design Options for Hierarchical CLA

Value of l. (Since n is given, if we choose l that fixes m = n/l.)

Type of CLB: CLB-c (block uses l-bit CLA) or CLB-r (block uses l-bit ripple adder).

Type of CGL: lookahead or ripple.

Design Options Example

Given: We want a 32-bit adder, money is no object.

Choose l = 8, this fixes m = 4.

For CLB use a CLA.

For CGL use lookahead logic.

Are these good choices? To find answer need to analyze cost and performance.


cla23 cla23Hierarchical CLA Delay Analysis

Delay Analysis for Hierarchical CLA with CLB-r and lookahead CGL

Critical Path and delay under unrealistic and conservative models:

a0

b0

a1

b1

al-1

bl-1

al-2

bl-2

bl-3

al-3

a b

a0 b0

CLB-r0

P0

s0

c0

A

B

carr

y in

S


am-1

bm-1

CLB-rm-1

Pm-1

Gm-1

sm-1

cm-1 cm

carry

out

G-1

G0

l bits

l b

lm bits

3+2 = 5

1+2lg l + 2lgm = 1+2lglm

Unrealistic

Delay

Conservative Delay

a0

b0

a1

b1

al-1

bl-1

al-2

bl-2

bl-3

al-3

P

G

l-bit ripple adder

Gm-2

l bits

t=0

t=0

Unrealistic Delay

Conservative Delay

0+1+2lg l

0+3

5+2(l-1)

1+2lglm+2(l-1)


Delay of Entire Circuit

lm bits

Pm-3

l-bit ripple adder


cla24 cla24Hierarchical CLA Delay Analysis

Delays for m × l-bit Hierarchical CLA. (n = lm)

Hierarchical CLA with CLB-r and lookahead CGL

Unrealistic: 7 + 2(l − 1) gate delays

Conservative: 1 + 2 lg n + 2l gate delays

Hierarchical CLA with CLB-c and lookahead CGL

Unrealistic: 9 gate delays

Conservative: 3 + 2 lg l + 2 lg n gate delays

Hierarchical CLA with CLB-r and ripple CGL

Unrealistic: 1 + 2m + 2l gate delays

Conservative: 2 lg l + 2(m + l) gate delays

For details see Fall 2013 Homework 2 Solution.


cla25 cla25

Hierarchical CLA Cost Analysis

Omitted for now.


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