By P.-H. Lin, H. Zhang, M.D.F. Wong, and Y.-W. Chang

Presented by Lin Liu, Michigan Tech

Based on “Thermal-Driven Analog Placement Considering Device

Matching”

2

Rectangular devices and blocks

3

Id1 and Id2 are considered to be identical based on the common-centroid placement. With the thermal gradient, Id1 and Id2 may become mismatched.

Floorplan representations The absolute floorplan representation B*-tree, hierarchical B*-tree Sequence pair Transitive closure graphs Corner block list(CBL) for symmetry

constrains CBL and grid-based approaches for

common-centroid constrains

4

Among those works, only two addressed thermally constrained symmetric placement.

5

Propose the first thermal-driven analog placement considering thermal device matching

Simultaneously place all devices, including power devices and thermally-sensitive matched devices with either the symmetry or the common-centroid constraint.

6

Analog PlacementDesired Thermal ProfileThermal-driven analog placement

Conclusion

7

8

Which one is more preferable for analog circuits?Placement should be not just well packed, but also should include analog-specific features such as regularity.

Symmetry constraint

9

Common-centroid constraint

Lower temperature at thermal hot spots; Smoother thermal gradients at the non-

power device areas; More separation between power and

thermally-sensitive devices; More regular isothermal contours in either

the horizontal or the vertical direction such that the matched devices can easily be placed along the contours;

Larger accommodation areas for multiple thermally sensitive device groups.

10

11

Fig. 1(a) All power devices are evenly distributed at four sides of the chip.(b) All power devices are evenly distributed at two opposite sides of the chip.

12

Fig. 2(a) Thermal profile where power devices are evenly distributed at four sides of the chip. (b) Thermal profile where power devices are evenly distributed at two opposite sides of the chip.

(b) is more desirable

It is always recommended to place non-power, thermally sensitive devices as far away from power devices as possible to alleviate thermal impacts from power devices.

13

14

Fig. 3 Placement configurations of power device area arrangements.(a)Power device area is arranged at one short side of the chip. (b)Power device areas are arranged at both short sides of the chip.

Inputs and Constraints A set of device modules including power

and non-power devices; Power densities of all power devices; The targeted aspect ratio of the placement

area; Symmetry and common-centroid

constraints for all matching device groups;

15

16

Fig. 4 (a) Symmetric placement containing a symmetry group S0 ={bs3 , (b4, b4)}, and two non-symmetric modules, b1 and b2. (b) Corresponding HB*-tree and ASF-B*-tree of the placement in (a).(ASF-automatically symmetric-feasible)

17

Fig. 5 An example of SA based algorithm

18

Fig. 6 Placement configuration and its corresponding HB*-trees. (a)Placement configuration based on the power area arrangement in Fig. 3.(b)HB*-trees representing the topology among the three regions in (a).

Formulation min: cost function,

Ap -- Area of the bounding rectangle for the placement

Wp -- Half-perimeter wire lengthRp -- Difference between the aspect ratio of P and the

targeted aspect ratioTp -- Thermal cost of P

19

20

Tl,max and Tl,min denote the maximum and minimum temperatures at the left targeted isothermal contour;Tr,max and Tr,min denote the maximum and minimum temperatures at the right targeted isothermal contour.

The previous works computed the thermal profile by calculating approximated thermal equations based on different thermal models.

Although it is fast to compute the thermal

profile of a certain placement, it becomes inefficient during the simulated annealing process.

Look-up table to store the pre-simulated thermal profile.

21

22

Fig. 7 Coarse-grid and fine-grid thermal tables indicating the thermal profile of the power device with different precisions and scales.

Thermal Halo Allocation

23

Effectively reduce the temperature at the thermal hot spots

Global Thermal Profile Optimization

24

Coarse-grid thermal tables

Detailed Thermal Profile Optimization

Fine-grid thermal tables

Fig. 7 Placement of power devices is optimized based on (a) global and (b) detailed thermal profile optimization.

25

Symmetry device groups can simply be placed with their symmetry axes being perpendicular to the isothermal contours.

26

None of the previous works considers the thermal profile during the common-centroid placement.

27

Step 1: Pre-generate all possible common-centroid placements of each matching group

Step 2: Randomly select a candidate of the pre-generated placement when integrating with other devices

Step 3: Minimize the cost to get final candidates.

28

k-row TCCP Algorithm

Gcc = {b1, b2, . . . , bq}

Each device bj has nbj sub-devices with identical size

29

k-row TCCP Algorithm

Evenly distribute the sub-devices of each device along the direction of the thermal gradientMerge sub-devices on the same Eulerian trailThe column position of each sub-device in each row is assigned in a random order while keeping the symmetric row in the reverse order.

Address the thermal issue in analog placement and studied the thermal-driven analog placement problem.

Simultaneously optimize the placements of power and non-power devices to generate a desired thermal profile for thermally-sensitive matched devices.

Propose an analog placement methodology that considers the best device matching under the thermal profile while satisfying the symmetry and the common-centroid constraints.

30

31