BOOTH’S ALGORITHM DESIGN USING FIELD ... ALGORITHM DESIGN USING FIELD...multiplication [3]. This...

Webpage: www.ijaret.org Volume 2, Issue VII July 2014 ISSN 2320-6802

INTERNATIONAL JOURNAL FOR ADVANCE RESEARCH IN

ENGINEERING AND TECHNOLOGY WINGS TO YOUR THOUGHTS…..

Page 86

BOOTH’S ALGORITHM DESIGN USING FIELD

PROGRAMMABLE GATE ARRAY

A. Jaafar1, M. S. Omar

2, N. M. Z. Hashim

3, K. A. A. Aziz

4, N. A. A. Hadi

5

1, 2, 3 Centre for Telecommunication Research and Innovation (CeTRI) 4,5 Faculty of Electronic and Computer Engineering

Universiti Teknikal Malaysia Melaka (UTeM)

Hang Tuah Jaya 76100, Durian Tunggal, Melaka, Malaysia [email protected], [email protected], [email protected],

[email protected], [email protected]

Abstract: Nowadays, digital device is very important to all people in this world. The high speed operation and less

space and energy required had made the digital devices more preferred. This project is to design digital system

which performed fixed point Booth Multiplier Algorithm where the design system would be developed using

hardware description language (HDL), in this case, VHDL (VHSIC Hardware Description Language), VHSIC

stands for Very High Speed Integrated Circuit. In this project would be used Xilinx ISE 10.1which is the software

used to designed digital system for Xilinx manufactured FPGA board. In Xilinx have two main languages which are

VHDL and Verilog. For design Booth’s Multiplier Algorithm we used Verilog code which is has to create the

program module and test bench. In that case, to design digital system will have input and output which is input is 8

bits and output is 16 bits. Finally, it is proven that the system created can calculate and yield a fixed point multiplied

output of the input value.

Keywords: Booth’s Multiplier Algorithm, Hardware Description Language (HDL), VHSIC Hardware Description

Language (VHDL), Very High Speed Integrated Circuit (VHSIC, Xilinx

1. INTRODUCTION Addition and subtraction process for normal

computer is proceeds as if the two numbers were

unsigned integer. On any addition and subtraction,

the result may be larger than can be held in the word

size being used. This condition is call overflow.

When overflow occurs, the ALU must signal this fact

so that no attempt is made to use the result. Compare

with addition and subtraction, multiplication is a

complex operation whether performed in hardware or

software.

A wide variety of algorithms have been used in

various computers. The purpose of this subsection is

to give the reader some feel for the type of approach

typically taken. The system begin with the simpler

problem of multiplying to unsigned (non-negative)

integers, and then we look at one of the most

common techniques for multiplication of number in

two’s complement representation [1]. Booth

algorithms have three reasons that are looking here

by refer [1]. First, this will give you an example of an

algorithm which is in multiplication has an addition

and subtraction algorithm. In booth’s algorithm will

show the process of multiplier. Second, it will show

you one way a computer can do multiplication, given

only the kinds of functional units we have so far seen.

By design the multiplication algorithm, it can be

process to the hardware. Before implement to the

hardware, test the design by using Xilinx simulator

and check the functionality. Lastly, Booth’s

Algorithm is an example of how insights from

mathematics can lead to efficiency, albeit at the

expense of some increase in complexity. That mean

more arithmetic can be more complex circuit of

combinational logic gate.

Before discuss the booth algorithm, the first

important thing must know is the theory by refer [1],

the first digress for a moment to talk about how many

numbers are represented in computers. The subject is

considerably more complex than is presented here.

For instance, the design is not representing floating

point numbers [1].

Nowadays, digital system has been used in daily life

or industrial field because of the benefits compared

with analog system. Due to crucial developing of

digital system, many new complex digital devices

had been design. Some of the devices are called

microprocessor, microcontroller or microchip. It is

very important to have a very high speed

performance in all the devices. Booth Multiplier is

one of the most important parts in the devices which

can affect the performance of the devices.

So, the high speed and efficient multiplier system is

important for the designers of microprocessor,




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microcontroller and others digital devices. As we

know, multiplication algorithm can be operating on

binary, decimal and hexadecimal number. But, to do

the operation in binary number is very complex

operation. This project is being done to help design

or create a prototype of digital system design that can

operate as multiplier operation that would be

implemented into microprocessor, microcontroller

and other digital devices.

This project is more towards on implement

multiplication technology with using FPGA as a

device for design booth’s algorithm. The first

objective of this project is to design a digital

multiplier using Booth Multiplier Algorithm in

Verilog. The second objective is to design the booth’s

algorithm in two integer complement multiplication.

Finally, the system that has design will implement to

the FPGA trainer.

2. LITERATURE REVIEW Table 1 show that the Booth Multiplier Algorithm

Operation, which very important for this project. The

algorithm rules give a procedure for multiplying

binary integers in signed –2’s complement

representation. By follow this table, to design Booth

Multiplier system make easier to understand the

concept [2].

Table 1: Booth’s Multiplier Algorithm Operation

A A-1 Operation

0 0 Shift Right

0 1 A = A + M and Shift Right

1 0 A = A – M and Shift Right

1 1 Shift Right In the process of addition the multiple numbers of

times is repeated. From the system, the number that is

added is defined by multiplicand and the number of

times it has to be added is given by multiplier [3].

The project of the multiplier must achieved the

maximum speed in the multiplier hence, generation

of partial product and adding if partial product must

be optimized [3]. The multiplication perform on

signed binary number and unsigned multiplication is

perform on unsigned binary number is called a sign

multiplication [3]. This project is to modified booth’s

algorithm in order to improve the performance which

is high speed by reducing the product array

multipliers [3].

Based on Figure 1; this is the process of booth’s

multiplier. In this block diagram, the input of

multiplicand and multiplier is connecting to the

control system. In multiplier the most significant bit

is Xn which is the value can be added by 1 and the

least significant bit is 0. The number of multiplicand

must in two’s complement or signed number. The

two’s complement happen when the value is

negative. When this process is happening the value

must inverted and adds to 1. Then, see the process of

shifting in booth’s bit. The process of shifting will

shift to right until get the partial product. The product

will save into control [4].

Figure 1: Booth’s Multiplier Block Diagram

Hearing aids are one of many modems, portable,

digital systems requiring power efficient design in

order to give the life of the battery. Hearing aids are a

typical example of a portable device. They include

digital signal processing algorithms, which demands

considerable computing power. Yet miniature pill

sized batteries store to small amount of energy,

limiting their lifetime [5]. Hearing impairment is

often accompanied with reduced frequency

selectivity which leads to a decreased speech

intelligibility in noisy environments. One possibility

to alleviate this efficiency is the spectral sharpening

for speech enhancement based on adaptive filtering

the important frequency contributions. for

intelligibility in the speech are identified and

accentuated [5]. This work discusses the power

consumption in an FPGA implementation of the

speech enhancement algorithm. It point out that

power consumption can be reduce using Booth

Wallace Multiplier [5].

To ease the computational burden, the real-time

implementation of the hearing aid utilizes a spectral

sharpening and noise reduction due to spectral

sharpening design for the signal processing, which is

illustrated in Figure 2.2, 2.3 respectively. The input

signal comes in on the upper left side of the figure, is

sampled at a rate of 8 kS/s, and is delivered to the

high pass filter and the filtered signal is used for

updating the filter coefficients [5].

Based on Figure 2, the output of the analysis filter is

passed through synthesis filter and then to the

speaker. The speech enhancement usually results

from adaptively filtering the noise signals and

subtracting from the primary input by using high pass

filter. In the proto type implementation, the high pass

filter with 6 taps, FIR filter was designed with cut off

frequency 1k Hz.




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Figure 2: The Spectral Sharpening Filter for Speech

Enhancement

Based on the Figure 3, the noise reduction can be

reducing by using high pass filter. The adaptive

decorrelator will process by using Laplace Transform

to reduce the noise from speaker. Hardware

multiplication is necessary in any system that

contains Digital Signal Processing (DSP)

functionalities.

Figure 3: Spectral Sharpening for Noise Reduction

2.1. Multiplier Background

The shifts add Multiplier scheme is the most basic of

unsigned integer multiplication algorithm. This

algorithm uses addition and shift left operation to

calculate the product of two numbers. Two examples

are presented based on Table 2. The unsigned shift

and add is a basic multiplication the user can go

through any two multi digit numbers. When the

function is critical, the numbers of DSP on an FPGA

can be exhausted [6].

The left example shows the multiplication procedure

of two unsigned binary digits while the one on the

right is for signed multiplication. The first digit is

called multiplicand and the second multiplier. The

only difference between signed and unsigned

multiplication is that have to extend the sign bit in the

case of signed one, as depicted in the given right

example in PP row 3 [5].

Table 2: Examples of two’s complement

multiplication

Based on Figure 4, the process of the signed

multiplication algorithm will check MSB of sign of

digit. On the check MSB it has a three process which

is negative results, positive results and calculate

partial product. After calculate the partial product it

will do the final process which is addition. The

product will get in 8 bit output. From the flowchart, it

has using two’s complement to get the partial

product. When the MSB is ‘0’ it will display positive

result otherwise when the MSB is ‘1’ it will display

negative result.

Figure 4: Signed and unsigned multiplication

algorithm

2.2. Partial Product Generation

Partial product generation is the very first step in

binary multiplier. These are the intermediate terms

which are generated based on the value of multiplier.

If the multiplier bit is ‘0’, then partial product row is

also zero, and if it is ‘1’, then the multiplicand is

copied as it is. From the 2nd bit multiplication

onwards, each partial product row is shifted one unit

to the left as shown in the above mentioned example.

For signed multiplication, the sign bit is also

extended to the left. Partial product generators for a

conventional multiplier consist of a series of logic

AND gates based on Figure 5.

Figure 5: Partial Product of Generation Logic




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The main operation in the process of multiplication

of two numbers is addition of the partial products. To

achieve higher performance, the multiplier must be

pipelined. This is accomplished in a multiplier by

breaking the carry chain and inserting flip-flops at

strategic locations. Care must be taken that all inputs

to the adder are created by signals at the same stage

of the pipeline. Delay at this point is referred to as

latency [5].

3. METHODOLOGY

This project is to implementing and designing a

booth’s encoder and decoder for the multiplier [1].

The project has implemented the booth’s multiplier

according to the steps in the algorithm.

3.1. Design flow

Based on the Figure 6, the first step is to design the

booth’s algorithm by using the Xilinx ISE 10.1. After

design the system synthesizes the program. Second

step compile the program by check the syntax of

behavioral. Third step by using the Xilinx ISE

simulator, simulate the test bench program and check

the output. After that create a pin input output on

floor plan area and generate a map. Download the

program to the FPGA trainer and verify the input and

output.

Figure 6: Design flow

3.2. The Verilog Hardware Description

Language

Verilog Hardware Description Language (VHDL) is

commonly used as a design entry-language for FPGA

and application. Specific design integrated circuits in

electronic design automation of digital circuits.

VHDL is a fairly general-purpose language, although

it requires a simulator on which to run the code. It

can read and write files on the host computer, so a

VHDL program can be written that generates another

VHDL program to be integrated in the design being

developed. The advantage of VHDL when used for

systems design is that it allows the behavior of the

required system to be described and simulated

synthesis tools translate the design into real hardware

[7].

Based on Figure 7, this document uses short

examples to demonstrate the basic Verilog syntax,

time delays, and concurrent execution features. We

have tried to condense all the interesting and hard

parts of Verilog into 15 pages and skip all of the

boring stuff like what is the difference between real

and integer data types. Studying this document will

enable you to model circuits using simple structural

and behavioral Verilog code and provide a solid

framework for learning all the details of the language

[7].

In Verilog it has two types on design the system

which is structural model and behavioral modal.

Verilog is a great low level language. Structural

models are easy to design and Behavioral RTL code

is pretty good. The syntax is regular and easy to

remember. It is the fastest HDL language to learn and

use. However Verilog lacks user defined data types

and lacks the interface-object separation of the

VHDL's entity-architecture model.

VHDL is good for designing behavioral models and

incorporates some of the modern object oriented

techniques. Its syntax is strange and irregular, and the

language is difficult to use. Structural models require

a lot of code that interferes with the readability of the

model [7].

Figure 7: The part of Verilog

3.2.1. Switch Level

Based on Figure 8, Transistor and storage nodes in a

device and the connections between them are

described. Modeling transistor networks at the switch

level more accurately represents their operation.

Verilog provides unidirectional and bidirectional

primitives that you can use to model the switch

network [8]. The example program below is the type

of unidirectional primitives:

Figure 8: Switch Level Programs

3.2.2. Gate Level

Based on Figure 9, Logic gates and the connections

between them are described. There are 14 different

primitive gates in Verilog which is 8 are for logic

function, 4 for modeling tri state signals and 2 are

enhance signal strength [8]. Example Program:




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Figure 9: Gate Level Programs

3.2.3. Register Transfer Level (RTL)

Based on Figure 10 the Register Transfer Level

(RTL) design has techniques that are emphasized. In

essence, an RTL design signifies the placement in the

design and flow of data among the registers. The

flow of data between registers and the processing of

that data is described. This is a state machine

implementation [9]. Example Program:

Figure 10: Register Transfer Level Programs

3.2.4. Algorithmic

Based on Figure 11, the Algorithmic is the function

that using the logic gate and function of the

mathematical. This system can be using the

behavioral modelling. A design algorithm is

described in high level language constructs [8].

Example Program:

Figure 11: Algorithmic Programs

3.3. Overall Methodology

This project is design by using Xilinx ISE 10.1

software. Based on Figure 12, for the first block of

flowchart is design a Booth’s Algorithm using

Verilog program. Design the pattern module of

booth’s algorithm by creates a new Verilog HDL.

Design the test bench by creates a new test texture

Verilog HDL.

Next block is run the simulation using Xilinx System

Generator. If the system have no error it will during

download process else have error, check the design

and correct the error and simulate once time. After

simulate the program burn the program into FPGA by

configure the bit file to target device. Create the pin

input output on the FPGA by set to the floor plan

area.

Figure 12: Flowchart of design the project [10-27]

After done download the program, on the FPGA

trainer check the input and output that will displays.

Test one by one the input and check the displays. If

the result is not correct, design again the system.

4. RESULT AND DISCUSSION In this project to be able to design the Booth’s

Algorithm using Field Programmable Gate Array. To

get the project complete, use the Xilinx Integrated

Software Environment 10.1 software. This software

is dividing by two types of language which is VHDL

and Verilog language. This project will be design

using Verilog Algorithm and simulate using Xilinx

ISE Simulator.

4.1. Simulation for Booth Multiplier

This is the block diagram for the Booth’s Algorithm

by using Xilinx ISE 10.1.To show this block

diagram, in Xilinx software click the View RTL

schematic. The project design 4 inputs and 2 outputs

that the input present by multiplicand, multiplier, clk,

and start and the output will present by product and

busy. The multiplicand and multiplier will be present

by 4 bit input and the output will be present by 8 bit

output.

Based on Figure 13 the parameter mc and mp will

declare as multiplicand and multiplier. On the block




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diagram has a 2 input that will declare as 4 bit else

the output will declare as 8 bit. The function of

counter is to get the expected result. The process will

run four times to complete the operation. The last

output is LED_COM that are function as to display

on FPGA.

Figure 13: The original Block Diagram of Booth’s

Multiplier

In Figure 14 it will show the complex circuit inside

the booth’s algorithm block diagram. At the tool

processes in Xilinx have shown the view of RTL

schematic. To show the circuit, clicks the View RTL

Schematic and the schematic will be show based on

the Figure 14. Inside the each block have a logic

circuit. This circuit will use four flip flops because

the system will design 4 bit.

On the schematic circuit has a arithmetic logic unit

and has four flip flops which is each flip flop has 4

bit design. The flip flop will set by counter when a

counter will enter, the system will function. The

counter will run 4 times to make the final result when

finish count; it will reset and set the new value. The

process will repeat until the button reset will press.

Arithmetic logic will be function as subtraction and

addition. When the systems do the process of

subtraction it wills 0 and 1 and when the systems do

the process of addition it will be in value 1 and 0.

Figure 14: RTL Schematic Diagram inside the block

diagram of Booth’s Multiplier

Inside the flip flop A1_mux0000<0> have a

combinational of gate logic AND/ OR. In this

schematic have four flip flop design in which for

each flip flop have combinational gate logic based on

Figure 15.

Figure 15: Combinational Logic Gate

In the program that are design have an Arithmetic

Logic Unit (ALU) program which is have two type

adder and subtraction. The main functions of the

ALU are to do arithmetic and logic operations,

including bit shifting operations. Recall that

subtraction means adding the two’s complement

which is a – b = a + (-b) = a + (inverted b +1) based

on Figure 16.

Figure 16: Block Diagram for ALU

On Figure 17, the output works in behavioral

simulation. On this project, assume three inputs and

three outputs. From the example (-4) x 5 and the

answer is -20. Before get the answer there has to shift

to the right four times. If the parameter is 00 the

process is shift to the right. If the parameter 01 the

process is add for example A0 <= A0 + A3 and shift

to the right. If the parameter is 10 the process is

subtract for example A0 <= A0 – A3 and shift to the

right. If the parameter is 11 the processes do nothing

and shift to the right.

Figure 17: The result of Simulate the Behavioral

Model




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4.2. Hardware Implementation for Booth’s

Multiplier

A Field Programmable Gate Array is an integrated

circuit that could contain millions of logic gates that

can be electrically configured to perform a certain

task. For this project use the FPGA trainer because

the basic nature of FPGA allows it to be more

flexible than other devices. FPGA devices can

reprogrammed to do any logic task that can be

change the number of gates that it has.

On the board, push button is the input and the LED is

a display. When inside the value on the push button

the result will be display on LED. To make the value

shift, other button will add on board. The button is

call pulse button which is functioning when click the

pulse button the value will shift and click once more

time the value will shift until the value count four

times.

Figure 18: The Hardware Implementation

4.3. Discussion

This project is using the Xilinx ISE 10.1 software.

The system is design by using Verilog program and

Verilog testbench. This project design 4 input and 2

output which is the input present by multiplicand,

multiplier, clk and start and the output will present by

product and counter. The multiplicand and multiplier

will present by 4 bit input and the output will be

present by 8 bit output. This project will use the

process of addition and subtraction. When the

parameter is 01 it will do subtraction process and

shift to the right. When the parameter is 10 it will do

addition process and shift to the right and else when

the parameter is 00 and 11 the process just shift to the

right only. After finish design the algorithm, the

algorithm need to implemented on hardware which is

FPGA. Check the result by refers the FPGA trainer

that has been program.

5. CONCLUSIONS AND FUTURE

WORK The experiment that have done, we have proposed

and designed a Verilog program to implementation of

FPGA based on digital system which produces the

expected results because of various benefit like lower

power and higher efficiency. The purpose of this

project is to design a 4 by 4 bit booth’s multiplier

using the Xilinx ISE 10.1 software. On design a 4 by

4 bit booth’s multiplier, by using the method of

addition, subtraction and shifting can make the

system more efficient. The booth’s multiplier was

designed by using the Verilog coded and simulated

the design by using ISE simulator was achieved. On

this project, it should compare the speed between

addition, subtraction and booth’s algorithm. By

design booth’s algorithm and implemented on FPGA,

it can be see how it work on FPGA. After finish

design the program it was do the process of

synthesize using devices target and place and route

was also performed the input and output for a

particular Xilinx device. The program was

downloaded to the FPGA and the objective was

achieved.

For the future, the booth’s algorithm is recommended

to be designed 16 by 16 bit multiplier and 32 by 32

bit multiplier that will increases the speed of the

devices. Furthermore, changes of the display on 7

segments and LCD display on the FPGA board also

are recommended. FPGA can be used widely to build

the new technology and make the FPGA most

popular in the world.

Acknowledgments We are grateful to Centre for Telecommunication

Research and Innovation (CeTRI) and Universiti

Teknikal Malaysia Melaka (UTeM) through

PJP/2013/FKEKK (47B)/S01274 for their kind and

help for supporting financially and supplying the

electronic components and giving their laboratory

facility to complete this study.

References [1] M. Z. A. Khan, H. Saleem, S. Afzal, and J.

Naseem, “An Efficient 16-Bit Multiplier based on

Booth Algorithm,” vol. 1, no. 6, pp. 6–8, 2012.

[2] A. Getahun, “Booth Multiplication Algorithm,”

pp. 1–3, 2003.

[3] M. Chaudhary and M. S. Narula, “FPGA

Implementation of Booth’ s and Baugh - Wooley

Multiplier Using Verilog,” no. 1, pp. 221–224,

2013.

[4] S. Hegde and S. S. Navalgund, “Implementation of

Binary Multiplication using Booth and Systolic

Algorithm on FPGA using VHDL,” pp. 30–33,

2012.

[5] Engineering, “FPGA Implementation of an

Adaptive Hearing aid Algorithm Using Booth

Wallance Multiplier FPGA Implementation of an

Adaptive Hearing Multiplier,” 2007.




Page 93

[6] A. Sayed and M. Aly, “A Study of Large Width

Unsigned Multipliers on FPGAs,” vol. 5, no. 1, pp.

5–8, 2013.

[7] W. U. Verilog and M. Verilog, “Digital Design Lab

Manual 2011 Introduction to Verilog Digital

Design Lab Manual 2011,” pp. 1–48, 2011.

[8] Assoc. P. Dr. A. S. Jamal,” Digital Integrated

Circuit Design”, January 2011

[9] A. Jaafar, N. Arasid, N. M. Z. Hashim, A. A.

Latiff, and H. Rafis, "Three Bit Subtraction

Circuit via Field Programmable Gate Array,"

International Journal for Advance Research in

Engineering and Technology (IJARET), vol. 1. no.

8, pp. 1-13, 2013.

[10] N. M. Z. Hashim, M. H. A. Halim, H. Bakri, S. H.

Husin, and M. M. Said, “Vehicle Security System

Using Zigbee,” Int. J. Sci. Res. Publ., vol. 3, no. 9,

pp. 1–6, 2013.

[11] N. M. Z. Hashim, N. A. Ali, A. Salleh, A. S.

Ja’afar, and N. A. Z. Abidin, “Development of

Optimal Photosensors Based Heart Pulse

Detector,” Int. J. Eng. Technol., vol. 5, no. 4, pp.

3601–3607, 2013.

[12] N. M. Z. Hashim and N. B. Hamdan, “Flood

Detector Emergency Warning System,” Int. J.

Eng. Comput. Sci., vol. 2, no. 8, pp. 2332–2336,

2013.

[13] N. M. Z. Hashim, N. M. T. N. Ibrahim, Z.

Zakaria, F. Syahrial, and H. Bakri, “Development

New Press Machine using Programmable Logic

Controller,” Int. J. Eng. Comput. Sci., vol. 2, no. 8,

pp. 2310–2314, 2013.

[14] N. M. Z. Hashim, S. H. Husin, A. S. Ja’afar, and

N. A. A. Hamid, “Smart Wiper Control System,”

Int. J. Appl. or Innov. Eng. Manag., vol. 2, no. 7,

pp. 409–415, 2013.

[15] N. M. Z. Hashim, A. F. Jaafar, Z. Zakaria, A.

Salleh, and R. A. Hamzah, “Smart Casing for

Desktop Personal Computer,” Int. J. Eng.

Comput. Sci., vol. 2, no. 8, pp. 2337–2342, 2013.

[16] A. Salleh, N. R. Mohanad, N. M. Z. Hashim, M. Z.

A. A. Aziz, and M. H. Misran, “Design of

Wideband Microstrip Bandpass Filter for S-Band

Application,” Aust. J. Basic Appl. Sci., vol. 8, no.

4, pp. 843–848, 2014.

[17] S. H. Husin, A. A. Ngahdiman, N. M. Z. Hashim,

Y. Yusop, and A. S. Ja,afar, “Home Electrical

Appliances Smart System,” Int. J. Comput. Sci.

Mob. Comput., vol. 2, no. 9, pp. 85–91, 2013.

[18] A. S. Ja’afar, N. M. Z. Hashim, A. A. M. Isa, N. A.

Ali, and A. M. Darsono, “Analysis of Indoor

Location and Positioning via Wi-Fi Signals at

FKEKK , UTeM,” Int. J. Eng. Technol., vol. 5, no.

4, pp. 3570–3579, 2013.

[19] N. R. Mohamad, A. S. A. M. Soh, A. Salleh, N. M.

Z. Hashim, M. Z. A. A. Aziz, N. Sarimin, A.

Othman, and Z. A. Ghani, “Development of

Aquaponic System using Solar Powered Control

Pump,” IOSR J. Electr. Electron. Eng., vol. 8, no.

6, pp. 1–6, 2013.

[20] N. M. Z. Hashim and N. Arifin, “Laboratory

Inventory System,” Int. J. Sci. Res. (IJSR …, vol.

2, no. 8, pp. 261–264, 2013.

[21] N. M. Z. Hashim, N. A. Ibrahim, N. M. Saad, F.

Sakaguchi, and Z. Zakaria, “Barcode Recognition

System,” Int. J. Emerg. Trends Technol. Comput.

Sci., vol. 2, no. 4, pp. 278–283, 2013.

[22] N. M. Z. Hashim and S. N. K. S. Mohamed,

“Development of Student Information System,”

Int. J. Sci. Res., vol. 2, no. 8, pp. 256–260, 2013.

[23] A. Salleh, N. R. Mohamad, M. Z. A. A. Aziz, M. N.

Z. Hashim, M. H. Misran, and M. A. Othman,

“Design the High Gain and Low Power Amplifier

for Radio over Fiber Technology at 2 . 4 GHz,”

no. 09, pp. 163–170, 2013.

[24] N. M. Z. Hashim, N. H. Mohamad, Z. Zakaria, H.

Bakri, and F. Sakaguchi, "Development of

Tomato Inspection and Grading System using

Image Processing," International Journal Of

Engineering And Computer Science (IJECS), vol.

2 no. 8, pp. 2319-2326, 2013.

[25] A. Salleh, N. R. Mohamad, A. M. Aziz, M. H.

Misran, M. A. Othman, and N. M. Z. Hashim,

"Simulation of WiMAX System Based on OFDM

Model with Difference Adaptive Modulation

Techniques," International Journal of Computer

Science and Mobile Computing, vol. 2 no. 9, pp.

178-183, 2013.

[26] S. H. Husin, M. Y. N. Hassan, N. M. Z. Hashim,

Y. Yusop, A. Salleh, "Remote Temperature

Monitoring and Controlling," International

Journal for Advance Research in Engineering and

Technology (IJARET), vol. 1. no. 8, pp. 40-47,

2013.

[27] A. Salleh, M. Z. A. Abd Aziz, N. R. Mohamad, M.

H. Misran, M. A. Othman, N. M. Z.

Hashim,"Simulation of 2.4 GHz Low Power RF

Front End Design for Radio over Fiber

Technology," International Journal of Emerging

Trends in Engineering and Development, vol. 5,

no. 3, pp. 345–354, 2013.

http://ijaret.org/REMOTE%20TEMPERATURE.pdf

http://ijaret.org/REMOTE%20TEMPERATURE.pdf

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