Book Review Article
1
Book review Wafer-Level Chip-Scale Packaging (Analog and Power Electronics Packaging), XVII. Springer (2015). 322 pp., ISBN: 978-1-4939-1555-2 (Print) 978-1-4939-1556-9 (Online) Wafer Level Chip-Scale Packaging by Qu, Shichun, Liu, Yong presents good technical insights of wafer-level chip scale packaging (WLCSP) technology, suitable for both industry and academic practitioners. The authors provide insights on the broad values and fundamentals of wafer level packaging and technical applications in this book. The authors summarize the overall trends of wafer-level chip-scale packaging and highlight the design, assembly processes and chip-scale package designs with reliability test methods. The authors reviewed the overview of the demand and challenges for analog and power WLCSP, in Chapter 1. The main challenges and im- pact of due to die shrinkage are reviewed. The development of power WLCSP is explained. Basic concepts of fan-in and fan-out WLCSP, bumping process flow, design considerations, and reliability assessment are explained in Chapter 2 and Chapter 3. Chapter 2 covers the overall WLCSP bumping processes and costing strategy and provides us the considerations for WLCSP package development. Detailed board level drop test and temperature cycling stress requirements are discussed in Chapter 2. It also reveals some of the different approaches for designs of redistribution layer (RDL). The remainder of this book builds on the future of fan-out WLCSP technology and trends of development in Chapter 3. Chapter 4 presents the stackable packaging solutions involving WLCSP. The multichip module packages, stacked ide package and stacked package, wafer level three dimensional integration and embed- ded WLCSP are covered in this Chapter. In Chapter 4, the authors discuss various types of achieving package miniaturization through three di- mensional integrated circuit (IC) integration, stacked die package and stacked packages, 3 dimensional IC, thru-silicon via (TSV) and embed- ded WLCSP. It presents the various options and driving forces of package miniaturization through different stackable packaging solutions and technologies. Beyond these stackable packaging solutions and other package min- iaturization such as power MOSFET WLCSP is covered in Chapter 5. The authors discuss the details of wafer level discrete power MOSFET pack- age design considerations. Design considerations such as discrete power WLCSP design constructions, wafer-Level MOSFET direct drain design, power VDMOSFET WLCSP with Cu Stud Bumping, 3D power module with embedded WLCSP are explained in Chapter 5. Design concept of integration of analog and power solution, are discussed in Chapter 6. Key topics such as wafer-level power stack die 3D package with TSV, wafer-level TSV or stack die concept for analog and integration of power packaging with active and passive chips are provided. Chapter 7 is all on the critical topics of thermal management, design, and analysis for WLCSP. This chapter is very helpful for thermal analysis and thermal modeling of power WLCSP. It focuses on methods of ther- mal management which covers thermal resistance and measurement methods, thermal analysis and management for WLCSP and provides with transient thermal analysis for WLCSP. The electrical simulation for example electrical simulation for a fan-out molded chip scale pack- age is discussed in Chapter 8. Chapter 9 explains on the details of assem- bly processes of WLCSP devices which includes PCB designs, solder paste selection, component placement, fluxing, solder reflow recipes and WLCSP underfill. It provides the in-depth critical process parame- ters to industrial practitioners on WLCSP process development. Lastly, the authors describe in details on reliability and general testing of WLCSP semiconductors include WLCSP board level drop test, WLCSP design for reliability in Chapter 10. In summary, the book gives wide perspectives on the technical in- sights of wafer-level chip scale packaging interconnect system and reli- ability testing in industry while adding very valuable industry insights. It is a good reference to demonstrate the alternate wafer-level chip scale packaging, and can serve as a very informative technical reference. It was a single example of package miniaturization used to demonstrate many benefits of WLCSP. The book is valuable as a learning tool for WLCSP and its clear relevance to real-world industry practices make it useful for both students and reliability practitioners. Valuable as a learn- ing tool for wafer-level chip scale interconnect technology, its clear rel- evance to real world industry practices make it useful for both academics and semiconductor industry practitioners. Chong Leong Gan SanDisk Storage Malaysia Sdn. Bhd., Penang, Malaysia Institute of Nano Electronic Engineering, Universiti Malaysia Perlis, Malaysia Corresponding author. E-mail address: [email protected]. Uda Hashim SanDisk Storage Malaysia Sdn. Bhd., Penang, Malaysia Microelectronics Reliability 55 (2015) 2481 http://dx.doi.org/10.1016/j.microrel.2015.08.007 0026-2714/© 2015 Elsevier Ltd. All rights reserved. Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr
-
Upload
chong-leong-gan -
Category
Engineering
-
view
115 -
download
0
Transcript of Book Review Article
Microelectronics Reliability 55 (2015) 2481
Contents lists available at ScienceDirect
Microelectronics Reliability
j ourna l homepage: www.e lsev ie r .com/ locate /mr
Book review
Wafer-Level Chip-Scale Packaging (Analog and Power ElectronicsPackaging), XVII. Springer (2015). 322 pp., ISBN: 978-1-4939-1555-2(Print) 978-1-4939-1556-9 (Online)
Wafer Level Chip-Scale Packaging byQu, Shichun, Liu, Yong presentsgood technical insights of wafer-level chip scale packaging (WLCSP)technology, suitable for both industry and academic practitioners. Theauthors provide insights on the broad values and fundamentals ofwafer level packaging and technical applications in this book. Theauthors summarize the overall trends of wafer-level chip-scalepackaging and highlight the design, assembly processes and chip-scalepackage designs with reliability test methods.
The authors reviewed the overview of the demand and challengesfor analog and powerWLCSP, in Chapter 1. Themain challenges and im-pact of due to die shrinkage are reviewed. The development of powerWLCSP is explained. Basic concepts of fan-in and fan-out WLCSP,bumping process flow, design considerations, and reliability assessmentare explained in Chapter 2 and Chapter 3. Chapter 2 covers the overallWLCSP bumping processes and costing strategy and provides us theconsiderations for WLCSP package development. Detailed board leveldrop test and temperature cycling stress requirements are discussedin Chapter 2. It also reveals some of the different approaches for designsof redistribution layer (RDL). The remainder of this book builds on thefuture of fan-out WLCSP technology and trends of development inChapter 3.
Chapter 4 presents the stackable packaging solutions involvingWLCSP. The multichip module packages, stacked ide package andstacked package, wafer level three dimensional integration and embed-dedWLCSP are covered in this Chapter. In Chapter 4, the authors discussvarious types of achieving package miniaturization through three di-mensional integrated circuit (IC) integration, stacked die package andstacked packages, 3 dimensional IC, thru-silicon via (TSV) and embed-dedWLCSP. It presents the various options and driving forces of packageminiaturization through different stackable packaging solutions andtechnologies.
Beyond these stackable packaging solutions and other packagemin-iaturization such as power MOSFETWLCSP is covered in Chapter 5. Theauthors discuss the details of wafer level discrete power MOSFET pack-age design considerations. Design considerations such as discrete powerWLCSP design constructions, wafer-Level MOSFET direct drain design,power VDMOSFET WLCSP with Cu Stud Bumping, 3D power modulewith embedded WLCSP are explained in Chapter 5. Design concept ofintegration of analog and power solution, are discussed in Chapter 6.Key topics such as wafer-level power stack die 3D package with TSV,
http://dx.doi.org/10.1016/j.microrel.2015.08.0070026-2714/© 2015 Elsevier Ltd. All rights reserved.
wafer-level TSV or stack die concept for analog and integration ofpower packaging with active and passive chips are provided.
Chapter 7 is all on the critical topics of thermalmanagement, design,and analysis forWLCSP. This chapter is very helpful for thermal analysisand thermal modeling of power WLCSP. It focuses on methods of ther-mal management which covers thermal resistance and measurementmethods, thermal analysis and management for WLCSP and provideswith transient thermal analysis for WLCSP. The electrical simulationfor example electrical simulation for a fan-out molded chip scale pack-age is discussed in Chapter 8. Chapter 9 explains on the details of assem-bly processes of WLCSP devices which includes PCB designs, solderpaste selection, component placement, fluxing, solder reflow recipesand WLCSP underfill. It provides the in-depth critical process parame-ters to industrial practitioners on WLCSP process development. Lastly,the authors describe in details on reliability and general testing ofWLCSP semiconductors include WLCSP board level drop test, WLCSPdesign for reliability in Chapter 10.
In summary, the book gives wide perspectives on the technical in-sights of wafer-level chip scale packaging interconnect system and reli-ability testing in industry while adding very valuable industry insights.It is a good reference to demonstrate the alternate wafer-level chipscale packaging, and can serve as a very informative technical reference.It was a single example of packageminiaturization used to demonstratemany benefits of WLCSP. The book is valuable as a learning tool forWLCSP and its clear relevance to real-world industry practices make ituseful for both students and reliability practitioners. Valuable as a learn-ing tool for wafer-level chip scale interconnect technology, its clear rel-evance to real world industry practices make it useful for bothacademics and semiconductor industry practitioners.
Chong Leong GanSanDisk Storage Malaysia Sdn. Bhd., Penang, Malaysia
Institute of Nano Electronic Engineering, Universiti Malaysia Perlis,Malaysia
Corresponding author.E-mail address: [email protected].
Uda HashimSanDisk Storage Malaysia Sdn. Bhd., Penang, Malaysia
