Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution Beyond CMOS CTSG IRC Meeting...
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Transcript of Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution Beyond CMOS CTSG IRC Meeting...
Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution
Beyond CMOS CTSG IRC Meeting
December 15, 2009
DRAFT
Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution
Objectives Beyond CMOS CTSG IRC FxF Meeting
Dec.15, 2009
♦ Follow up discussion of shared treatment of Alternate Channel Materials – Transfer to PIDS
♦ Mention new Emerging Research Architectural planning underway for the 2011 ERD Chapter
♦ Discuss ERD/ERM Workshops planned for 2010.– Memory Technology Assessment– Emerging Research Architectures– Emerging Research Devices – Hi Perf Computing– Emerging Research Devices – More than Moore
ITRS 2009 Exec. Summary Propoals Draft – Nov 2009Work in Progress – Do Not PublishSource: 2009 ITRS – ERD/ERM/PIDS/FEP Proposal for
Production Ramp-up Model &Technology Cycle Timing Proposal [Example: III-V MOSFET Channel Replacement Materials]
1K
10K
100K
Months-72
1M
10M
100M
Alpha
Tool
0 24-48
Development Production
Beta
Tool
Product
Tool
Vol
ume
(Waf
ers/
Mon
th)
2
20
200
2K
20K
200K
-24
Research
-96
Transfer to PIDS/FEP(96-72moLeadtime)
First Tech. Conf.
Device PapersUp to ~12yrs
Prior to Product
20192017201520132011 2021
III/V Hi- gateExample:
1st 2Cos.
Reach
Product
First Tech. Conf.
Circuits PapersUp to ~ 5yrs
Prior to Product
Rev 3Hutchby
ITRS 2009 Exec. Summary Propoals Draft – Nov 2009Work in Progress – Do Not PublishSource: 2009 ITRS – ERD/ERM/PIDS/FEP Proposal for
Production Ramp-up Model &Technology Cycle Timing Proposal [Example: III-V MOSFET Channel Replacement Materials]
1K
10K
100K
Months-72
1M
10M
100M
Alpha
Tool
0 24-48
Development Production
Beta
ToolProduct
Tool
Vol
ume
(Waf
ers/
Mon
th)
2
20
200
2K
20K
200K
-24
Research
-96
Transfer to PIDS/FEP(96-72moLeadtime)
First Tech. Conf.
Device PapersUp to ~12yrs
Prior to Product
20192017201520132011 2021
III/V Hi- gateExample:
1st 2Cos.
Reach
Product
First Tech. Conf.
Circuits PapersUp to ~ 5yrs
Prior to Product
Rev 4Hutchby
Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution
Major Challenges of III-V MOSFETs♦ High K Gate Dielectric
♦ Passivation of High-K / III-V Semiconductor Interface
♦ Integration of Ge and III-V Compound Semiconductor on Silicon
♦ P-Channel III-V MOSFET or N-Channel Ge MOSFET
Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution
Issues Related to III-V MOSFETs♦ Impact of parasitics on I-V Characteristics
• Effect of source resistance
• Ballistic model for III-V FETs: role of Density-of-States
• Ballistic FET I-V characteristics: InGaAs & Si
• Quasi-Ballistic I-V characteristics: InGaAs & Si♦ Impact of parasitics on switching behavior
• Estimation of switching behavior
• Switching behavior of quasi-ballistic FETs: InGaAs & Si♦ Performance projection with scaling
• Dimensional scaling
• Supply voltage scaling♦ Drain leakage current
Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution
ERM ChallengesGe & III-V
• Growth of low defect III-Vs on silicon• Co-integration of Ge & III-Vs
– Ge dopant activation at higher temperatures– III-V doping of Ge
• Growth of a high quality high κ dielectric on Ge & III-Vs– Passivation of the interface
Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution
ERD & ERM Alternate Channel Assessments
• Ge p-FET• III-V n-FET• Ge p-FET & III-V n-FETs (Separate
Assessment?)• Nanowire FETs• Graphene FETs• Carbon Nanotube FETs
Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution
III-V Ge Alternate Channel Partition Proposal
ERM
Materials, Interfaces & Process Issues & Challenges
Critical Assessment of Materials & Integration Capabilities
ERD
Integrated Device Performance Assessment & Challenges
(For different structures surface, buried channel, etc.)
Critical Assessment of Device Performance
PIDS
III-V & Ge Potential Solution
SiGe P-FET with Si N-FET
Collaborate with ERD on device Readiness
FEP
Potential Solution: SiGe P-FET with Si N-FET
III-V & Ge Potential Solution
Track III-V & Ge Issues
Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution
ERD Recommendation
ERD recommends to PIDS and FEP that we transfer the III-V and Ge Alternate Channel Materials Technology Element to PIDS and FEP in 2011
Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution
2009 Emerging Architectures Benchmarking
Memory
Morphic
Thermodynamic
Beyond CMOS CTSG Dec. 15, 2009 Work in Progress: Not for Distribution
Proposed ERD/ERM Workshops
Workshop Topic Location Date
Memory Assessment Lake Marjorie, Italy April 6-7, 2010
Emerging Architectures San Francisco, CA ITRS Dates in July, 2010
Emerging Devices for Hi Performance Computing
Seville, Spain Sept. 17, 2010
Emerging Devices for More than Moore
Tokyo, Japan Winter ITRS – Dec. 2010