Behavioral Modeling of Data Converters using Verilog-A

George Suárez

Graduate StudentElectrical and Computer EngineeringUniversity of Puerto Rico, Mayaguez

Code 564: Microelectronics and Signal

Processing Branch

NASA Goddard Space Flight Center

2NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

Introduction Verilog-A Objectives Sample and Hold

Analysis Jitter Noise Thermal noise Model Simulation results

Generic DAC Analysis and model Dynamic element matching Simulation results

3NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

Generic ADC Analysis and model Simulation results

Flash ADC Analysis and model Simulation results

SAR ADC Analysis and model Simulation Results

Pipelined ADC Analysis 1.5 bit Stage

- 1.5 bit ADC

4NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

- 1.5 bit MDAC

Digital Correction Simulation results

ΣΔ ADC ΣΔ Modulator

- SC integrator analysis

- Model

- Simulation results

Conclusions Future Work Acknowledgements References

5NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Introduction

Transistor-level modeling and simulation is the most accurate approach for mixed-signal circuits.

It becomes impractical for complex systems due to the long computational time required.

Cell ViewNo. of

TransistorsNo. of

EquationsSimulation Time

Transistor Level

436 1111 52 s

7000 17601125 ks

1 day, 10 hours, 42 min.

Taken form the article: Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A Nitin Mohan, Sirific Wireless www.techonline.com

6NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Introduction

This situation has led circuit designers to consider alternate modeling techniques:

In addition, behavioral modeling can be effectively used in a top-down design approach.

Approach Accuracy Speed Flexibility

Device models Custom C++ models

Finite-difference equations Circuit-based macromodels Time-domain macromodels

Behavioral models

Cell ViewNo. of

TransistorsNo. of

EquationsSimulation

Time

Transistor Level

436 1111 52 s

Behavioral 270 697 4 s

Transistor Level

7000 17601

125 ks1 day, 10 hours, 42

min.

Behavioral 439 1148 124s

www.techonline.com Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A, Nitin Mohan, Sirific Wireless

7NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Introduction

Loop filterF(s)

Phasecomparator

VCO

A=1

fo

System Level(Matlab, C++, SystemC, AHDLs, etc…)

Functional Level(SPICE, AHDLs)

Transistor Level(SPICE)

Layout

Top-Down Design Approach

Behavioral models

+

- Vout

Vin

A=1

+

-

V +V -

8NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Verilog-A

The Verilog-A is a high-level language developed to describe the structure and behavior of analog systems and their components.

It is an extension to the IEEE 1364 Verilog HDL specification for digital design.

The analog systems are described in Verilog-A in a modular way using hierarchy and different levels of modeling complexity.

The motivation is to invest in a new higher level of abstraction in analog design and its combination with the digital one.

`include "constants.vams"`include "disciplines.vams"

module COMP (vin, vref, vout);output vout;electrical vout;input vin;electrical vin;input vref;electrical vref;parameter real slope = 100.0;parameter real offset = 0.0 ;

vin

vref

vout

9NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Objectives

Build a set of analog and mixed-signal behavioral models using the Verilog-A AHDL, that allows a high level simulation of ADCs.

Simulate some popular ADCs architectures such as: Flash ADC SAR ADC Pipelined ADC

Simulate other common used mixed-signal circuits such as: ΣΔ Modulator Sample and Hold

Provide a general modeling approach for noise sources and other non-idealities.

Provide performance results for the simulated data converters such as spectrum measures SNR, SNDR, THD etc.

10NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

Introduction Verilog-A Objectives Sample and Hold

Analysis Jitter Noise Thermal noise Model Simulation results

Generic DAC Analysis and model Dynamic element matching Simulation results

11NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Sample and Hold

• Finite DC gain A0

• Finite GBW

• Cp and CL

• Defective settling • Linear• Slewing • Partial Slewing

Ron

1 – exp[-t / (2RonCs)]

Φs1

Jitterδ

x(t+δ) - x(t) ≈ δ x(t) dt

d

Thermal noiseVth ≈ kT/Cs

(Opamp noise neglected)

εg= 1 - Cs /[ Cs + (Cs + Cp)/A0]

Cp

CL

+

-

Vin

Vout

Cs

Φs1

ps

sp

2p

p

p2

2p

CC

CGBW2πω

ωsQ

ωs

ωH(s)

Vou

t

Time

Ideal value

|H|

f

Φs1

12NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Clock jitter is due to the non-uniform sampling of the input signal.

The magnitude of this error is a function of the statistical properties of the jitter and the input signal to the system.

In sampled data systems, when a sinusoidal input is taken, the error introduced by jitter can be modeled by,

Jitter Noise

x(t+δ) - x(t) ≈ 2πfinδAcos(2πfinnt) ≈ δ x(t) dt

d

δ

where δ is the sampling uncertainty, this is taken to be a Gaussian random process with standard deviation Δt.

ΔV

13NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Jitter Noise It is assumed that is a Gaussian random process with zero mean and standard deviation Δt.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 106

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

Ma

gn

itu

de

(d

B)

3.01MHz301 kHz30.1kHz

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 106

-140

-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

Ma

gn

itu

de

(d

B)

100 ps1 ns10 ns

Δt

-Δt

Statistical properties of the jitterInput signal to the system

14NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Thermal Noise

0 0.5 1 1.5 2 2.5 3 3.5 4

x 106

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

Ma

gn

itud

e (

dB

)

27 oC 0 oC-30 oC

1.98 2 2.02 2.04 2.06 2.08 2.1

x 106

-132

-131

-130

-129

-128

-127

-126

-125

-124

-123

Frequency (Hz)

Ma

gn

itud

e (

dB

)

27 oC 0 oC-30 oC

Thermal noise in circuits is because of the random fluctuation of carriers due to thermal energy.

Proportional to the temperature.

It is assumed to be a Gaussian random process with zero mean.

15NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Sample and Hold model

Ideal S&H

+JitterDefective

settlingVout

Vou

t

IdealNonideal

ThermalNoise

Vin τ = RonCs

Filter

16NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

0 0.5 1 1.5 2 2.5

x 107

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

Ma

gn

itu

de

(d

B)

IdealNonideal

Sample and Hold simulation results

PSD for sampled signal of 0 dB, fin = 2.5146MHz N = 8192, BW = 25MHz

Increase in noise floor due nonidealities

17NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

Introduction Verilog-A Objectives Sample and Hold

Analysis Jitter Noise Thermal noise Model Simulation results

Generic DAC Analysis and model Dynamic element matching Simulation results

18NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Generic DAC

Mismatch in DAC units. INL Gain error Offset

MSB27C 26C 22C 21C C C

Dummy

VinVref

Gnd

-

+

SAR Capacitive DAC, SAH and comparator

Mismatch in capacitors!(trimming can reduced it to 0.1%Increase in harmonics content)

0 0.5 1 1.5 2 2.5

x 105

-140

-120

-100

-80

-60

-40

-20

0

0.0% DAC mismatch DEM off0.1% DAC mismatch DEM off

Mag

nit

ud

e (

dB

)

Frequency (Hz)

unit

unit

unit

…unit

Vout+

Generic DAC model including mismatch in units

2B-1

0

1

2B-2

The

rmom

eter

dec

oder

B bits

19NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Integral non-linearityINL

Quantization stepq

Gain errorεg

Full scale voltageFS

Offset errorεoff

nominal gaing

α(wa + off) ya

1/(1+q εg)α

(2N-1-1)qA

FS/(2N-1)q

(1- ε0)xa + xa3 ε0/A2wa

(INL)sqrt(27)/(2N-2)ε0

(l1 εg-εoff)qoffset

-FS/(2g)l1

Generic DAC model

DACwith

mismatch+

N bits

α

offset

xa wavavadc

Digital input code

Ana

log

outp

ut

INL = 0.5LSB

Gain error = 0.5LSB

IdealNonideal

Offset error = 0.5LSB

20NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Dynamic Element Matching (DEM) techniques are used to minimize the effect of DAC units mismatch.

DAC DEM techniques can be divided in deterministic and stochastic.

Due to design complexity and non-scalability for modeling purposes it is easier to implement a general stochastic approach using randomization.

DEM

Improve the DAC performance by locating the distortion caused by the

component mismatch errors in certain frequency bands.

Ma

gn

itude

(d

B)

f (Hz) f (Hz)

Ma

gn

itude

(d

B)

Spread the mismatch error energy across the spectrum

generating white or colored noise in the DAC output.

Ma

gn

itude

(d

B)

f (Hz)

Ma

gn

itude

(d

B)

21NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

0 0.5 1 1.5 2 2.5

x 105

-140

-120

-100

-80

-60

-40

-20

0

0 0.5 1 1.5 2 2.5

x 105

-140

-120

-100

-80

-60

-40

-20

0

0.1% DAC mismatch DEM on

0.1% DAC mismatch DEM off

Mag

nitu

de (d

B)

Frequency (Hz)

DAC 0.1% mismatch

DEM off

DEM on

DEM simulation results

By randomizing the DAC units (i.e. using a digital circuitry FSM with a system clock) the effect of the mismatch in the spectrum is reduced by reducing the harmonic distortion.

In Verilog-A its rather simple to randomize uniformly the units. Assuming we have a system clock, for each rising edge of the clock signal we randomize the units.

if(DEM_enable) begin generate i(1,`DAC_UNITS) begin temp = $dist_uniform(seed, 1, `DAC_UNITS); if(temp - floor(temp) >= 0.5) DEM[i] = ceil(temp); else DEM[i] = floor(temp); endend // Then select units stored in the array DEM[ ] for conversion

unit

unit

unit

…

unit

Vout

+

2B-1

0

1

2B-2T

herm

omet

er d

ecod

er

B bits …

Ran

do

miz

e …

22NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

Generic ADC Analysis and model Simulation results

Flash ADC Analysis and model Simulation results

SAR ADC Analysis and model Simulation Results

Pipelined ADC Analysis 1.5 bit Stage

- 1.5 bit ADC

23NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Generic ADC model

Analog input

Dig

ital o

utpu

t co

de

INL = 0.5LSB

Gain error = 0.5LSB

IdealNonideal

Offset error = 0.5LSB

Integral non-linearityINL

Quantization stepq

Gain errorεg

Full scale voltageFS

Offset errorεoff

nominal gaing

α(wa + off)

ya

1/(1+qεg)α

(2N-1-1)qA

FS/(2N-1)q

(1- ε0)xa + xa3 ε0/A2

wa

(INL)sqrt(27)/(2N-2)ε0

(l1 εg-εoff)qoffset

-FS/(2g) + q/2l1

IdealADC

+N bits

α

offset

xawavavadc

24NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Generic ADC simulation results

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 106

-120

-100

-80

-60

-40

-20

0

Ma

gn

itu

de

(d

B)

Frequency (Hz)

gain error =0.5LSB, offset error = 0.5LSB and INL = 0.5LSB

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 106

-120

-100

-80

-60

-40

-20

0

Ma

gn

itu

de

(d

B)

Frequency (Hz)

SNDR = 49.82 dB SNR = 49.90 dB THD = -64.668 dBSFDR = 67.461 dB ENOB = 8 bits

PSD plot for 8-bit generic ADC with 0 dB input signal f in of 500.977KHz, Samples = 8192, BW = 2MHz

SNDR = 47.877 dB SNR = 49.455 dB THD = -53.037 dBSFDR = 53.859 dB ENOB = 7.7 bits

25NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

Generic ADC Analysis and model Simulation results

Flash ADC Analysis and model Simulation results

SAR ADC Analysis and model Simulation Results

Pipelined ADC Analysis 1.5 bit Stage

- 1.5 bit ADC

26NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Flash ADC

+

-

+

-

+

-

+

-

… ……

+Vref

-Vref

R

R

R

R

R

R

…

Dec

oder N bits

Are made by cascading high-speed comparators.

Are the fastest way to convert an analog signal to a digital signal.

Ideal for applications requiring very large bandwidth.

Typically consume more power than other ADC architectures and are generally limited to 8-bits resolution.

27NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Flash ADC non-idealities OPAMP

Finite DC gain Finite GBW Input resistance Output resistance Bias current Offset voltage Slew Rate

Bubbles It is due the metastability of the

comparators. (Future work will try model this effect)

Cc

V +V -

Vdd

Ibias

CL

GBW = gm1/CC

I5

I5 = SR*Cc

Cadence provides a well accepted behavioral model of an non-ideal

OPAMP/OTA for the most used AHDLs (Verilog-A, Verilog-AMS and VHDL-AMS)!

28NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 106

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Ma

gn

itu

de

(d

B)

Frequency (Hz)

Flash ADC simulation results

SNDR (dB) 49.264 44.408

SNR (dB) 49.323 44.481

THD (dB) -67.954 -62.193

SFDR (dB) 60.778 47.261

ENOB 7.9 7.1

IdealNonideal

PSD plot for 8-bit Flash ADC with 0 dB input signal f in of 3.01MHz, Samples = 4096, BW = 5MHz

29NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

Generic ADC Analysis and model Simulation results

Flash ADC Analysis and model Simulation results

SAR ADC Analysis and model Simulation Results

Pipelined ADC Analysis 1.5 bit Stage

- 1.5 bit ADC

30NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

SAR ADC

Successive-approximation-register (SAR) ADCs) used for medium-to-high-resolution (8 to 16 bits) applications with sample rates under 5 Msps.

Used in portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition.

Provide low power consumption.

An N-bit SAR ADC will require N comparison periods and will not be ready for the next conversion until the current one is complete.

31NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

SAR ADC

VDAC

time

Vin

bit 3=0 bit 2=1 bit 1=0 bit 0=1

¼ Vref

½ Vref

¾ Vref

Vref

(MSB) (LSB)

Successive Approximation

Register (SAR)

DAC

Timing control

Sample & hold

Register

StartCLKEOC

N bitsN bits

Vin

+

-

Start

CLK

CONV

SAH

EOC

CO

NVSAH

Conversion time

Anti-aliased signal

32NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

0 0.5 1 1.5 2 2.5

x 105

-140

-120

-100

-80

-60

-40

-20

0

20

Frequency (Hz)

Ma

gn

itu

de

(d

B) 8.0ENOB

67.353SFDR (dB)

-65.263THD (dB)

49.949SNR (dB)

49.823SNDR (dB)

Ideal PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz

SAR 8-bit ADC simulation results

33NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

0 0.5 1 1.5 2 2.5

x 105

-140

-120

-100

-80

-60

-40

-20

0

0 0.5 1 1.5 2 2.5

x 105

-140

-120

-100

-80

-60

-40

-20

0

0.1% DAC mismatch DEM on

0.1% DAC mismatch DEM off

Ma

gn

itu

de

(d

B)

Frequency (Hz) Ideal SNDR

6.02N+1.76=49.92 dB

PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz

Increase in harmonics duemismatch in DAC units

SAR 8-bit ADC simulation results

34NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

0 0.5 1 1.5 2 2.5

x 105

-140

-120

-100

-80

-60

-40

-20

00.1% DAC mismatch DEM on0.1% DAC mismatch DEM off

0.0% DAC mismatch DEM off0.1% DAC mismatch DEM off

Mag

nit

ud

e (

dB

)

Frequency (Hz) Ideal SNDR

6.02N+1.76=49.92 dB

7.36.9ENOB

48.7847.74SFDR (dB)

-66.38-45.61THD (dB)

45.9947.43SNR (dB)

45.9543.42SNDR (dB)

PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz

Increase in harmonics duemismatch in DAC units

SAR 8-bit ADC simulation results

35NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

Generic ADC Analysis and model Simulation results

Flash ADC Analysis and model Simulation results

SAR ADC Analysis and model Simulation Results

Pipelined ADC Analysis 1.5 bit Stage

- 1.5 bit ADC

36NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

- 1.5 bit MDAC

Digital Correction Simulation results

ΣΔ ADC ΣΔ Modulator

- SC integrator analysis

- Model

- Simulation results

Conclusions Future Work Acknowledgements References

37NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Pipelined ADC

Has become the most popular ADC architecture for sampling rates from a few MS/s up to 100MS/s, with resolutions from 8 bits at the faster sample rates up to 16 bits at the lower rates.

Low-power capability.

Allows the use of "digital error correction" and “digital calibration” to greatly reduce the accuracy requirement of the internal flash ADCs and DACs respectively.

Because each sample has to propagate through the entire pipeline before all its associated bits are available there is some data latency.

38NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Pipeline ADC

Stage1 Stage2 Stagek-1 Stagek

Registers

Digital correction

N1 bits N2 bits Nk-1 bits Nk bits

N1 bits N2 bits Nk-1 bits Nk bits

M bits

Sample & hold

Nk-1bitDAC

Nk-1bitADC

+ 2N k-1

Residue amplifier

+

-Nk-1 bits

39NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Pipeline ADC 8-bit (1.5-bit per stage )

Stage1 Stage2 Stage6

Registers

Digital correction

2 bit 2 bit 2 bit 2 bits

2 bit 2 bit 2 bit 2 bits

8 bits

Sample & hold

1.5 bitADC

Vin

dout

Φ1

Φ2

Φ2Φ1Φ2Φ1 Φ1

Φ1

Φ2

Anti-aliased signal

40NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

1.5-bit Pipelined Stage

MDAC1.5 bit ADC

1.5 bitDAC

1.5 bitADC

+ 2

Residue amplifier

+

-2 bits

+

-

+

-

1/4Vref

-1/4Vref

Vin

Enc

ode

r

2 bits

C1

C2

Φ2Φ1

Φ1Φ1

Φ2

Vin

1/2Vref4:1MUX

-1/2Vref

0

X

From ADC

Φ1

Φ2

-

+

b0b1

Vr

Residue

Vin Residue

41NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

1.5 bit ADC

1.5-bit ADC

1.5 bitDAC

1.5 bitADC

+ 2

Residue amplifier

+

-2 bits

+

-

+

-

1/4Vref

-1/4Vref

VinE

ncod

er

2 bits

Modeled as a Generic ADC with the specified reference levels

-1/4Vref 1/4Vref

00

01

10

Vin

Dig

ita

l c

od

e

42NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

1.5-bit MDAC

-1/4Vref -1/4Vref

Vin

Residue

-Vref

-1/2Vref

0

1/2Vref

Vref

Vres = Vin(C1+C2)/C1 + Vr

C1

C2

Φ2Φ1

Φ1Φ1

Φ2

Vin

1/2Vref4:1MUX

-1/2Vref

0

X

From ADC

Φ1

Φ2

-

+

b0b1

Vr

Residue

1.5 bitDAC

1.5 bitADC

+ 2

Residue amplifier

+

-2 bits

MDAC ResidueVin

43NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

1.5-bit MDAC nonidealities

CCC 12

• Finite DC gain A0

• Finite GBW, Cp and CL

• Defective settling • Linear• Slewing • Partial Slewing

C1

C2

Φ2Φ1

Φ1Φ1

Φ2

Vin

1/2Vref4:1

MUX-1/2Vref

0

X

From ADC

Φ1

Φ2

-

+

Cp

CL

εg= C1+(C1+ C2+ Cp)/A0

pp

pp

p

p

CCC

CGBWω

ωsQ

ωs

ωH(s)

21

1

22

2

2

|H|

Thermal noise Vth ≈ kT/C1

(Opamp noise neglected)

Capacitors mismatch

Vre

s

Time

Ideal value

44NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

1.5-bit Stage model

Defectivesettling

Vres

IdealNonideal

1.5bit MDACIncluding mismatch

+

ThermalNoise

Vin

VADC 1.5 bit GenericADC

2-bits

45NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Digital Correction

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Register

Φ2

Φ1

++++++ +ba

cincout

sum

ba

cincout

ba

cincout

ba

cincout

ba

cincout

ba

cincout

ba

cincout

sum sum sum sum sumsumOverflow

s7[1] s7[0]

s6[1] s6[0]

s5[1] s5[0]

s4[1] s4[0]

s3[1] s3[0]

s2[1] s2[0]s1[1] s1[0]

b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0]

sk[1] sk[0] are the bits from stage k

46NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Pipelined 8-bit ADC model (Cadence)

47NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Pipelined 8-bit ADC simulation results

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 106

-140

-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

Ma

gn

itu

de

(d

B)

Non-idealIdeal

7.87.2ENOB

61.77854.427SFDR (dB)

-57.082-49.923THD (dB)

49.23849.573SNR (dB)

48.57744.922SNDR (dB)

PSD plot for 8-bit Pipelined ADC with 0 dB input signal Input frequency of 1.01MHz, Samples = 8192, Bandwidth = 5MHz

48NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Agenda

- 1.5 bit MDAC

Digital Correction Simulation results

ΣΔ ADC ΣΔ Modulator

- SC integrator analysis

- Model

- Simulation results

Conclusions Future Work Acknowledgements References

49NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

ΣΔ ADC

Makes use of oversampling and ΣΔ modulation techniques to achieve high resolution.

Used for low bandwidth and high-resolution applications but recently there is great interest for medium to high bandwidth applications.

Due oversampling the requirements of the anti-aliasing filter are reduced.

ModulatorDigital Filter

yo[n]

Analog Digital

Anti-alias filter

fs

y[n]x[n]xi(t) xb(t)

50NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

ΣΔM is the major analog component of the ADC.

Due to its mixed-signal nature, non-idealities largely affect the performance of the ADC, i.e. the integrator, DAC mismatch.

Quatization noise is shaped outside the band of interest.

Several architectures exists depending on the number of integrators and the quantizer levels.

ΣΔ Modulator (ΣΔM)

N-levelQuantize

r∫

g1

g2

DAC

Lth order contains L integrators Single or Multi-bitdepending on the

quantizer

Frequency (Hz)M

agn

itu

de

(dB

) Signal

Digital Filter

ShapedQuantization

Noise

WhiteNoise

51NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

SC integrator transient model

OTA

Ci

Cr

Cint

Cp

CL

Cinxt

Vi

Vr

Va Vo

+

-

Φ1 Φ2

Φ1 Φ2

Φ2 Φ1

Φ2 Φ1

Φ1

Φ2

Φ1

Φ2

Single pole OTA model Defective settling due to the OTA finite DC

gain, GBW and SR limitations. Possible settling scenarios:

Linear• |Vai| ≤ Io/gm

Slewing• |Vai| > Io/gm and t < to

Partial Slewing• |Vai| > Io/gm and t ≥ to

Sampling Φ1Integration Φ2

Va

Time

Ideal value

settling error

-gmVa go Co

Va

Vo

+Io

-Io

Parameter Description

Ci, Cr Sampling capacitors

Cint Integrating capacitor

Cp,Co Input and output parasitic capacitances

Cinxt Next stage input capacitance

gm OTA transconductance

go OTA output conductance

Io OTA max output current

to slewing time

Vai Initial voltage at Va

52NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Va

Second-Order ΣΔΜ Model

∫g11

g12∫

g21

g22

5-level 3-bitsFlash ADC

Decoder

DAC

3-bits

4-bits4-bits

+

ThermalNoise

+

ThermalNoise

JitterSC intg

OTA + switches for both phases Φ1 and Φ2

0.1% mismatch

SC intg

gX1 = Ci/Cint gX2 = Cr/Cint

OTA

Ci

Cr

Cint

Cp

CL

Cinxt

Vi

Vr

Vo

+

-

Φ1 Φ2

Φ1 Φ2

Φ2 Φ1

Φ2 Φ1

Φ1

Φ2

Φ1

Φ2

Vin

DAC

ILA4-bits

53NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

ΣΔΜ Simulation Results GSM mode

VHDL-AMS 74.0164 dBActual data 74.5000 dB

*Second order sigma-delta modulator with -6 dB input signal Input frequency of 30kHz, OSR = 65, N = 65536, BW = 200kHz (GSM mode)

*This work has been accepted as a lecture presentation at the IEEE MWCAS 2005 conference, August 7-10 Cincinnati, Ohio.

0.65% error

54NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

ΣΔΜ Simulation Results WCDMA mode

VHDL-AMS 45.21 dBActual data 49.00 dB

Second order sigma-delta modulator with -6 dB input signal Input frequency of 300kHz, OSR = 12, N = 65536, BW = 200kHz (GSM mode)

7.7% error

55NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Conclusions

Behavioral modeling is a viable solution for the complex modeling and simulation of mixed-signal circuits.

Verilog-A AHDL is suitable for modeling and simulation of mixed-signal circuits providing modularity and flexibility.

Accurate behavioral models are achieved via validation.

Behavioral modeling can be used as part of a Top-Down design approach but an iterative procedure is needed in order to refine the models.

Effective circuits modeling techniques involves deep analysis including

noise sources.

56NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Future Work

Include more ADCs architectures such as integrating, sub-range and inter-leaved.

Add specific DAC architectures such as resistor-string, capacitive, ΣΔ, multiplying, algorithmic and current-steering.

Explore current based techniques.

Model some other effects in common blocks such as the comparator metastability.

Validate some of the models with available or future designs.

57NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Acknowledgments

Dr. Umesh Patel Dr. Manuel Jimenez at UPR Mayaguez Bob Kasa Wesley Powell Ellen Kozireski George Schoppet Alex Dea Damon Bradley Aaron Dixon George Winkert Betsy Pugel

58NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

References

M. Gustavsson, J. J. Wikner and N. N. Tan. “CMOS DATA CONVERTERS FOR COMMUNICATIONS”, Kluwer Academic Publishers, 2002.

A. Rodriguez-Vazquez, F. Medeiro and E. Janssens. “CMOS Telecom Data Converters”. Kluwer Academic Publishers, 2003.

F. Medeiro, A. Perez-Verdu and A. Rodriguez-Vazquez. “TOP-DOWN ESIGN OF HIGH-PERFORMANCE SIGMA-DELTA MODULATORS”, Kluwer Academic Publishers, 1999.

D. Fitzpatrick and I. Miller. “ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE”, Kluwer Academic Publishers, 1998.

B. Razavi. “Principles of Data Conversion System Design”. IEEE Press, 1995. T. M. Hancock. S. M. Pernia and A. C. Zeeb. “A Digitally Corrected 1.5-Bit/Stage

Low Power 80Ms/s 10-Bit Pipelined ADC”. University of Michigan EECS 598-02, December 2002.

M. Anderson, K. Norling and J. Yuan. “On the Effects of Static Errors in a Pipelined A/D Converter”. SSoCC 2003.

R. Sommer, I. Rugen-Herzig, E. Hennig, U. Gatti, P. Malcovati, F. Maloberti, K. Einwich, C. Clauss, P Schwarz and G. Noessing. “From System Specifications To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications. Proc. of the 2002 Design, Automation and Test in Europe, 2002.

N. Mohan. “Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A“, www.techonline.com .

59NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

References J. W. Bruce II. “DYNAMIC ELEMENT MATCHING TECHNIQUES FOR DATA

CONVERTERS” PhD Dissertation, University of Nevada Las Vegas , May 2000. K. Kundert. “Top-Down Design of Mixed-Signal Circuits”. Cadence Design Systems,

San Jose, California, 2000. K. W. Current, J. F. Parker, and W. J. Hardaker, “On Behavioral Modeling of Analog

and Mixed-Signal Circuits”. IEEE Conference Record of the Twenty-Eighth Asilomar on Signals, Systems and Computers, vol. 1,  pp264 – 268, 1994

F. O. Fernandez “Behavioral Modeling of ΣΔ Modulators”. Master’s Thesis University of Puerto Rico. Mayaguez, Puerto Rico 2003.

T. Kugelstadt. “The operation of the SAR-ADC based on charge redistribution” TI Analog Applications Journal, Texas Instruments, 2000.

J. Compiet, R de Jong, P, Wambacq, G, Vandersteen, S. Donnay, M. Engels and I. Bolsens. “HIGH-LEVEL MODELING OF A HIGH-SPEED FLASH A/D CONVERTER FOR MIXED-SIGNAL SIMULATIONS OF DIGITAL TELECOMMUNICATION FRONT-ENDS”. IEEE SSMSD, pp. 135 – 140, 2000.

B. Brannon. “Aperture Uncertainty and ADC System Performance”. Analog Devices APPLICATION NOTE AN-501.

“Understanding SAR ADCs”. Maxim-IC Application Note 387: Mar 01, 2001. “Understanding Pipelined ADCs”. Maxim-IC Application Note 383: Mar 01, 2001. “Understanding Flash ADCs”. Maxim-IC Application Note 810: Oct 02, 2001

60NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

printf (“Questions?“);

#include <stdio.h> int main () {

}

char str [100];

scanf ("%s",str);return 0;

61NASA Goddard Space Flight Center

Code 564 Microelectronic and Signal ProcessingBehavioral Modeling of ADCs using Verilog-A

by George Suárez

Acronyms

ADC – Analog-to-digital converterAHDL – Analog Hardware Description Language DAC – Digital-to-analog converterDEM – Dynamic Element MatchingENOB – Effective number of bits.FS – Full scale voltageGBW – Gain bandwidthILA – Individual Level AveragingINL – Integral non-linearityMDAC – Multiplying DACSAR – Successive Approximation RegisterSFDR - Spurious Free Dynamic RangeSNDR – Signal-to-noise plus distortion ratioSNR – Signal-to-noise ratioTHD – Total Harmonic DistortionΣΔΜ – Sigma-Delta Modulator