Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A Seyed...
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Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi Behavioral Modeling and Simulation (BMAS) Conf. September 2010 Sharif University of Technology Department of Computer Engineering Dependable System Lab [DSL] 1
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Transcript of Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A Seyed...
Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A
SeyedNematollahAhmadian,SeyedGhassemMiremadi
BehavioralModelingandSimulation(BMAS)Conf.September2010
SharifUniversityofTechnologyDepartmentofComputerEngineering
DependableSystemLab[DSL]
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Outline
Dependability MixedSignalFlow BehavioralFaultModeling FaultModels
SingleEventTransient/Upset(SET/SEU) PowerLineDisturbance(PLD) ElectroMagneticInterference(EMI)
Results
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DependabilityandReliability
DependabilityandReliability Notjustwords!
Aneffectivetechniquefortheexperimentaldependabilityevaluation
Weproposeasimulation-basedfaultinjectionmethodinmixed-signalenvironment.
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PreviousFaultInjectionTools
Levelofabstraction
HDLCircuit
HDL CircuitDoes not include enough details For accurate modeling
Too slow, too old. cannot include verification method like
testbenches, etc.
solution:Mixed-signal fault injection
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Flow
FaultinjectionandsimulationisperformedinMixed-Signalenvironment Performance/Accuracytradeoff
MoreaccuratethanRTLsimulationFasterthanSPICEsimulation
FaultinjectiononSoCswithanalogcoresPLLs,DLLs,SRAMs,…
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Flow
SPICEsimulationnearthefaultsite: accuratefaultsimulation
HDLSimulation(elsewhere) Motive:Mostofthefaultmanifestthemselvesasanderror
outsidethefaultsite HDLsimulationprovidesenoughaccuracytocontinuesimulation.
Originaltestbenches/verificationscriptsareintact Fastersimulation.CancompensatefortheSPICEsimulation
penalty.
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FaultModeling
Wedevelopfaultmodelsinbehavioralmodelinglanguages(suchasVerilog-A) Easymodeling Reducedevelopmenttime Accuratesimulations Accesstointernalnodes/structureoftransistor/electricalelement
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Tool-chainarchitecture
Mixed-signalthree-levelofabstraction
FaultsareembeddedinsideVerilog-Amodel. ResultedfaultmodelsareinsertedtoCircuitasanexternalcomponent
Design Under TestUnit Under Test
Converted to SPICE
Replaced device modelWith
Fault Injection
Unit under test
FaultyCell/
device
HDL level Circuit Level Gate Level
Verilog/VHDLModelSim 6.5 SE
SPICE netlistSynopsys hsim
Verilog-A modelSynopsys hsim
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Faultmodels
Behavioralfaultmodeling SingleEventTransients/Upset(SET/SEU) Electro-MagneticInterference(EMI) PowerLineDisturbance(PLD)
Ourflowsupportsotherfaultmodelsaswell.
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SETFaultModeling
Cause:hittingahigh-powerparticleintotransistorsdiffusionarea.
Effect:transientcurrentspikeondiffusion,singleeventtransientandupset.
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Electro-MagneticInterferenceModeling
EMorRFinducedinterference
ModeledasaContinues-waveRFIsuperimposedonspecificnodes. Input Clock …
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PowerLineDisturbanceModeling
CommonPLDs: Powersupplynoise Overshoot,Undershoot
GroundBouncing
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Flow:Initialization/Injection
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Flow:Simulation/Evaluation
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ExperimentalSetup
Weusedthefollowing3rdpartytoolsandIPs: HDLSimulator:ModelSim6.5SE SpiceSimulator:SynopsysHSIM2008.09 Process:TSMC0.25μm
Ourfaultcharacteristics: SET:Q=10pc,withTO=TB=10ns,Randominjection,Twoexponentialmodel
EMI:100MHzCWRFsignal,Vpeak=0.5V,100nspulseenvelope,Randominjection
PLD:100nsduration,Voltageshortage(from2.5Vto0V)onVDDline,Randominjection
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ResultsofSystemFailures
Counter FSM ALU SRAM UART AVERAGE0
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PLDEMISET
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Thankyou!
Questions?
Thankyouforyourattention.
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