Bdc

MOTOROLA CMOS LOGIC DATA1

MC14534B

The MC14534B is composed of five BCD ripple counters that have theirrespective outputs multiplexed using an internal scanner. Outputs of eachcounter are selected by the scanner and appear on four (BCD) pins.Selection is indicated by a logic high on the appropriate digit select pin. BothBCD and digit select outputs have threestate controls providing anopencircuit when these controls are high and allowing multiplexing.Cascading may be accomplished by using the carryout pin. The countersand scanner can be independently reset by applying a high to the countermaster reset (MR) and the scanner reset (SR). The MC14534B wasspecifically designed for application in real time or event counters wherecontinual updating and multiplexed displays are used. Four Operating Modes (See truth table) Input Error Detection Circuit Clock Conditioning Circuits for Slow Transition Inputs Counter Sequences on Positive Transition of Clock A Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or One Lowpower

Schottky TTL Load Over the Rated Temperature Range

BLOCK DIAGRAM

PULSE ERRORDETECTORPULSE

SHAPERTEST

CONTROL

OUTPUTCONTROL

MUX

MUX MUX MUX MUX

UNITSCARRY

CONTROL

TENS HUNDREDS THOUSANDS TENTHOUSANDS

C 10 C 10 C 10 C 10 C 10

Q0 Q3 Q0 Q3 Q0 Q3 Q0 Q3 Q0 Q3

Cn+4 Cn+4 Cn+4 Cn+4 Cn+4

22

7 8 14 16 11

1

23

4

2

5

6

9

10

CLOCK B

CLOCK A

MASTERRESET

MODE AMODE B

SCANNERRESET

SCANNERCLOCK

ERROR OUT3

R

SCANNER

13

17

18

19

20

Q3

Q2

Q1

Q0

213STATE BCDCONTROL

CARRY OUT

3STATE DIGITCONTROL

15

DS1 DS2 DS3 DS4 DS5

DIGIT SELECT3STATEOUTPUT BUFFER

NOTE:

BCDOUT

VDD = PIN 24VSS = PIN 12

TO CAPACITORS

3State Control Out

Q or DSHigh Impedance

01

=

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1995

REV 31/94

L SUFFIXCERAMICCASE 623

ORDERING INFORMATIONMC14XXXBCP PlasticMC14XXXBCL CeramicMC14XXXBDW SOIC

TA = 55 to 125C for all packages.

P SUFFIXPLASTICCASE 709

DW SUFFIXSOIC

CASE 751E

MOTOROLA CMOS LOGIC DATAMC14534B2

MAXIMUM RATINGS (Voltages referenced to VSS)Symbol Parameter Value Unit

VDD DC Supply Voltage 0.5 to + 18.0 V

Vin, Vout Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 VIin, Iout Input or Output Current (DC or Transient),

per Pin 10 mA

PD Power Dissipation, per Package 500 mWTstg Storage Temperature 65 to + 150 C

TL Lead Temperature (8Second Soldering) 260 C* Maximum Ratings are those values beyond which damage to the device may occur.Temperature Derating:

Plastic P and D/DW Packages: 7.0 mW/C From 65C To 125CCeramic L Packages: 12 mW/C From 100C To 125C

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic SymbolVDDVdc

55C 25C 125CUnitCharacteristic Symbol

VDDVdc Min Max Min Typ # Max Min Max Unit

Output Voltage 0 LevelVin = VDD or 0

VOL 5.01015

0.050.050.05

000

0.050.050.05

0.050.050.05

Vdc

1 LevelVin = 0 or VDD

VOH 5.01015

4.959.9514.95

4.959.9514.95

5.01015

4.959.9514.95

Vdc

Input Voltage 0 Level(VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

VIL5.01015

1.02.03.0

1.53.04.5

1.02.03.0

1.02.03.0

Vdc

1 Level(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

VIH5.01015

4.08.012

4.08.012

3.57.011

4.08.012

Vdc

Output Drive Current(VOH = 2.5 Vdc) Source(VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)

IOH5.05.01015

3.0 0.64 1.6 4.2

2.4 0.51 1.3 3.4

4.2 0.88 2.25 8.8

1.7 0.36 0.9 2.4

mAdc

(VOL = 0.4 Vdc) Sink(VOL = 0.5 Vdc)(VOL = 1.5 Vdc)

IOL 5.01015

0.641.64.2

0.511.33.4

0.882.258.8

0.360.92.4

mAdc

Output Drive Current Pins 1 and 22(VOH = 2.5 Vdc)(VOH = 9.5 Vdc) Source(VOH = 13.5 Vdc)

IOH5.01015

0.31 0.31 0.9

0.25 0.25 0.75

0.8 0.4 1.6

0.17 0.17 0.51

mAdc

(VOL = 0.4 Vdc) Sink(VOL = 0.5 Vdc)(VOL = 1.5 Vdc)

IOL 5.01015

0.0240.061.3

0.020.050.25

0.030.091.63

0.0140.0350.175

mAdc

Input Current Iin 15 0.1 0.00001 0.1 1.0 Adc

Input Capacitance(Vin = 0)

Cin 5.0 7.5 pF

#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance. (continued)

This device contains protection circuitry toguard against damage due to high staticvoltages or electric fields. However, pre-cautions must be taken to avoid applications ofany voltage higher than maximum rated volt-ages to this highimpedance circuit. For properoperation, Vin and Vout should be constrainedto the range VSS (Vin or Vout) VDD.

Unused inputs must always be tied to anappropriate logic voltage level (e.g., either VSSor VDD). Unused outputs must be left open.


MC14534B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) (continued)

Characteristic SymbolVDDVdc

55C 25C 125CUnitCharacteristic Symbol

VDDVdc Min Max Min Typ # Max Min Max Unit

Quiescent Current(Per Package)

IDD 5.01015

5.01020

0.0100.0200.030

5.01020

150300600

Adc

Total Supply Current**(Dynamic plus Quiescent,Per Package) (CL = 50 pF on all outputs, all buffers switching)

IT 5.01015

IT = (0.5 A/kHz) f + IDD Scan Oscillator IT = (1.0 A/kHz) f + IDD Frequency = 1.0 kHzIT = (1.5 A/kHz) f + IDD

Adc

ThreeState Leakage Current ITL 15 0.1 0.0001 0.1 3.0 Adc#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.**The formulas given are for the typical characteristics only at 25C.To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL 50) Vfkwhere: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001.


SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25C, see Figure 1)

Characteristic SymbolVDDVdc Min Typ # Max Unit

Output Rise and Fall Time tTLH,tTHL

5.01015

1005040

20010080

ns

Propagation Delay Time,Clock to Q

tPLH, tPHL = (1.8 ns/pF) CL + 4.0 stPLH, tPHL = (0.8 ns/pF) CL + 1.5 stPLH, tPHL = (0.6 ns/pF) CL + 1.0 s

tPLH,tPHL

5.01015

4.01.51.0

8.03.02.25

s

Clock to Carry OuttPLH = (1.8 ns/pF) CL + 3.3 stPLH = (0.8 ns/pF) CL + 1.1 stPLH = (0.6 ns/pF) CL + 0.8 s

tPLH5.01015

3.31.10.8

6.62.21.7

s

Master Reset to QtPHL = (1.8 ns/pF) CL + 1.8 stPHL = (0.8 ns/pF) CL + 0.6 stPHL = (0.6 ns/pF) CL + 0.5 s

tPHL5.01015

1.80.60.5

3.61.20.9

s

Master Reset to Error OuttPHL = (1.8 ns/pF) CL + 0.57 stPHL = (0.8 ns/pF) CL + 0.19 stPHL = (0.6 ns/pF) CL + 0.11 s

tPHL5.01015

0.60.20.12

1.5.5

0.38

s

Scanner Clock to QtPLH, tPHL = (1.8 ns/pF) CL + 1.8 stPLH, tPHL = (0.8 ns/pF) CL + 0.6 stPLH, tPHL = (0.6 ns/pF) CL + 0.5 s

tPLH,tPHL 5.0

1015

1.80.60.5

3.61.20.9

s

Scanner Clock to Digit SelecttPHL, tPLH = (1.8 ns/pF) CL + 1.5 stPHL, tPLH = (0.8 ns/pF) CL + 0.5 stPHL, tPLH = (0.6 ns/pF) CL + 0.4 s

tPLH,tPLH 5.0

1015

1.50.50.4

3.01.00.75

s

Propagation Delay Time3State Control to Q

tPHZ 5.01015

754540

1509080

ns

tPZH 5.01015

1205540

24011080

ns

tPLZ 5.01015

1205545

24011090

ns

tPZL 5.01015

1607045

32014090

ns

Clock Pulse Frequency fcl 5.01015

1.03.05.0

0.51.01.2

MHz

Clock or Scanner Clock Pulse Width tWH 5.01015

1000500375

500190125

ns

Scanner Reset Pulse Width tw 5.01015

32013080

1606540

ns

Scanner Reset Removal Time trem 5.01015

900150100

2708050

ns

Master Reset Pulse Width tWH(R) 5.01015

2000600450

900300250

ns

Master Reset Removal Time trem 5.01015

1060350250

550205140

ns

* The formulas given are for the typical characteristics only at 25C.#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.


MC14534B

COUNTER TIMING DIAGRAM

10610510410310210987654321CLOCK A

UNITS Q0

UNITS Q1

UNITS Q2

UNITS Q3

UNITS Cn + 4

TENS Q0

TENS Q3

TENS Cn + 4

HUNDREDS Q0

HUNDREDS Q3

HUNDREDS Cn + 4

THOUSANDS Q0

THOUSANDS Q3

THOUSANDS Cn + 4

TEN THOUSANDS Q0

TEN THOUSANDS Q3

CARRY OUT

MASTER RESET

MODE CONTROL TRUTH TABLEMode A Mode B First Stage Output Carry to Second Stage Application

0 0 Normal Count and Display At 9 to 0 transition of first stage 5digit Counter

0 1 Inhibited Input Clock Test Mode: Clock directly into stages 1, 2, and 4.

1 1 Inhibited At 4 to 5 transition of first stage 4digit counter with 10 and roundoff at front end.

1 0 Counts 3, 4, 5, 6, 7 = 5Counts 8, 9, 0, 1, 2 = 0

At 7 to 8 transition of first stage 4digit counter with 1/2 pence capability.


SCANNER TIMING DIAGRAM

NOTE: If Mode B = 1, the first decade is inhibited and S1 will not go high, and the cycle will beshortened to four stages.DS5 is selected automatically when Scanner Reset goes high.

TENTHOUSANDS

THOUSANDS

HUNDREDS

TENS

UNITS

SCANNERCLOCK

SCANNERRESET

DS1

DS2

DS3

DS4

DS5

ERROR DETECTION TIMING DIAGRAM

NOTE: Error detector looks for inverted pulse on Clock B. Whenever a positive edge atClock A is not accompanied by a negative pulse at Clock B (or viceversa) withina time period of the oneshots an error is counted. Three errors result in Error Outto go to a 1. If error detection is not needed, tie Clock B high or low and leavePins 1 and 22 unconnected.

CLOCK ACLOCK B

RESET

ERROROUT

GOOD PULSEERROR

1ERROR

2 ERROR3

ERROR4

GOOD PULSE

CLOCK SKEW RANGE

NOTES:1. The skew is the time difference between the

lowtohigh transition of CA to the hightolow transition of CB or viceversa. CapacitorsC1 = C22 tied from pins 1 and 22 to VSS.

2. This graph is accurate for C1 = C22 100 pF.3. When the error detection circuitry in not used,

pins 1 and 22 are left open.

1000500300

100

5030

105.03.0

1.03.0 5.0 7.0 9.0 11 13 15 17

VDD (Vdc)

SKEW IN THIS RANGERESULTS IN COUNTEDERROR.

MAX

SKEW IN THIS RANGERESULTS IN NO ERRORCOUNTED.

TYP

MIN

SKEW IN THIS RANGEMAY OR MAY NOTRESULT IN COUNTEDERROR.

ALLO

WABL

E CL

OCK

SKEW

(ns/p

F)


MC14534B

APPLICATIONS INFORMATION

Figure 1. Cascade Operation

* Carry Out is high for a single clock period when all five BCD stages go to zero.(Carry Out also goes high when MR is applied.)

VDD

CLOCKCLOCK A CLOCK A

En

CQ4 Cout*

1/2MC14518B

MC14534B MC14534B

Figure 2. Forcing a BCD Stage to the Q Outputs

When the Q outputs of a given stage are required, this configuration willlock up the selected stage within four clock cycles. The select line feedbackmay be hardwired or switched.

CLOCK BCD FORSELECTEDSTAGE

Q0CLOCK AQ1Q2Q3

SC

DS5DS4DS3DS2DS1

MC14534B

MODE B

CLOCK AEout

MR

Cext

DS2DS1

MODE A Q03ST BCDCext

CLOCK BVDD

3ST DIGDS4Q3

5

4

3

2

1

10

9

87

6

14

15

16

17

18

19

20

13

11

12

21

22

23

24

Cout

DS3

Q2Q1

DS5VSS

SCSR

PIN ASSIGNMENT


OUTLINE DIMENSIONS

P SUFFIXPLASTIC DIP PACKAGE

CASE 70902ISSUE C

L SUFFIXCERAMIC DIP PACKAGE

CASE 62305ISSUE M

NOTES:1. POSITIONAL TOLERANCE OF LEADS (D),

SHALL BE WITHIN 0.25 (0.010) AT MAXIMUMMATERIAL CONDITION, IN RELATION TOSEATING PLANE AND EACH OTHER.

2. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLDFLASH.

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 31.37 32.13 1.235 1.265B 13.72 14.22 0.540 0.560C 3.94 5.08 0.155 0.200D 0.36 0.56 0.014 0.022F 1.02 1.52 0.040 0.060G 2.54 BSC 0.100 BSCH 1.65 2.03 0.065 0.080J 0.20 0.38 0.008 0.015K 2.92 3.43 0.115 0.135L 15.24 BSC 0.600 BSCM 0 15 0 15 N 0.51 1.02 0.020 0.040

1 12

1324

B

H

A

FDG

K

SEATINGPLANE

NC

M J

L

NOTES:1. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUMMATERIAL CONDITION (WHEN FORMEDPARALLEL).

1 12

24 13

B

A

SEATINGPLANEF

DG K

N

C

M JL

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 31.24 32.77 1.230 1.290B 12.70 15.49 0.500 0.610C 4.06 5.59 0.160 0.220D 0.41 0.51 0.016 0.020F 1.27 1.52 0.050 0.060G 2.54 BSC 0.100 BSCJ 0.20 0.30 0.008 0.012K 3.18 4.06 0.125 0.160L 15.24 BSC 0.600 BSCM 0 15 0 15 N 0.51 1.27 0.020 0.050


MC14534B

OUTLINE DIMENSIONS

DW SUFFIXPLASTIC SOIC PACKAGE

CASE 751E04ISSUE E

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.13 (0.005) TOTAL INEXCESS OF D DIMENSION AT MAXIMUMMATERIAL CONDITION.

A

B P12X

D24X

12

1324

1

M0.010 (0.25) B M

SAM0.010 (0.25) B ST

T

G22XSEATINGPLANE K

C

R X 45

M

F

JDIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 15.25 15.54 0.601 0.612B 7.40 7.60 0.292 0.299C 2.35 2.65 0.093 0.104D 0.35 0.49 0.014 0.019F 0.41 0.90 0.016 0.035G 1.27 BSC 0.050 BSCJ 0.23 0.32 0.009 0.013K 0.13 0.29 0.005 0.011M 0 8 0 8 P 10.05 10.55 0.395 0.415R 0.25 0.75 0.010 0.029

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MFAX: [email protected] TOUCHTONE 6022446609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://DesignNET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be providedin Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patentrights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implantinto the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create asituation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended orunauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registeredtrademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MC14534B/D

Bdc

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