Bary pangrle mentor track d

Israel, May 4, 2010 © 2010 Mentor Graphics Corp.

www.mentor.com

Low Power

Keeps Getting Hotter

Barry Pangrle, Ph.D.

Solutions Architect

Mentor Graphics Corporation

Israel, May 4, 2010 2© 2010 Mentor Graphics Corp.

www.mentor.com

• Purpose: – Update Information on Power-Efficient Design

• Process: – Background

– Trends Data

– Q & A

• Outcome:– Better Understanding of:

• Where the Industry is Going

• How it Affects You

• How to Best Leverage the Design Process for Your Needs

The Next 25 Minutes…


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Created and runs the Energy Star Program in the U.S. among other

programs for controlling environmental impact

Designers Facing More

Green Requirements

Companies displaying The Green Fan logo demonstrate that they are actively making a positive contribution to reducing CO2

emissions

Aims to reduce energy consumption in worldwide ICT networks by a factor of

1000

A global consortium dedicated to developing and promoting energy

efficiency for data centers and business computing ecosystems


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PCBPower Integrity

PCBPCBPower IntegrityPower Integrity

VerificationPower-Aware

VerificationVerificationPowerPower--AwareAware

TestPower-Aware

TestTestPowerPower--AwareAware

System LevelDesign

System LevelSystem Level

DesignDesign

ChipDesignChipChip

DesignDesign

PackageDesignPackagePackage

DesignDesign

PCBDesignPCBPCB

DesignDesign

“Platform power is as important as core silicon power.”— Joe Macri, CTO, AMD

TLMPower-Aware Models

TLMTLMPowerPower--Aware ModelsAware Models

HLSArchitectural Analysis

HLSHLSArchitectural AnalysisArchitectural Analysis

Place & RouteMulti-Corner Multi-Mode

Place & RoutePlace & RouteMultiMulti--Corner MultiCorner Multi--ModeMode

Power Impacts the Whole System


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Low-Power Requirement vs. Power Trend

SOC Consumer Portable Power Trend

0.00.0

0.50.5

1.01.0

1.51.5

2.02.0

2.52.5

3.03.0

3.53.5

20072007 20082008 20092009 20102010 20112011 20122012 20132013 20142014 20152015 20162016 20172017 20182018 20192019 20202020

StaticStatic DynamicDynamic

Source: The International Technology Roadmap for Semiconductors (ITRS), 2008 Update

(W)(W)

TrendRequirement


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Low-Power Requirement vs. Power Trend

SOC Consumer Portable Power Trend

0.00.0

2.02.0

4.04.0

6.06.0

8.08.0

10.010.0

12.012.0

14.014.0

Source: The International Technology Roadmap for Semiconductors (ITRS), 2009

(W)(W)

20242024202320232022202220212021202020202019201920182018201720172016201620152015201420142013201320122012201120112010201020092009

StaticStatic DynamicDynamic

Requirement


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clock gatingclock gating

’’9595 ’’9696 ’’9797 ’’9898 ’’9999 ’’0000 ’’0101 ’’0202 ’’0303 ’’0404 ’’0505 ’’0606 ’’0707 ’’08080%0%

10%10%

20%20%

30%30%

% of Total Silicon Demand Share

% of Total Silicon Demand Share

250nm250nm 130nm130nm 90nm90nm 65nm65nm 45nm45nm

multi-Vtmulti-Vtpower gatingpower gating DVFSDVFS

Source: VLSI Research, Silicon Demand, July 2008Source: VLSI Research, Silicon Demand, July 2008

Power Driven by Advanced Technology Adoption


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0%0%

20%20%

40%40%

60%60%

1Q1Q’’0505

1Q1Q’’0606

1Q1Q’’0707

1Q1Q’’0808

1Q1Q’’0909

4Q4Q’’0909

3Q3Q’’0404

<=130nm<=130nm 90nm90nm 65nm65nm 45 / 40nm45 / 40nm

% of TSMC Total Wafer Revenues

% of TSMC Total Wafer Revenues

Source: TSMC Quarterly ReportsSource: TSMC Quarterly Reports

70% of Wafer Revenues70% of Wafer Revenues



9+% of Wafer Revenues9+% of Wafer Revenues

Power Driven by Advanced Technology Adoption


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http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=220900080

http://pc.watch.impress.co.jp/docs/2004/0524/epf01.jpg

Power is *NOT* Scaling with Technology

“In a decade, 11nm process technology could deliver devices with 16x more transistors running 2.4x faster than today's parts. But those devices will only use a 1/3 as much energy as today's parts, leaving engineers with a power budget so pinched they may be able to activate only 9% of those transistors.”

–Mike Muller, CTO

ARM


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““Managing leakage power at 90 nm and belowManaging leakage power at 90 nm and below””

Barry Pangrle and Barry Pangrle and ShekharShekhar KapoorKapoor , , EEdesign.comEEdesign.com, Nov 05, 2004, Nov 05, 2004

10000

1000

100

10

1

nW

0 16 32 48 64 80 96 112

128

144

160

176

192

208

224

240

256

272

288

304

320

336

352

368

384

400

416

432

448

464

480

496

512

528

Low Vt

High Vt

90 nm Process

Sorted Cell #

Lower Threshold: Higher Leakage


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Ioff(nA/mm)

1000

100

10

1

0.1

0.01

0.0015

Gate Delay (pS)10 15 20 25 30

Ioffn

Ioffp

“Managing leakage power at 90 nm and below” , Pangrle and Kapoor , EEdesign.com, Nov 05, 2004

90 nm Transistors

Leakage vs. Delay Tradeoff


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“DC power has exceeded AC power for the first time.”

– John Y. Chen VP of Technology and Foundry OpsNVIDIA

http://www.semiconductor.net/article/438968-

Nvidia_s_Chen_Calls_for_Zero_Via_Defects.phphttp://www.scu.edu/engineering/ee/images/John_Chen_1.jpg

Leakage Exceeds Dynamic Power


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0.150.15

0.10.1

0.050.05

00

--0.050.05

--0.10.1--0.50.5 00 0.50.5

VVBSBS (V)(V)

∆∆ ∆∆∆∆ ∆∆VVTHTH(V)

(V)

“Low Power Design Essentials”, Jan Rabaey, 2009

210 mV210 mV130nm130nm

95 mV95 mV90nm90nm

55 mV55 mV65nm65nm

ReverseReverse ForwardForward

GG

BB

DDSS

Body Bias has Diminishing Impact


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Watt

s/c

mW

att

s/c

m22

10001000

100100

1010

1111µµµµµµµµ 0.50.5µµµµµµµµ 0.250.25µµµµµµµµ 0.130.13µµµµµµµµ 65nm65nm

i486i486Pentium®Pentium®

Pentium® ProPentium® Pro

Pentium® IIPentium® IIPentium® IIIPentium® III

P4P4C2DC2D

P4DP4DCi7Ci7

Power DensityPower DensityPower Density

“The numbers I would cite would be by 2010: 30GHz, 10billion

transistors, and 1 tera-instruction per second.”

--Pat Gelsinger, CTO, Intel April 9, 2002

“The numbers I would cite would be by 2010: 30GHz, 10billion

transistors, and 1 tera-instruction per second.”

--Pat Gelsinger, CTO, Intel April 9, 2002

i386i386

100100

1010

10001000

1000010000

100000100000

’’8787 ’’9292 ’’9797 ’’0202 ’’0707

Pentium®Pentium®Pentium® ProPentium® Pro

P4P4

C2DC2DCi7Ci7

i486i486

Pentium® IIIPentium® III

P4DP4D

MHz

MHz

Clock FrequencyClock Frequency

i386i386

’’1010

~30GHz~30GHz

Pentium® IIPentium® II

Inflection PointInflection PointInflection PointInflection Point

When Power Doesn’t Scale …

Hot Plate

Nuclear Reactor

Rocket Nozzle


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http://blogs.intel.com/idf/2010/04/moores_law_after_32nm.php

http://www.scu.edu/engineering/ee/images/John_Chen_1.jpg

http://www.intel.com/pressroom/kits/bios/mbohr.htm

Power Efficiency is the Main Goal

“Achieving very high operating frequencies is no longer the prime target for new microprocessors. Instead, the goal has shifted to delivering higher performance combined with lower power. “Power efficiency” is the main scaling goal for chips used both in small hand held devices and in large data centers.”

–Mark T. Bohr, Intel Senior Fellow

Intel


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• Power budgets of leading general purpose (MPU) and special purpose (ASP) processors

ClockClock

MPU1

Logic

Mem

I/O

ClockClock

MPU2

Logic

Mem

I/O

ClockClock

ASP2 Logic

MemI/O

ClockClock

ASP1

LogicMem

I/O

Jan Rabaey, “Low Power Design Essentials”, various references

Leading Processor Power Budgets


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Power• Increases as skew and jitter

decrease• Insertion delays increase,

longer buffer chains, power increases

Timing• Use skew to improve timing

IR-Drop• Increases as skew decreases • Lower drop-> lower margin->

lower voltage-> less power• Reliability & noise• During test can cause good

die to fail

Packaging• Ldi/dt, IR drop, thermal

considerations

∆

Power

Power

“0-skew” clk

“∆∆∆∆-skew” clk

clk

Clocks


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• Cores per die continues to increase

• Each core is a candidate for its own power island

• As cores increase so do operating modes

• Multi-Core chips are impractical w/o low-power design

April 2003April 2003

SingleSingle--Core 130nmCore 130nm April 2005April 2005

DualDual--Core 90nmCore 90nm

September 2007September 2007

QuadQuad--Core 65nmCore 65nmJune 2009June 2009

HexaHexa--Core 45nmCore 45nm

Low-Power Design and Multi-Core


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Cell Phone Chip ExampleCell Phone Chip ExampleCell Phone Chip Example

More than 21 mode/corner scenarios

Wally Rhines' DesignCon 2009 Keynote Address: “Common Wisdom Versus Reality in the Electronics Industry”, February 3, 2009

Low-Power Design Requires MCMM


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� Complexity Grows as More Domains are Added

Island2:0.9v-1.5v

1.2v-1.8v

Island2:0.9v-1.5v

1.2v-1.8v

Island1:0.9v-1.5v

ON/OFF

Island1:0.9v-1.5v

ON/OFF

Core:Core:1.2v1.2v--1.8v1.8v

Concurrent Power and Timing Closure for Multi-Voltage Designs


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• Tools and methodologies are always chasing the available capabilities of the existing technologies

• Tools and methodologies are always chasing the available capabilities of the existing technologies

EDA Waves


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• Increased design complexity due to the shear number of available gates demands higher-level tools

• Increased design complexity due to the shear number of available gates demands higher-level tools

The Next Big Wave


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Design and Optimization in the ESL Domain has the Biggest Impact on Power

Source: LSI Logic

Architectural

RTL Synthesis

Gate

Layout

0% 20% 40% 60% 80% 100%

Power Optimization Potential

Why Optimize Power at the Architecture?


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ESLESL

(Behavioral)(Behavioral)

20%20%

ESLESL


30%30%

ESLESL


40%40%

ESLESL


50%50%

ESLESL(Architectural)(Architectural)

20%20% ESLESL(Architectural)(Architectural)

20%20% ESLESL(Architectural)(Architectural)

30%30%ESLESL

(Architectural)(Architectural)

30%30%

RTL 10%

RTL 10%

RTL 10%

RTL 10%

Physical 10%Physical 20%

Physical 40%Physical 50%

2009 2011 2013 2015

Evolving Role of Design Phases in Overall System Power Minimization

Source: The International Technology Roadmap for Semiconductors (ITRS), 2009: Design


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Bill Dally‘s 46th DAC Keynote Address: “The End of Denial Architecture and the Rise of Throughput Computing”, July 29, 2009

“I want high-level tools to help me do design exploration.”“I want high-level tools to help me do design exploration.”

Power tools for architecture explorationRapid evaluation of the power and perfimpact of architecture tradeoffsEnd-of-flow tools are not sufficient

Low-power XStorage arrays, interconnect, etc…Custom design for power, not perfOptimized Vdd, Vt

Power

Bill Dally Sr. VP Research, Nvidia

Low-Power Architectural Exploration


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3.993.99

34.634.6

Source: “802.11a Transmitter: A case Study in Microarchitectural

Exploration”, N. Dave et. al., Proceedings of MEMOCODE 2006

8.6x power variation resulted from architecture tradeoffs

Transmitter Transmitter

DesignDesign

(IFFT Block)(IFFT Block)

Min. Freq. to Min. Freq. to

Achieve Req. RateAchieve Req. RateAreaArea

(mm(mm22))

Average Average

PowerPower

((mWmW))

Comb ( 48 bfly4s ) 1.0 MHz 4.91 3.99

Piped ( 48 bfly4s ) 1.0 MHz 5.25 4.92

Folded ( 16 bfly4s ) 1.0 MHz 3.97 7.27

Folded ( 8 bfly4s ) 1.5 MHz 3.69 10.90

Folded ( 4 bfly4s ) 3.0 MHz 2.45 14.40

Folded ( 2 bfly4s ) 6.0 MHz 1.84 21.10

Folded ( 1 bfly4 ) 12.0 MHz 1.52 34.60

~8.6x~8.6x

Architectural Impact on Low-Power


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201020102009200920042004 20052005 20062006 20072007 20082008

½½ NodeNode

DFM AFDFM AF

Stat Stat TimTim’’gg

PwrPwr MgmtMgmt

DFMDFM

TimTim’’gg CFCF

HierHier FlowFlow

SI CFSI CF

PwrPwr CFCF

RF 5.0RF 5.0 RF 6.0RF 6.0 RF 7.0RF 7.0 RF 8.0RF 8.0 RF 9.0RF 9.0

De

sig

n C

ha

lle

ng

es

De

sig

n C

ha

lle

ng

es

ESL/HLS

RF 10.0RF 10.0 RF 11.0RF 11.0

SiPSiP

TSMC Sees the Importance of This Too


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Example: Power Down / Up Sequence

Power down sequence correctly

executed for isolation, retention & power

Output values restored at power up

Corruption of internal nets during power down

Outputs remain at isolated value

during power downOutput values saved during retention


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2929

Reduce Power During TestReduce Power During Test Test for LowTest for Low--Power DesignsPower Designs

� Design partitioning— Test in multiple sessions— Untested cores use low

power

� Low-power ATPG— Reduce switching during:

– Load– Capture– Unload

— Power metrics reporting— Constant flow compactor— ATPG gater control

� Power information— UPF/P1801

� Test in presence of low-power features— DRC— ATPG

� Test of low-power features— Power gating control logic— Retention cells— Isolation cells— Level shifters

Low-power Test Considerations


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http://techon.nikkeibp.co.jp/article/HONSHI/20090527/170863/

Packaging Impacts Power

• “These days about half of the dissipation in microprocessors comes from communication with external memory chips. If these chips are stacked together in 3D, communication energy cost might drop to a

tenth.”

– Bernard Meyerson, CTO of the

Systems & Technology Group, IBM


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• ICs have a power problem

Trends:

– Lower & Multiple voltages/IC

– Higher currents

– Lower voltage supply tolerances

• PCB power distribution

networks are more complex

– Multiple PDNs on single PCB

– Requires “jigsaw” of split power / ground planes

– Over-conservative design increases cost

Power Issues Extend to the Board


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TLM-Based

ESLPower-Aware Models

TLMTLM--BasedBased

ESLESLPowerPower--Aware ModelsAware Models

RTL & Gates

Power-Aware

RTL & GatesRTL & Gates

PowerPower--Aware Aware

HLS

Architectural

Trade-Off Analysis

HLSHLS

ArchitecturalArchitectural

TradeTrade--Off Analysis Off Analysis

Place & Route

Multi-Corner Multi-Mode

Place & RoutePlace & Route

MultiMulti--Corner MultiCorner Multi--ModeMode

Test

Power-Aware Test

Low-Power Test

TestTest

PowerPower--Aware TestAware Test

LowLow--Power TestPower Test

Formal Checks

Power Rule Checking

Formal ChecksFormal Checks

Power Rule CheckingPower Rule Checking

Clock Crossings

Multiple Domain issues

Clock CrossingsClock Crossings

Multiple Domain issuesMultiple Domain issues

LVS / DRC

Layout-Level

Power-Aware Checks

LVS / DRCLVS / DRC

LayoutLayout--LevelLevel

PowerPower--Aware ChecksAware Checks

DesignDesign VerificationVerification

TLM-Based


TLMTLM--BasedBased


HLS

Architectural

Trade-Off Analysis

HLSHLS


TradeTrade--Off AnalysisOff Analysis

Test

Power-Aware Test

Low-Power Test

TestTest



Place & Route




RTL & Gates

Power-Aware


PowerPower--AwareAware

Formal Checks

Power Rule Checking



Clock Crossings

Multiple Domain Issues


Multiple Domain IssuesMultiple Domain Issues

LVS / DRC

Layout-Level

Power-Aware Checks

LVS / DRCLVS / DRC



IEE

E S

td 1

80

1™

-20

09

IEE

E S

td 1

80

1IE

EE

Std

18

01™™

-- 20

09

20

09

Low-Power Flow Solution

TLM-Based


TLMTLM--BasedBased


HLS

Architectural

Trade-Off Analysis

HLSHLS


TradeTrade--Off Analysis Off Analysis

Test

Power-Aware Test

Low-Power Test

TestTest



Place & Route




RTL & Gates

Power-Aware


PowerPower--Aware Aware

Formal Checks

Power Rule Checking



LVS / DRC

Layout-Level

Power-Aware Checks

LVS / DRCLVS / DRC



Clock Crossings

Multiple Domain Issues


Multiple Domain IssuesMultiple Domain Issues


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• Rescued by New Process Technology?

– Not Likely Soon

– Probably Will Get Worse Before it Gets Better

• Standardized Formats – Significant Aid to Design & Verification Flows

• Power is a System-Wide Optimization

• Biggest Bang for the Buck is in Front-End Design

Summary

Bary pangrle mentor track d

Education

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