Background

• Physicist in Particle Physics.• Data Acquisition and Triggering systems.• Specialising in Embedded and Real-Time

Software.

• Since 2000 Project Manager of CMS Silicon Strip Tracker Readout.

• Major deliverable of UK to LHC programme at CERN. 22 SY effort over 6 Y.

TBU Electronics – CMS FED• Major electronics system for CMS experiment

Silicon Strip Tracker Off-Detector readout at the Large Hadron Collider facility CERN Geneva

• 500 Large Complex Electronic Boards (FEDs)– ~ 45 K ADC channels– Massively Parallel FPGA based Processing

> 1 TERA-BYTE / sec (~2,000 CDROMs/sec)

• Designed, implemented and tested by Technology~ £ 4 Million project over several years in collaboration with Imperial College, PPD, CERN.

• Manufactured in Partnership with UK Industry eXception EMS Ltd received CMS Gold Award 2006

• Knowledge Transfer

• Delivered to CERN on budget & ahead of schedule

CMS Awards

x 500

RAL

Commissioning at CERNSlide shown at CEO Staff Talk July 2006

CMS FED - Project Manager Role• Led project from Feasibility stage through Design,

Implementation to Delivery. Leading team of ~ 6 engineers

• Low-level software for FPGA design verification. • Major role in all activities from capturing Requirements to

Board & FPGA design specification, manufacture and Qualification.

• Reporting to CMS UK Management Committee, CMS/Tracker management CERN.

• Presentations at International Conferences.

• Maintained effective collaboration with project stakeholders, Imperial College, PPD, CERN.

• Negotiated and managed FED manufacturing contract £1.75M on behalf of CMS UK and CERN.

TBU – Electronics Systems Design Group

• Section leader in ESDG (2 staff).

• Deputy Group Leader (15 staff).

• Control Group Budget.

• Manage SLHC, ASIC (non MAPS) accounts.

• In charge of Communications, Software Training, PC and FPGA related purchasing.

• Active formulating group Strategy via Business Plan.

Future Roles

• Complete Installation and Commissioning of FEDs for LHC pilot run 2007.

• Lead R&D team in Embedded Systems based on FPGAs.

• Apply to New Challenges and Opportunities:– SLHC, ILC– Diamond, XFEL +…

• Offer to CCLRC : Technical expertise, Management abilities and Scientific world view.

Additional Slides

Readout Silicon Tracking detector.

~ 10 million Silicon Strip channels

ON Detector: APV25 pipeline chips

@ L1 Trigger: MUX APV Frame output

Analogue Data readout via Optical links

(100 kHz APV Frames: Header + Strip Data)

OFF Detector: Front-End Drivers (FED)

Digitise / Zero Suppress / DAQ readout

~ 500 x 9U VME64x boards (incl spares)

96 ADC channel boards

Each 25 K channels per event.

~ 3 GB/s input

~ 50 MB/s/% output

DAQ

CountingRoom

On Detector (Radiation Hard)

FPGA

25

VME 9U FEDs

HybridFront-End HybridSilicon Strips 70m

Tracker Readout

And Tracker needs 500500 of them

Large Complex Electronics Board

NBNB One FED One FED board is doing the job of many cratesmany crates of electronicsof tracker readout on last generation of HEP experiments eg HERA

Major manufacturingmanufacturing taskOptical

Digital34 x FPGAs

Analogue Output: CDAQ

Input: Tracker FEnds 25K MUX stripsto ~100 ADC channels@ 3 Gbytes3 Gbytes/sec

<= 200 Mbytes200 Mbytes/sec

Q. How to support a Board with re-programmable digital logic during operation for 10 years ? ...

Digital Logic Digital Logic Re-ProgrammableRe-Programmable

FirmwareFirmware (VHDL, Verilog) (VHDL, Verilog)

FField ield PProgrammable rogrammable GGate ate AArraysrrays

SoftwareSoftware

Data Reduction & ProcessingData Reduction & Processing

System ArchitectureSystem ArchitectureNB System Interfaces criticalNB System Interfaces criticalTracker FE, DAQ, Trigger ...Tracker FE, DAQ, Trigger ...

Hit Finding Event Builder

VME

1. Custom CMS TestsAt Assembly Plant

Boundary ScanAnalogue

3. Tests at CERNPrevessin 904

B186 Tracker Integration

2. Tests at RAL

Optical, SLINK,Full crate

4. Installation at CMSUSC55

0. Quality Controlsduring Assembly

processAOI, X-ray

RAL Test Rig

Assembly Company FED

“Pipeline” with each stage taking ~ 1 month and containing ~ 50 FEDs

VME SLINKTransition card

CERN Test Rig

eXception EMS Ltd UK

FED Quality Assurance

Xilinx Virtex 4 System on Chip

Field Programmable Gate Array

+ Embedded IP Blocks

Hardware Programming Language RTL; VHDL

System Partitioning ; Operating Systems

Software Programming Language; Ce.g. PPC, Ethernet MAC

FPGAs

CPUsSLHC DAQ?