Avocet Image Sensor-Info - Future Electronics · MLX75411 (Avocet) Image Sensor Datasheet Page 2 of...

MLX75411 (Avocet) Image Sensor Datasheet

(Advanced Information)

Avocet Image Sensor Information Brief

Feature List

• Melexis’s low noise, low power rolling shutter

CMOS imaging technology

• 1024 x 512 Image Array, with programmable sub-

window

• ~⅓ optical format for 1024x512

• Autobrite® Wide Dynamic Range (>150db), with

fully automatic, semiautomatic and manual

control

• Monochrome, standard Bayer and custom color

filter arrays available

• Integrated image optimization and noise

reduction tuned for automotive applications

• AutoviewTM

Histogram Remapping

• 2-Wire serial interface for control

• Parallel data (8/10/12 data bits +

CLK/HSYNC/VSYNC) provides direct connect to

common video components and video enabled

DSP’s

• Start of production Q1 2010

• Operating Temperature Range:

-40C to +85C full performance

(>+85C to +115C degraded performance)

• Storage Temperature Range: -40C to +125C

Applications

• Night vision

• Forward looking ADAS applications; collision

warning, pedestrian detection, lane departure

warning, traffic sign/light recognition

• Blind spot monitoring and detection

• Color rear-view cameras

• Driver monitoring for drowsiness

• Environments that require high sensitivity, wide

dynamic range (WDR).

• Machine Vision applications that require high

quality monochrome or color with high sensitivity.

Specification Avocet

Active Pixel Resolution 1024 x 512

Optical format ~⅓”(6.45mm)

Pixel size 5.6μ square

Pixel type 3T

Maximum frame rate 60fps (full resolution)

Input clock range 20 – 54 MHz

Exposure time range at full

resolution and speed

1.0μs – 16.7 ms

Control interface 2 Wire Serial Slave

Video interface 12-bit LVTTL (data, hsync,

vsync, and clock)

Signal processing Defect pixel interpolation

FPN correction

Histogram Optimization

Dark Current correction

Sharpening

Scanning modes Progressive

Pseudo-Interlaced

Subsample

Subwindow

Event Synchronization

Ordering Information

Part

Number

Description

MLX75411 RoHS-compliant Monochrome Image

Sensor

MLX754xx RoHS-compliant Color RGGB Image

Sensor

MLX754xx RoHS-compliant Color RGBi Image

Sensor

CONFIDENTIAL

This document is being provided on a confidential basis and is intended strictly for use by a limited number of interested parties for the sole

purpose of determining potential interest in pursuing a transaction with the Company. By accepting this document, each recipient agrees to treat

the information contained herein in a manner consistent with its own information of a confidential nature


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1. Document Version

Version Date Notes

1.1 05/9/2009 Initial version

1.2 6/18/2009 Updated with register information, added appendices, added detail to

chip operation sections, and added reference circuits.

1.3 7/14/09 Updated electrical parameters, updated board layout guidelines, updated

mechanical information.

1.4 7/21/09 Updated with review comments.

1.5 7/27/09 Updated register reset values to account for changes in firmware.


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Table of Contents Feature List........................................................................................................................................... 1 Applications.......................................................................................................................................... 1 Ordering Information........................................................................................................................... 1

1. Document Version ........................................................................................................................... 2 2. Device Overview .............................................................................................................................. 5

2.1. Avocet Image Sensor Overview ............................................................................................... 5 2.2. Sensor Architecture ................................................................................................................. 6 2.3. Package Options....................................................................................................................... 7 2.4. Pixel Array Description & Operation........................................................................................ 7 2.5. Interfaces ................................................................................................................................. 8

2.5.1. Pin description ................................................................................................................. 8 2.5.2. Pixel data output interface .............................................................................................. 9

2.5.2.1. 12/10/8 bit digital video mode (default) ................................................................. 9 2.5.2.2. Packetized video mode.......................................................................................... 10

2.5.3. Two Wire Serial Slave Interface ..................................................................................... 11 2.5.4. Two Wire Boot Loader Interface.................................................................................... 11 2.5.5. GPIO Interface................................................................................................................ 11

2.6. On-chip Algorithms ................................................................................................................ 12 2.6.1. Autobrite® Wide Dynamic Range .................................................................................. 13

2.6.1.1. Autobrite® Feedback Loop..................................................................................... 13 2.6.1.2. Autobrite® Advantages .......................................................................................... 14

2.6.2. Column FPN Correction ................................................................................................. 15 2.6.3. Dark Current Correction ................................................................................................ 16 2.6.4. Spatial Filtering: Defective Pixel Correction .................................................................. 17 2.6.5. Spatial Filtering: Sharpening .......................................................................................... 18 2.6.6. Autoview™ Histogram Optimization.............................................................................. 19

2.7. Device power up behavior and initialization ......................................................................... 20 3. Device Electrical Parameters ......................................................................................................... 21

3.1. Maximum Electrical Ratings................................................................................................... 21 3.2. DC Electrical Characteristics................................................................................................... 22 3.3. AC Electrical Characteristics (Non-inverted PIXCLK, default) ................................................ 23 3.4. AC Electrical Characteristics (Inverted PIXCLK, with 18ns clock period) ............................... 23 3.5. Optical Characteristics ........................................................................................................... 24

4. Disclaimer....................................................................................................................................... 25


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Table of Figures Figure 1 - Avocet Architecture Block Diagram......................................................................................... 6 Figure 2 - 56-pin TPBGA package and bare die........................................................................................ 7 Figure 3 - Digital Video Interface Line Timing........................................................................................ 10 Figure 4 - Digital Video Interface Frame Timing .................................................................................... 10 Figure 5 - Autobrite® feedback and control mechanism....................................................................... 14 Figure 6 - Images Captured without (left) and with (right) Autobrite................................................... 14 Figure 7 - Sharpening Filter (Unsharpened Image)................................................................................ 18 Figure 8 - Sharpening Filter (Sharpened Image) .................................................................................... 18 Figure 9 - Avocet Sharpening Matrix Multiply....................................................................................... 18

Table of Tables Table 1 - Avocet image sensor highlights ................................................................................................ 5 Table 2 - On chip algorithms.................................................................................................................. 12 Table 3 - Electrical Specifications: Maximum Ratings ........................................................................... 21 Table 4 - Electrical Specifications: DC Electrical Characteristics............................................................ 22 Table 5 - Electrical Specifications: AC Electrical Characteristics............................................................ 23 Table 6 - Electrical Specifications: AC Electrical Characteristics............................................................ 23 Table 7 - Specifications: Optical Characteristics .................................................................................... 24



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2. Device Overview

2.1. Avocet Image Sensor Overview

The Avocet image sensor is manufactured using advanced 0.18μm CMOS imaging process,

integrates a high-sensitivity array, a fully-featured digital imaging processing pipeline and camera

control functions into a single module. Avocet is a 1024 x 512 pixel, ~⅓” optical format CMOS

image sensor. For VGA applications, the center 640 x 480 pixels can be used in a ¼” format which

can reduce the size and/or cost of the matching optical components. The device captures either

Monochrome or Bayer-pattern color still pictures.

Table 1 - Avocet image sensor highlights

Specification Avocet Comments

Active Resolution 1024 x 512 Wider horizontal resolution to meet the next generation ADAS

requirements

Optical format ~⅓”(6.45mm) Center ¼ “ can be used for VGA resolution

Pixel size 5.6μ square Optimized for sensitivity at 1024x512 resolution

Pixel type 3T Optimized for WDR and Sensitivity

Max frame rate 60fps At full resolution

Input clock range 20 – 54 MHz Options for clocking: Crystal input, Oscillator

Exposure time range 1μs – 16.7 ms At 54MHz and 60fps, at full resolution and speed. Minimum barrier

time 1.22us.

2 Wire Boot Loader

Interface

Used to load register settings on recovery from a reset. Must be

accessible (for programming of serial PROM) via other control

interfaces.

Control interface

2 Wire Serial Slave 2-Wire, low speed, serial control interface used for short distances.

Does support broadcast writes for writing multiple imagers.

Video interface LVTTL 12-bit Monochrome or Raw Color.

Pixel clock, vsync and hsync compatible with the DSP’s.

(i.e. TI DaVinci or ADI Blackfin)

Signal processing Defect pixel interpolation

FPN correction

Histogram Optimization

Dark Current correction

Sharpening

Sensor provides on-chip processing required for vision applications or

monochrome display applications. (Color processing is not included in

on-chip functions.)

Progressive Required to support machine vision applications

Interlaced Required to support monochrome display based applications;

supports NTSC timing – can generate video using 10 bit DAC.

Subsample 2x and 4x vertical subsampling

Subwindow Single rectangular region. The starting point of the x- and y-address is

programmable, as well as the window size.

Scanning modes

Event Synchronization Sync to external event



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2.2. Sensor Architecture

The Avocet CMOS image sensor is a digital image sensor targeted at video capture in automotive,

industrial and transportation safety applications. The Avocet sensor is available as either a color

or monochrome imaging device.

In a monochrome system, image processing is performed on the Avocet as a single chip solution

and the Color Filter Array (CFA) is eliminated to maximize device sensitivity.

In a color system Avocet acts as a slave in a system controlled by a separate Image Signal

Processor chip through one of the external interfaces delivering raw single images or video-like

streams of color Bayer-patterned images. The sensor captures the images at the required speed,

exposure, and gain, and the external device is responsible for all further image processing such as

color demosaicing, white balance, and automatic exposure/gain control.

Figure 1 - Avocet Architecture Block Diagram



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2.3. Package Options

Avocet is offered in two package solutions: a 56 pin TPBGA and a bare die for use in chip-on-

board.

Figure 2 - 56-pin TPBGA package and bare die

2.4. Pixel Array Description & Operation

The pixel array is composed from 5.6um square sensing elements based on Melexis’s 3T pixel

architecture. The Sensor array can either be monochrome or have a set of color filters applied

depending on the application requirements.

The image sensor operates using an electronic rolling shutter. This maximizes the amount of

integration time available by overlapping the readout with the “reset” of a pixel to begin

integration.

Avocet operates in an adaptable, programmable Wide Dynamic Range (WDR) mode maximizing

sensitivity while providing uncompromising dynamic range.



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2.5. Interfaces

Avocet has four main interfaces: pixel data output, two wire serial slave, two wire serial master,

and GPIO. Each of these interfaces is described below.

2.5.1. Pin description

56 TPBGA Ball Symbol Type Description

[H3, E2, F2, E1,

F1, G1, H1, C2,

B4, A4, C4, B5]

PIXD[11:0] OUTPUT Parallel pixel data output bit 11 (MSB) to 0 (LSB)

H8 HSYNC OUTPUT Line valid. Asserted high when PIXDAT data is valid

F3 VSYNC OUTPUT Frame valid. Asserted high when PIXDAT data is valid

C3 PIXCLK OUTPUT Pixel clock out.

E8 SDAT I/O 2-wire slave serial data interface.

H7 SCLK INPUT 2-wire slave serial clock interface.

G8 BLIDAT I/O 2-wire serial boot loader interface data.

F8 BLICLK OUTPUT 2-wire serial boot loader interface clock.

D1 ADDR0 INPUT 2-wire slave serial interface address bit select [0]

D2 ADDR1 INPUT 2-wire slave serial interface address bit select [1]

C6 XTALIN INPUT System clock input.

C5 RESET_N INPUT Active low image sensor reset.

B1, B8, G4, H6 VDDA SUPPLY Analog power supply 3.3V

A1, A8, G5, H5 GNDA SUPPLY Analog Power supply ground

B2, B7, G3 VDDD SUPPLY Digital power supply 1.8V

A2, A7, H4 GNDD SUPPLY Digital Power supply ground

B3, B6, H2 VDDIO SUPPLY I/O pad power supply 3.3V

A3, A6, G2 GNDIO SUPPLY I/O Power supply ground

F6 VREFM REF Analog reference voltage

F5 VREFP REF Analog reference voltage

F4 VCM REF Analog reference voltage

G7 GPIO INPUT Leave unconnected if unused.

F7 GPIO2 INPUT Leave unconnected if unused.

E7 GPIO3 INPUT Leave unconnected if unused.

A5 RSVD_1 INPUT Connect to GND

D8 RSVD_2 INPUT Connect to GND

C8 RSVD_3 INPUT Connect to GND

G6 RSVD_4 OUTPUT Connect to GND

D7 RSVD_5 INPUT Connect to VDD

C7 RSVD_6 OUTPUT Leave unconnected

C1 NC N/C No connection



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2.5.2. Pixel data output interface

The image data from Avocet is sent via a pixel interface. The interface is designed to be

compatible with standard interfaces to DSP’s (TI DaVinci and ADI Blackfin) for image data

transfer.

Data is transferred as frames (images), one line at a time from the top of the image to the

bottom of the image. Each line is transferred in contiguous data bursts from the left of each line

to the right.

The interface consists of the following pins:

• PIXD[11:0] – 12/10/8 bit pixel data interface. In the 10 and 8 bit modes, the lower order

bits are not used and are held to zeros.

• HSYNC – This signal indicates horizontal sync or data valid. It can be configured as active

high or active low by changing on-chip configuration registers.

• VSYNC – This signal indicates vertical sync. It can be configured as active high or active

low by changing on-chip configuration registers.

• PIXCLK – This is the output clock that should be used to clock in HSYNC, VSYNC, and

PIXD[11:0] on the receiving end. By default, the output registers are clocked on the

rising edge of this clock. This can be changed so that the negative edge corresponds to

the data changing by an on-chip configuration register.

2.5.2.1. 12/10/8 bit digital video mode (default)

When configured in digital video mode, the chip outputs pixel data on the PIXD bus and

signals start of line and frame with HSYNC and VSYNC.

The chip will output one pixel per clock at the input clock rate; with data changing on the

rising edge of PIXCLK by default (can be changed to negative edge if desired).

HSYNC will be asserted for every valid pixel of a line (1024 by default), and de-asserted during

h-blank and v-blank intervals. By default, h-blank will be for 298 clocks between valid lines.

VSYNC will be asserted for every valid line, and will rise coincident with the rise of the first

HSYNC of the frame. It will drop coincident with the fall of the last HSYNC of the frame.



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The digital video timing is as follows:

Figure 3 - Digital Video Interface Line Timing

Figure 4 - Digital Video Interface Frame Timing

2.5.2.2. Packetized video mode

The chip can also be configured to transmit all relevant information on the PIXD bus (including

start of line and start of frame indicators). The video data is sent in one line per “packet”,

with packet start, stop, and CRC. Additional status information is also transmitted in the video

stream. In this mode, the start of line and start of frame are sent framed in separate

“packets” on the PIXD bus. As a result, the HSYNC and VSYNC lines are not used.

For further information on the packetized video mode and its format, please contact Melexis.



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2.5.3. Two Wire Serial Slave Interface

Avocet provides an interface to all configuration and control of the imager sensor and image

processing functions. This two wire interface is comprised of a single clock line and a single data

line. A serial protocol is used to address the chip and to read and write data.

2.5.4. Two Wire Boot Loader Interface

Avocet is capable of using an external PROM to control the behavior of the device after power

up and to augment the internal processing. It does this through a 2 wire interface that uses the

same protocol as the two wire serial slave interface. The only supported use of this interface is

for the connection of the external PROM to control the power up behavior.

2.5.5. GPIO Interface

Avocet has 3 GPIO pins that can be configured as inputs or outputs. The use of these pins is for

future expansion of device capabilities. Consult Melexis for more details.



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2.6. On-chip Algorithms

The image processing algorithms for Avocet are described in this section. Each algorithm is

individually controlled with an enable/disable. All of the algorithms also have individual control

bits that allow tuning and control of the behavior of the individual algorithms. The Spatial

Filtering algorithms are not color aware, and should be disabled if color filters are present.

Table 2 - On chip algorithms

Algorithm Section Description

Autobrite® Avocet Timing Sequencer An Automatic Exposure (AE)

controller that regulates the

dynamic range compression

of high-dynamic-range pixels.

Column FPN removal FPN Offset Correction Uses electrical black from

DAC’s to compensate for

ADC and column circuitry

offset mismatches.

Dark Current subtraction Dark Current Offset and Gain

Correction

Performed using optical

black (dark row) averages.

Defective Pixel Correction Spatial Filtering

Sharpening Filter

Done within a single 3x3

kernel

Image Statistics Statistics Feeds image information to

apply to the next frame for

Autobrite, spatial filtering,

and Melexis’s histogram

optimization

Autoview™ Melexis Histogram

Optimization

Performs automatic

histogram equalization, or

gamma correction, or a user-

programmable transfer

function



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2.6.1. Autobrite® Wide Dynamic Range

Autobrite uses the variable height/multiple reset method and a feedback loop to meet the

criteria for wide dynamic range cameras. Autobrite uses combined technologies to expand

dynamic range and a straightforward standard, three transistor CMOS pixel to provide reliability

and cost-effectiveness. No additional frame buffers or post processing is required. Based on

research conducted at the Massachusetts Institute of Technology, Autobrite controls the pixel

through Melexis proprietary variable height/multiple reset method. A complete feedback loop

simultaneously controls the integration time and dynamic range expansion for total adaptability

and programmability.

2.6.1.1. Autobrite® Feedback Loop

Achieving wide dynamic range through an image sensor with linear response at low

illumination and non-linear response at high illumination solves only part of the problem. To

complete the solution, the automotive camera must be able to decide which response curve

to use. Furthermore, system designers must be able to override the automated decision to

customize the response for specific applications. Autobrite uniquely meets these criteria with

its key features: adaptability and programmability. Autobrite includes a mechanism to

dynamically adjust both the response curve and the total integration time based on the scene

being observed. Essentially, the dynamic range is expanded in real time by changing the

timing and height of the reset signal. The control mechanism can be configured to

automatically adapt to each environment or programmed for a specific application, thereby

providing performance that is unmatched by other approaches for achieving wide dynamic

range. “Figure 5 - Autobrite® feedback and control mechanism” illustrates the Autobrite

control mechanism.

The control loop starts with the image sensor capturing an image. Registers acquire statistics

of the scene such as average intensity and number of pixels that exceed a threshold. A

proprietary control mechanism, which can be tailored to a specific application, uses the

statistics to select the optimum response curve and integration time. A multiplexing device

inputs the signals and allows either the calculated values or user-supplied values to be fed to

the voltage and timing control, which generates the barrier voltage(s) for the image sensor.

Simultaneously calculating both the integration time and the required dynamic range

expansion allows the image sensor to settle on optimal settings very quickly. This fast

response time is critical in applications where dramatic changes in the lighting conditions

occur quickly, such as the appearance of headlights from other vehicles. Another advantage

of this approach is that the collection of the statistics and the control algorithms can be

tailored to a specific application. Users can program Autobrite to meet specific requirements

of their application.



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Figure 5 - Autobrite® feedback and control mechanism

For example, system engineers can program Autobrite to:

• Select a specific region of interest within the image frame that Autobrite will use to

optimize the integration time and response curve.

• Select a specific integration time and response curve, overriding the automated

adjustment.

• Select a maximum integration time or response curve that the automated adjustment

is not to exceed.

• Adjust the speed of adaptability to respond more quickly or slowly to lighting changes.

• Manually adjust the height and timing of the barrier voltages.

2.6.1.2. Autobrite® Advantages

Figure 6 provides a side-by-side comparison of images captured with and without Autobrite.

In the image on the left, the intra-scene dynamic range clearly exceeds the dynamic range of

the camera, resulting in lost details in both the light and dark regions. In the image on the

right, Autobrite enables the same scene to be captured with complete visual details even in

the extremes of brightness and darkness.

Figure 6 - Images Captured without (left) and with (right) Autobrite



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2.6.2. Column FPN Correction

Fixed Pattern Noise or FPN correction is meant to correct for the differences in the ADCs that

are used to convert the pixel voltages to pixel values and the column circuitry that connects the

pixels to the ADCs. Because ADCs are not perfect, they do not always convert a given voltage to

the same value. The differences in the values for any single ADC tend to be small, but the

differences between two ADCs converting the same voltage can be noticeable. The transistors

and wires that carry the pixel voltages to the ADCs can experience similar differences. This

causes pixels in one ADC or column to appear brighter or darker than another. Differences

between two ADCs lead to banding in the image with the bands being equal to the width of the

multiplexers that feed the ADCs. Differences in the column circuitry lead to differences

between adjacent columns or striping. This kind of noise is very visible in the output image

because it is not random noise. It also creates false edges or differences in contrast between

columns. These differences will be exaggerated by pixel processing algorithms like sharpening.

They can also cause machine vision applications problems with object detection because of the

extra false edges in the image.

To correct for this, the differences between ADCs and column circuits are measured by applying

known voltages to each column and using the ADC to measure the voltage. A near black signal

is applied to each column to allow measurement of the offset. Black is not used because some

of the offsets might be negative. These measurements are saved for each column in a RAM

structure and used to calculate the correction factors for each column.

Variables that affect the FPN values:

• Process differences - Because ADCs, transistors, and wires are not manufactured

identically, these differences can lead to differences in the ADC output when converting

a given voltage.

• Temperature - Changes in temperature will change the analog behavior of the ADCs and

transistors. Higher temperatures typically lead to higher differences between ADCs,

transistors, and wires and therefore higher FPN.

• Voltage - Changes in voltage will change the analog behavior of the ADCs and transistors.

Lower voltages typically lead to higher FPN.

Because both temperature and voltage can vary over time, FPN correction is designed as a

dynamic correction process that constantly measures the differences and adjusts the correction

factors.



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2.6.3. Dark Current Correction

Dark current correction is meant to correct for the average leakage of all pixels. Because pixels

are not perfect, they leak current over time even if there is no light shining on them. This causes

pixels to appear unnecessarily bright. To correct for this, some pixels on the array are covered

with a metal shield that is meant to block all light from reaching them. These pixels can then be

read and the results averaged to obtain the "average" leakage value for all the pixels in the

array. This “average” leakage is used to correct the active area.

Variables that affect the dark current values:

• Process differences - Because not all pixels manufactured identically, some leak more

than others.

• Temperature - The higher the temperature, the more current a pixel will leak.

Temperature is a relatively slow change on the imager in comparison to frame times. Quick

changes in the dark current values are probably due to other non-leakage causes. To help

reduce the effects of these other fast changing causes, a low pass filter is included on the dark

current average. Without this low pass filter, minor changes in the dark current value could lead

to a fast frame to frame change of the correction value. This would cause frame to frame

flickering. The hardware uses a low pass filter and caps the maximum dark current value to

counteract any short term variation in the dark current measurements.

The device also offers a manual mode of dark current correction. When in manual mode, the

dark current measurements and the correction value can be written via the 2-wire serial bus.



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2.6.4. Spatial Filtering: Defective Pixel Correction

When the image sensor is manufactured, not all pixels are created identically. There are often

pixels in the image array that respond differently than the others. Sometimes these pixels are

stuck off or stuck on. This results in white or black pixels in the output image. But more often,

there are pixels that respond to the light more quickly or more slowly than average. These

pixels do not appear white or black all the time, but appear lighter or darker than the

surrounding pixels when exposed to the same amount of light. Both types of pixels can be alone

or "clustered" with other defective pixels in groups.

Avocet implements “neighbor comparisons” which takes advantage of the fact that two pixels

next to each other in the array are unlikely to be significantly different than all of their

neighbors. Even when the image has a black or white spot that would be one pixel in size, the

use of imperfect optics leads to light being scattered to adjacent pixels. This tends to smooth

out the transitions from one pixel with its neighbors. The advantage of this algorithm is that the

comparisons are done in real time, without the need for a PROM to record the pixel map. The

algorithm is also capable of handling pixels that become damaged.

Note: The on-chip defective pixel correction algorithm is not color aware, and should be

disabled if color filters are present.



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2.6.5. Spatial Filtering: Sharpening

Sharpening is meant to enhance the contrast differences between adjacent pixels. This has the

visual effect of "sharpening" the focus of an image. Below is a section of an image.

Figure 7 - Sharpening Filter (Unsharpened Image)

Figure 8 - Sharpening Filter (Sharpened Image)

The filter operation is done with a matrix linear convolution operation. A matrix of source pixels

is convolved with a matrix of constants to generate a single value:

Figure 9 - Avocet Sharpening Matrix Multiply

The possible selections for sharpening matrices are (from weakest to strongest):


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2.6.6. Autoview™ Histogram Optimization

Avocet includes a histogram remapping function that maps from 12 bit pixels to 8 or 10 bit

pixels to facilitate data processing and transfer in systems that do not implement the full 12 bit

pixels. The algorithm emphasizes areas in the histogram that contain most of the information

while compressing areas with limited information. This is particularly useful in scenes that

naturally have a somewhat sparse histogram. An automotive night scene is an example where

most of the information is lumped into three luminance bands: headlights and taillights which

are very bright; traffic signs that are of medium intensity; and pavement which is relatively dark.

By emphasizing the regions containing the most information, 12 bits can be reduced to 8 with a

minimum loss of information.

The on-chip hardware is capable of remapping 8 individual segments of the histogram to new

areas. Both the offset and the gain of the remapping are controllable through register settings.

The automatic algorithm uses the image statistics to calculate remapping constants to provide a

good mapping when reducing the number of bits of the pixels.


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2.7. Device power up behavior and initialization

Avocet has an internal power-on reset circuit that will reset the chip after power has reached

acceptable levels. After power-on, the user may optionally download a set of application specific

register values. These values configure the internal circuitry (analog bias levels, register

settings ...) for optimal application specific performance. This initialization may be accomplished

using a standard serial PROM or over the 2 wire interface from a host controller.

From a high level, the power up sequence is as follows:

1. Power is applied to the chip.

2. A clock is applied to the chip. The default programming expects a 27MHz clock, which will

give 30FPS video on the output interface.

3. The on-chip power-on-reset logic holds the chip in reset until the power is stable.

4. All on-chip registers are reset to the default states.

5. If the reset pin is logically high, the chip will be held in reset and the boot sequence is held

at this step. If the reset pin of the chip is not logically high, the chip comes out of reset

with all the power on values and proceeds to the next step in the sequence.

6. The firmware boot sequence takes over. The boot sequence comprises:

a. Query the 2 wire serial master interface to see if a valid PROM is located at device

address 0xA0.

b. If a valid PROM is present, load the contents of the PROM into the chip. If no valid

PROM is present, continue with the boot sequence. The contents of the PROM can

be used to change the default behavior of the device. See section Error! Reference

source not found. for more information about the use of the boot loader interface

and the PROM.

c. Enable the image capture and enable the output to begin transmission of video.

d. Complete the firmware boot by setting register 0x8500 to 0x00, which indicates

the boot process is complete. (Until the boot process is complete, 0x8500 will read

as non-zero.)

7. At this point, the user can change the device operation by using the 2 wire serial slave

interface to set the chip control registers.


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3. Device Electrical Parameters

3.1. Maximum Electrical Ratings

Table 3 - Electrical Specifications: Maximum Ratings

Symbol Description Minimum Nominal Maximum Unit

Vdda Analog supply voltage -5% 3.3 +5% V

Idda Analog supply current mA

Vddio I/O supply voltage -5% 3.3 +5% V

Iddio I/O supply current mA

Vddd Digital supply voltage -5% 1.8 +5% V

Iddd Digital supply current mA

Tstg Storage Temperature -40 +125 C

Topl Operational Temperature -40 +115 C


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3.2. DC Electrical Characteristics

VDDIO = 3.3V (+/- 5%); Tamb=Ambient=25C

Table 4 - Electrical Specifications: DC Electrical Characteristics Symbol Definition Condition Minimum Nominal Maximum Unit

VIH Input high voltage 2.4 - VDDIO + 0.3 V

VIL Input low voltage -0.3 - 0.8 V

IIN Input leakage current No pull-up resistor;

Vin = VPWR or VGND

-2 - 2 uA

VOH Output high voltage IOH = -4.0mA VDDIO – 0.4 - - V

VOL Output low voltage IOL = 4.0mA - - 0.4 V

IOH Output high current VOH = VDDIO -0.7 -7 - - mA

IOL Output low current VOL = 0.7 - - 7 mA

VDDA Analog supply voltage Default settings 3.135 3.3 3.465 V

IDDA Analog supply current Default settings;

XTALIN=27MHz

- 40 62 mA

VDDIO I/O supply voltage Default settings 3.135 3.3 3.465 V

IDDIO I/O supply current Default settings;

XTALIN=27MHz

- 20 20 mA

VDDD Digital supply voltage Default settings 1.71 1.8 1.89 V

IDDD Digital supply current Default settings;

XTALIN=27MHz

- 30 32 mA


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3.3. AC Electrical Characteristics (Non-inverted PIXCLK, default)


Table 5 - Electrical Specifications: AC Electrical Characteristics

Symbol Definition Condition Minimum Nominal Maximum Unit

XTALIN Input system clock frequency 20 27 54 MHz

Clock duty cycle 45 50 55 %

tRCLK Input clock rise time 0.5 2 3 ns

tFCLK Input clock fall time 0.5 2 3 ns

tPDXP XTALIN to PIXCLK

propagation delay

CLOAD = 10pF 1.6 2.6 3.5 ns

tPDPD PIXCLK to valid DOUT[11:0]

propagation delay

CLOAD = 10pF 2.5 3.8 5 ns

tSUD Data setup time -1 -0.5 -0.1 ns

tHD Data hold time 0 0.25 0.5 ns

tPDPH PIXCLK to HSYNC

propagation delay

CLOAD = 10pF 1.2 2.4 3.5 ns

tPDPV PIXCLK to VSYNC

propagation delay

CLOAD = 10pF 1.2 2.4 3.5 ns

3.4. AC Electrical Characteristics (Inverted PIXCLK, with 18ns clock period)


Table 6 - Electrical Specifications: AC Electrical Characteristics

Symbol Definition Condition Minimum Nominal Maximum Unit

XTALIN Input system clock frequency 20 27 54 MHz

Clock duty cycle 45 50 55 %

tRCLK Input clock rise time 0.5 2 3 ns

tFCLK Input clock fall time 0.5 2 3 ns

tPDXP XTALIN to PIXCLK

propagation delay

CLOAD = 10pF 10.8 11.8 12.8 ns

tPDPD PIXCLK to valid DOUT[11:0]

propagation delay

CLOAD = 10pF -4.5 -6 -6.5 ns

tSUD Data setup time 4.5 6 6.5 ns

tHD Data hold time 8 8.5 9 ns

tPDPH PIXCLK to HSYNC

propagation delay

CLOAD = 10pF -6 -6.5 -7 ns

tPDPV PIXCLK to VSYNC

propagation delay

CLOAD = 10pF -6 -6.5 -7 ns


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3.5. Optical Characteristics

Table 7 - Specifications: Optical Characteristics

Parameter Definition Condition Minimum Nominal Maximum Unit

Chief Ray

Angle

Chief ray angle the sensor

has been optimized for.

10 degrees



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4. Disclaimer

Devices sold by Melexis are covered by the warranty and patent indemnification provisions

appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by

description regarding the information set forth herein or regarding the freedom of the described

devices from patent infringement. Melexis reserves the right to change specifications and prices at

any time and without notice. Therefore, prior to designing this product into a system, it is necessary

to check with Melexis for current information. This product is intended for use in normal commercial

applications. Applications requiring extended temperature range, unusual environmental

requirements, or high reliability applications, such as military, medical life-support or life-sustaining

equipment are specifically not recommended without additional processing by Melexis for each

application.

The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall

not be liable to recipient or any third party for any damages, including but not limited to personal

injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special

incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,

performance or use of the technical data herein. No obligation or liability to recipient or any third

party shall arise or flow out of Melexis’ rendering of technical or other services.

© 2009 Melexis NV. All rights reserved

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