Aveek Sarkar, Vice President Product Engineering ......homogeneity of power delivery network (PDN)...
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1 © 2011 Apache Design, Inc. Aveek Sarkar, Vice President Product Engineering & Customer Support Apache Design, Inc.
Transcript of Aveek Sarkar, Vice President Product Engineering ......homogeneity of power delivery network (PDN)...
1 © 2011 Apache Design, Inc.
Aveek Sarkar, Vice President Product Engineering & Customer Support Apache Design, Inc.
2 © 2011 Apache Design, Inc. 2
Stacked die design multi-physics challenges Power and noise modeling
– Concurrent and model based approaches Thermal modeling
– Impact on power, reliability and timing Ongoing work
Outline
3 © 2011 Apache Design, Inc. 3
Multi-physics challenges: – Electrical-, thermal-, and mechanical-
aware design
Cross-domain, organization, company
Simulation Goals
Exploration and planning
Analysis, optimization and sign-off
Stacked Die Design Needs
Inter-die thermal interplay
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Voltage Drop and Power Noise Impact – Top die experience additional voltage drop and coupled noise
from lower die or interposer in the stack-up
– Presence of TSV farm and associated metal/via affect the homogeneity of power delivery network (PDN) for the bottom die
Thermal Impact – Thermal profile due to combined power and thermal signature
from shared micro-bump connections
– Significant impact to power (leakage), reliability (EM) and timing (hold)
Simulation Needs for Stacked Die Designs
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Simulation Approaches for Stacked Die Designs
Power
ESD Signal
Thermal
Model based • Compact, IP protection
• Simplified and open format
Concurrent • Simultaneous analysis
• Multiple layout/result display
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Contain self-consistent electrical data
Enable seamless connections to other
models or to chip/interposer layout
Be in open standard format
Simplified topology to enable analysis
– Power estimation
– Power noise: DC and time-domain
– Impedance analysis (frequency/DC)
– Reliability analysis (EM, ESD)
Similar or integrated model for thermal
Contain technology / design parameters
Model Requirements for Stacked Die Analysis
Package
Interposer
Die 1 Die 2
Package netlist (RLCK / S-parameter)
Interposer Layout
Die 1 Model
Die 2 Layout
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Resource: Sarkar, “System level power distribution noise closure: Looking beyond the SoC power integrity challenge”, DAC 2010.
Model Based Stacked Die Analysis Self-Consistency of Model
IC Model (e.g. CPM)
Full layout based analysis Model based analysis
e.g. using RedHawkTM e.g. using Spice
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Streamlined import and hookup
Define model creation options (static, dynamic – VCD/V-less)
Define content for stacked die power analysis (estimation, drop, …)
Model Based Stacked Die Analysis Open Interface Protocols
ASIC
RAM uC
DSP
S/P
DMA
Package netlist (RLCK / S-parameter)
Interposer Layout
Die 1 Model
Die 2 Layout
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Resource: Singh et al, “Design and optimization of a power delivery network for 3D stacked die designs”, DesignCon 2011.
Case Studies of Stacked Die Design Analysis Co
ncurrent setup
Mod
el based
setup
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Resource: Singh et al, “Design and optimization of a power delivery network for 3D stacked die designs”, DesignCon 2011.
Case Studies of Stacked Die Design Analysis
Concurrent analysis: Voltage drop on both die
Com
parin
g co
ncur
rent
ver
sus
mod
el b
ased
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Resource: Doyen et al, “Analysis of Power Delivery Network of Multiple Stacked ASICs using TSV and Micro-bumps”, DAC 2010.
Case Studies of Stacked Die Design Analysis
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Model Based Thermal Analysis
System Designers Cooling System Design
IC Designers Power, EM Analysis
Package Design
Thermal Profile & Thermal Model
Package Designers
Thermal Analysis
SentinelTM-TI
IC DESIGN
IC Designers
CTM Generation
RedHawk
CTM P
T
CTM: Chip-Thermal-Model, Temperature dependent library of power maps for each chip
3D Temp Profile layer-by-layer
Thermal Model Θ-JA/JB/JC, Delphi
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Case Study: Model Based Thermal Analysis
Thermal hot spot in the bottom die on the lower right corner (aligned with power density hot-spot)
Thermal hot spot in the top die on the lower right corner (due to heat sharing from uBumps)
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Stacked die analysis presents several multi-physics problems
Good models are necessary to bridge design and organization silos
Apache is working on several areas:
– Stacked die power noise simulation
– Stacked die thermal and mechanical stress modeling
– Reliability and timing analysis
Working with Si2 on Open3D initiative
Re-cap and Summary
