Automotive ADAS MPSoC Roadmap on GF FDSOI technology SOI...
Transcript of Automotive ADAS MPSoC Roadmap on GF FDSOI technology SOI...
Automotive ADAS MPSoC Roadmap on GF FDSOI technology
SOI Consortium Santa Clara, Apr. 26th, 2018
Dr. Jens Benndorf MD, COO Dream Chip
Dream Chip Technologies GmbH
Dream Chip Technologies
DCT Company Profile
Dream Chip Technologies …
• Positioned as a Fabless Semiconductor Engineering Company for medium to large SoC designs covering the whole range from Architecture, Specification, Design, Verification to GDSII with a strong focus on Vision Processing
• Technologies: 130nm, 40nm, 28nm, 22nm FDX, 14/16nm FF • 75 Employees/ 65 Engineers with 10 … 20 years SoC design experience • Based in Hanover (HQ) and Hamburg, Germany • Member of Silicon Saxony/ Germany • Cadence Design Center Partner for Tensilica
Dream Chip Technologies GmbH
Dream Chip Technologies
Source: Texas Instruments
Assisted Driving requires Cameras, Radar, Lidar and Ultrasonic
Dream Chip Technologies GmbH
Dream Chip Technologies
Use Cases
I/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A534x Tensilica
Vision P6
InterconnectI/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A53
Interconnect
4x Tensilica Vision P6
Dream Chip Technologies GmbH
Dream Chip Technologies
Use Case #1: Digital Mirroring
Source:
Dream Chip Technologies GmbH
Dream Chip Technologies
Use Case #2 : 360 deg Top View Camera
Dream Chip Technologies GmbH
Dream Chip Technologies
Use Case #3 : Pedestrian detection via HOG and CNNs
Dream Chip Technologies GmbH
Dream Chip Technologies
MPSoC Chip Architecture
I/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A534x Tensilica
Vision P6
InterconnectI/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A53
Interconnect
4x Tensilica Vision P6
Dream Chip Technologies GmbH
Dream Chip Technologies
SDIP Roadrunner 2 (TO Jan. 2017)
Dream Chip Technologies GmbH
Dream Chip Technologies
Floorplan
IVP: Pixel Level
Memory IF
Memory IF
Lock-Step
ARM A53: Object L.
• Tape-Out on Jan. 10th, 2017
• Global Foundries – 22 FDX GF – externally adjustable BIAS voltage – 8x8 mm (64 mm^2)
• Calculation Power – ARM Cortex A53 quad core – 4x Tensilica Vision P6 – optimized for ADAS and CNN – 4x video-in, 1x video-out
• MCM package – DIE + 2x DDR4 on Silicon interposer
Dream Chip Technologies GmbH
Dream Chip Technologies
CNN capabilities
I/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A534x Tensilica
Vision P6
InterconnectI/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A53
Interconnect
4x Tensilica Vision P6
Dream Chip Technologies GmbH
Dream Chip Technologies
• Convolutional Neural Network (CNN) benchmark − Speedup of 64 through VP6 optimization − VP6: 330 CNNs / s @ 750 MHz, 4 W − Core-i5: 83 CNNs/s @ 2,6 GHz, 45 W
• 360°Surround View − VP6: 30 fps @ 750 MHz, ~4 W − Intel GPP: 8 fps @ 4x3,4 GHz, ~65 W
➢ Tensilica Vision P6 architecture (512b SIMD, 5-way VLIW, DMA, Gather-Scatter) fits to common Computer Vision use cases
Intel GPP Tensilica VP6
x45 x61
CNN and Top View Performance Benchmarks
Dream Chip Technologies GmbH
Dream Chip Technologies
AlexNet performance comparisonVision P6 (¼ SDIP)
Ceva XM6(IP planned)
Nvidia X1(SoC)
Clock rate 1.1 GHz 1.5 GHz 690 MHz
Multipliers 256 128+512 256
GMAC 282 395 176
AlexNet runtime 5.2 ms 3.7 ms 15 ms
AlexNet throughput 192 fps* 268 fps** 67 fps***
AlexNet throughput normalized to 1.1 GHz 192 fps 196 fps 106 fps
*: Source: Cadence Design Systems **: extrapolated from CEVA presentation “Fifth-Generation CEVA Imaging & Vision Silicon IP”***: Source: Nvidia white paper “GPU-Based Deep Learning Inference: A Performance and Power Analysis” (single batch)
Dream Chip Technologies GmbH
Dream Chip Technologies
Power Analysis (no power optimization)
Dream Chip Technologies GmbH
Dream Chip Technologies
MPSoC Chip / Starter Kit
I/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A534x Tensilica
Vision P6
InterconnectI/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A53
Interconnect
4x Tensilica Vision P6
Dream Chip Technologies GmbH
Dream Chip Technologies
System in Package Design
System-on-Module features • 4GB LP-DDR4 3200 RAM
Interfaces • Four 300MB/s video inputs • One 300MB/s video output • Gigabit Ethernet
Dream Chip Technologies GmbH
Dream Chip Technologies
Assembling the SOM...
Overview • Power management and
measurement • Chip power supplies included
Benefits • Reduced application-specific
baseboard complexity • Interfaces customizable to
application requirements
Dream Chip Technologies GmbH
Dream Chip Technologies
Demo
I/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A534x Tensilica
Vision P6
InterconnectI/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A53
Interconnect
4x Tensilica Vision P6
Dream Chip Technologies GmbH
Dream Chip Technologies
ELIV2017/AutoSense 2017/GTC2017
Dream Chip Technologies GmbH
Dream Chip Technologies
MWC 2018
■Pedestrian Detection based on CNN technology executed on two Vision P6 processors at MWC 2018
Dream Chip Technologies GmbH
Dream Chip Technologies
Whats Next?
I/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A534x Tensilica
Vision P6
InterconnectI/Os
Mem
ory
4x Video InVideo Out
4x ISP
2x ARM Cortex-R5
4x ARM Cortex-A53
Interconnect
4x Tensilica Vision P6
Dream Chip Technologies GmbH
Dream Chip Technologies
VP Roadmap
Dream Chip Technologies GmbH
Dream Chip Technologies
SDIP Roadmap
Roadrunner 14x VP6, 4xSensors1024 MACs0.6 TMAC/s175 GMAC/W64mm2
Roadrunner 24x VP6, 4xSensors1024 MACs0.7 TMAC/s175 GMAC/W64mm2, 22nmFDX
Veyron 2xVP6, 2xVC5, 4xSens.2.5 kMACs2 TMAC/s0.8 TMAC/W90mm2, 22nm FDX
Chiron 2xVP6, NG C5, 8xHDR ISPs16 kMACs48 TMAC/s3-4 TMAC/W2-2.5 TMAC/mm2130mm2, 12nm FDX
Oct. 2016 Jan. 2017 Jul. 2018 Dec. 2019 Time
Perfo
rman
ce
Dream Chip Technologies GmbH
Dream Chip Technologies
Thank You! Please contact
Dream Chip Technologies GmbH Steinriede 10
D-30827 Garbsen/Hannover Germany
+49-5131-90805-120