Truly Innovative 28nm FDSOI Technology for …...Truly Innovative 28nm FDSOI Technology for...
Transcript of Truly Innovative 28nm FDSOI Technology for …...Truly Innovative 28nm FDSOI Technology for...
Truly Innovative 28nm FDSOI Technology for Automotive Microcontroller
Applications embedding 16MB Phase Change Memory
F.ARNAUD1, P.ZULIANI2, J.P.REYNARD1, A. GANDOLFO2, F.DISEGNI2, P.MATTAVELLI2, E.GOMIERO2, G.SAMANNI2, C.JAHAN3, R.BERTHELON1, O.WEBER3, E.RICHARD1, V.BARRAL3, A.VILLARET1, S.KOHLER1,
J.C.GRENIER1, R.RANICA1, C.GALLON1, A.SOUHAITE3, D.RISTOIU1, L.FAVENNEC1, V.CAUBET1, S.DELMEDICO1, N.CHERAULT1, R.BENEYTON1, S.CHOUTEAU1, P.O.SASSOULAS1, A.VERNHET1, Y.LE FRIEC1, F.DOMENGIE1,
L.SCOTTI2, D.PACELLI2, J.L.OGIER1, F.BOUCARD1, S.LAGRASTA1, D.BENOIT1, L.CLEMENT1, P.BOIVIN4, P.FERREIRA1, R.ANNUNZIATA2, P.CAPPELLETTI2
1STMICROELECTRONICS, 3CEA-LETI, 850 rue Jean Monnet 38926 Crolles, France2STMICROELECTRONICS via Camillo Olivetti 2, Agrate Brianza, Italy
4STMICROELECTRONICS, zone industrielle, 190 avenue Coq, 13106 Rousset, France
Outline of Presentation
Introduction
Technology description
CMOS devices suite
PCM analytical cell
16MB PCM array results
Conclusions
2IEDM conference, Dec 3-5 2018, San-Francisco, CA
Outline of Presentation
Introduction
Technology description
CMOS devices suite
PCM analytical cell
16MB PCM array results
Conclusions
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Automotive Microcontrollers
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*Source: Strategy Analytics
Automotive MCU growth contributors:
Advanced Powertrain: combining Electric Motors, Thermal Engine and Transmission management
Electrification: smart power supporting electrification
Gateways: Secure communication interfaces
ADAS: safety microcontrollers
eNVM trend: increase memory size due to:- increased software complexity - multiple firmware image storage
Body600 M$
Gateway740 M$
ADAS MCU1.4 B$
Powertrain, Chassis & Safety
2.3 B$
Electrification650 M$
4.1B$
5.7B$
0
1
2
3
4
5
6
2018 2025
Microcontroller Market
+4,8%CAGR
Microcontroller Chips for Automotive
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eNVM PMU
Analog LOGIC I/Os
Real MCU layoutfor automotive
Physical Mechanisms for eNVM
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Charges manipulation Atoms manipulation Spin manipulation
STT MRAMOx.RAMPCRAMeFLASH
© ESF3 structure from SST
HRS LRS
Y-H Lin et al, “Excellent high T° retention of InNOxNy ReRAM by interfacial layer engineering”VLSI-TSA, 2018
GeSbTe phase diagram
T. Kawahara et al, “Spin transfer torque RAM technology”Mircoelectron Reliability, 2012
Phase Change Memory Principle
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Crystalline phase Crystalline phaseAmorphous phase
from SET (1) state to RESET (0) state from RESET (0) stateto SET (1) state
current
time
current
time
Outline of Presentation
Introduction
Technology description
CMOS devices suite
PCM analytical cell
16MB PCM array results
Conclusions
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Technology Architecture
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GST material
heater
Stacked contacts in logic/SRAM
Via in PCM array
Contact
Contact
Handle substrate
Thin Si film Thin buried oxide
PCM array Logic/SRAM area
Process Integration Sequence
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<100> 45° off-axisFDSOI Substrate
HYBRID BRICK(Bulk & FDSOI)
ISOLATION(STI & well)
GATE STACK(Triple GOx)
VT ADJUST(NMOS & PMOS)
GATE PATTERNING(5V / 1V8 / 1V)
JUNCTIONS(raised SD & I2)
SALICIDE(SiProtect & NiSi)
CONTACT(barre & hole)
PCM ELEMENT(heater & GST)
VIA-0(to PCM & contact)
M1 WIRES(single damascene)
THIN METAL(Trench First HM)
INTERM. METAL(Trench First HM)
THICK METAL(xxxxx)
ALU PAD(Alu & passivation)
Co-Integrated Memories Morphology
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GST
heater
BL
WL
SL
HD SRAM Cell (0,120um2) PCM Cell (0,036um2)
Pull-up
STI
Buriedoxide
GNDSharedContact
Pull-down
Devices Suite - Morphology
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5V Transistor Logic Transistor
140A
0,6um
1,8V Transistor
34A
0,15um
BULK AREA
SOI AREA
SRAM Transistor
SOI AREA SOI AREA
16A
28nm
16A
36nm
PCM Selector
16A
30nm
SOI AREA
PCM Element Morphology
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HEATER
GST
CONTACT
HEATER
GST
Cel
l in
X d
irec
tio
n
Cel
l in
Y d
irec
tio
n
SELECTOR
Outline of Presentation
Introduction
Technology description
CMOS devices suite
PCM analytical cell
16MB PCM array results
Conclusions
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Devices Table
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DevicesLogic
devicesSRAM
devicesI/O devices
VDDnom (Volt) 1 1 1,5 & 1,8
Lmin (um) 0,028 0,036 0,1 & 0,15
Tinv (nm) 1,6 1,6 3,4
VT options HVT & LVT LL & HS RVT LVT
Substrate FDSOI FDSOI FDSOI
DevicesHV/Analog
devicesESD devices
VDDnom (Volt) 5 1 1,8
Lmin (um) 0,6 0,048 0,15
Tinv (nm) 14 1,6 3,4
VT options HVT RVT RVT
Substrate BULK FDSOI BULK
Core oxide
IO oxide
HV oxide
Core Oxide Transistors – Well Scheme
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p-BP
p-well
NMOS PMOS
n+ n+
n+ p+
p+ n+n-BP
p+
n-well
p+
GND VDD
p-BP
n-well
NMOS PMOS
n+ n+
n+ p+
p+ p+n-BP
n+
p-well
p+
GND GND
HIGH VT option (regular well) LOW VT option (flip well)
p-BP
n-well
NMOS PMOS
n+ n+
n+ p+
p+ p+n-BP
n+
p-well
p+
GND GND
LOW VT option (flip well)
p-BP
n-well
NMOS PMOS
n+ p+
p+ p+n-BP
n+
p-well
p+n+n+
GND GND
HIGH VT option (flip well)
Mix & matchcapability
VT adjust
Digital Performance & Design Flexibility
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100% performance enhancement
3decadesreduction
Lg= 28nm
Lg= 32nm
Lg= 38nm
Gate length
FBB
VT adjust
Low VT
High VT
Fastest
38nm
0,9V
28nm
Low leakage
Reference
5V Transistors – Digital Characteristics
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PMOS NMOS PMOS NMOS
VGS=5V
VGS=4V
VGS=3V
VGS=2V
VGS=1V
Transfer characteristic Output characteristic
1pA/um
Triple Gate Oxide Devices Platform for Automotive Micro-Controllers
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NMOS
PMOS
HV Transistor
Logic Transistor
IOs Transistor
5V Transistor – Analog Characteristics
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Flicker Noise
NMOS
PMOS
MatchingPMOS
MatchingNMOS
5V Transistor – Gate Oxide Reliability
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10y life time 10y life time
5V
+1
0%
5V
+1
0%
PMOS NMOS
5V Transistor – Hot Carrier Injection
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10 years life time
VD
D= 5
V + 1
0%
PASS
Outline of Presentation
Introduction
Technology description
CMOS devices suite
PCM analytical cell
16MB PCM array results
Conclusions
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MOS Selector Requirements
• Deliver high drive current for cell programming phase (reaching GST melting point)
• Use optimum W/L ratio reducing the cell area (cost effective solution)
• Reading operation at low Voltage
• Mitigate leakage current (IOFF) of un-selected Word-Line and selected Bit-Line during writing and reading steps
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MOS Selector Structure
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NMOS
SourceLine
Buried oxide
PWELL = Back Bias (RBB for leakage mitigation)
BitLine
NMOS
RBB
RBB
NMOS
NMOS
WL
SL
SL
BL
Storage Element
WordLine
WordLine
SourceLine
Enhanced MOS Selector with RBB Technique
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Optimum
Area penalty
1T1R Analytical Cell Description
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VBL
VWL
VRBB
GST
HEATER
1T1R Analytical Cell Electrical Characteristics
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LRS“1”
HRS“0”
Analytical Cell Endurance
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LRS trend
HRS trend
Cycling algorithm
LRSHRS
10Mcycles
GST RESET Data Retention vs T°
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N.Ciocchini et al“Modeling Resistance Instabilities of SET and RESET States in Phase Change Memory with Ge-rich GeSbTe”IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
Outline of Presentation
Introduction
Technology description
CMOS devices suite
PCM analytical cell
16MB PCM array results
Conclusions
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16MB Test Chip & Array Organization
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4MB PCM array 4MB PCM array
4MB PCM array 4MB PCM array
I/Os
Row decoders
Sense amps
SL
On-state selector
MOS selector
PCM
OFF-state selectors
16MB SET & RESET States Distributions
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16MB statistics
16MB Test Chip Reliability Figures
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ENDURANCE RESET RETENTION
MCU Demo Chip Preliminary Results
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eNVM PMU
Analog LOGIC I/Os
MCU content & specs
Core 32b processor
SRAM 640KB
PCM 6MB
T range -40C - 165C
Supply 0.9-1.1V / 4.5-5.5V
Preliminary reliability tests
Soldering Pass (30/30)
Data retention Pass (30/30)
Endurance (10K) Pass (30/30)
Outline of Presentation
Introduction
Technology description
CMOS devices suite
PCM analytical cell
16MB PCM array results
Conclusions
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Conclusions
• For the first time, Non volatile Phase Change Memory has been co-integrated with 28nm FDSOI technology for microcontroller applications in the Automotive market
• Triple gate oxide scheme enabling 5V transistor with FDSOI substrate for analog requirements in Automotive system
• Attractive leakage/drivability of FDSOI NMOS selector leveraging Reverse Body Biasing technique
• Fully validated 0,036um2 PCM cell using optimized GST alloy showing robust endurance and good activation energy compatible with Automotive criteria (150°C achieved)
• Excellent PCM current distributions demonstrated on 16MB array before and after 150°C bake without degradation after 10k cycles
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Acknowledgements
• Innovation proposed and developed by design, process, electrical characterization and product test teams from European ST sites (Rousset, Agrate and Crolles) using patents in PCM cell design and GST alloy optimization for automotive
• The authors would like to warmly thank our colleagues from CEA-LETI located in Grenoble for their strong technical expertise, PDF Solution and their constant support in deep electrical characterizations on this technology platform
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