ATLAS Tracker Upgrade Stave Collaboration Workshop

Oxford 6-9 February 2012

ABC 130 Hybrid

Overview

•First pass of the hybrid (and module)•Proposed topology and geometry of hybrid•Using realistic assumptions for asic geometries, hybrid build and layout

•Still some uncertainties•Especially true for placement of SP bypass (and HV filtering)

•Proposal is to move off hybrid onto bus cable – is this possible?•Hybrid now sits within the area of the sensor , no overlap

•Able to wire-bond to the bus cable?•Use of 3 layer build hybrid without shield layer, does this matter?•Hybrid LVDS Bus termination

•Propose making use of embedded resistors within ABC130 – no discretes

•Hybrid on Panel Testing, first pass.

ABC130 Hybrid/module - Topology & GeometryAssumptions

•Sensor geometry: 97.54mm x 97.54mm

•ABC130: 7.9mm x 6mm (target size)•Width increased from 7.5mm to 7.9mm

•HCC: 3.5mm x 3.5mm (target size)

Hybrid Detail•Hybrid: 15mm x 97.5mm

•Sits within the area of the sensor – no overhang

•3 layer build (top – down)•Layer 1: Component + trace•Layer 2: Trace + VDD + hatched GND•Layer 3: GND•Typically ≥100µm track & gap

•Two data loops of 5 x ABC130/loop•80MHz or 160MHz on hybrid data clocks•Stave data rates of 160Mbs or 320Mbs

•Readout each end of a column – redundancy

•No SP Bypass circuitry on hybrid (+HV?)•Propose attachment to the Bus cable

•Ideally ALL Hybrids to be identical

15mm

48.75mm

63.75mm

Data Loop 0

Data Loop 1

Data I/O (Service side)

Power Entry

0

1

2

3

4

5

6

7

8

9

HCC

NTC

ABC130 Hybrid – Layer Detail

Layer 1 Layer 2 Layer 3

7.9mm

1.636mm

ABC130 Data Paths

0508 Capacitor Array (4 x 100nF,10V, X7R)Front-end and Digital Decoupling

Stave I/O

Capacitor Bank for AC-Coupled Stave Side Signals (100pF, 50V, X7R, 0402 devices)

HCC Pad count ~80(double row bonding)

VDD

Hatched GNDAdded to balance the

build

GND

ASIC Bus Bond Field

Hybrid Bus termination embedded in final ABC130

Strip Bias Capacitor

Bond pads typically 150µm x 300µm

Hybrid to Bus Cable wire-bonding

Bus Detail

225µm pitch

150µm x 400µm

2mm

•Multi-drop Bus is 100µm track & 125µm gap (was originally 100µm T&G)•Minimum gap is 100µm between bond pad and track

3.675mm

Stave I/O

ABC130 Hybrid – Is 3 layer build ok?•Tests on present ABCN-250 hybrid, provisionally show there is a problem with pickup

•Test module constructed using a shielded (reference) and a shield-less hybrid•Input noise from 3PTG for both hybrids identical•BUT shield-less hybrid shows a regular pattern in occupancy from the DTnoise scan (see below)•Peaks correlate geometrically with vias associated with the COM line on the hybrid – not the bus trace

•Problem due to vias not being blind whereas on shielded hybrid they are

•Expect the use of blind vias throughout hybrid build to resolve this•Final submission of the ABCN-25 asic hybrid planned to be shield-less as proof of principle

Shield-less Hybrid

Shielded Hybrid

Dtnoise Plot

Hybrid Bypass(DCDC?)

PWR

Panel Testing of hybrids, first pass

•To facilitate tooling, plan is to make the panel ‘flat’ – minimise the use of connectors around hybrid areas

•Hybrid data I/O will bond out to a bus embedded within the flex circuit•Terminates to a connector to hook up to DAQ (Samtec 1.27mm pitch, detail as per HSIO for stavelet?)

•Propose using NTC as vacuum interlock – necessary to exclude from HCC?

•Assume Serial Powering? What are the overheads? •Hybrid power and bypass (on separate PCB carrier)•Matches up to pads on panel – sprung loaded pins or connector (on carrier) used for connection to hybrid•AC coupling of hybrid data paths back to DAQ

•Parallel powering might be easier...•DC connection for hybrid data paths, but not easy to get power in to hybrids (DCDC maybe?)

Data I/OBus Termination

(on panel)

Wire Bonds to bus on panel

DAQ

NTC