ASSESSING RADIATION HARDNESS OF SIC MOS STRUCTURES · 2018. 9. 26. · MOS5 24 150 30 →GATE...
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ASSESSING RADIATION HARDNESS OF SIC MOS STRUCTURES Juan Moreno - Alter Technology Philippe Godignon - IMB-CNM - CSIC Enrique Maset - University of Valencia Silvia Massetti - European Space Agency → MOTIVATION AND STUDY STRATEGY This study aims to support the development of discrete European radiation hardened SiC power MOSFET for use in space applications by means of studying the gate oxide in terms of SEE and TID as one of the key parameters in the future development of these devices. The resistance of the P/N junctions present in these devices was also studied as well taking into account the problems seen in Schottky junctions under heavy ions radiation combined with high voltage. The following approach to better understand SiC Power MOSFET sensitivity was followed: ▪ Gate Oxide oxidation process and gate geometry study: 3 oxidation processes + 5 gate geometries tested under gamma and heavy ions ▪ Heavy Ions test of 600V HV L-DMOS with experimental boron-doped gate oxide that could improve radiation hardness ▪ Heavy ions onto 1200V PIN diodes fully representative of the built-in ones present in power MOSFETs → HV L-DMOS UNDER HEAVY IONS Catastrophic damage of the devices for bias values as low as VDS=200V for LET values of 32.4 and VDS=400V for 20.4 MeV/cm 2 /mg(Si). The damage occurs during radiation while biasing or during intermediate PIGS after a step. Results: →ACKNOWLEDGMENTS Project funded by European Space Agency, AO/1-8081/14/NL/KML “Prototyping and Characterization of Radiation Hardened SiC MOS Structures” DUT Gate Width (μm) Gate Length (μm) Channel Rotation Vs flat (11-20) (°) MOS1 2 150 0 MOS2 4 150 0 MOS3 24 150 0 MOS4 4 300 0 MOS5 24 150 30 →GATE OXIDATION PROCESSES & GEOMETRIES DUTs description: SiC Lateral MOS Results: ▪ No failures under heavy ions beams up to LET=62.5MeV /mg/cm 2 ▪ Total recovery after annealing for gamma (300Krad) ▪ Small differences among oxide types and no difference among gate geometries • Ox1: Thermally grown gate thin SiO2 oxide in N2O ambient + TEOS deposition 400 Å • Ox2: Thermally grown gate SiO2 oxide + Boron doped 1 + TEOS 400 Å • Ox3: Thermally grown gate thin SiO2 oxide in N2O ambient + TEOS deposition 400 Å with oxidation process optimization LET V GS (V) V DS (V) Damage 10.0 0, 2.5, -5 0 no 20.4 0, 2.5, -5 0 no 32.4 0, 2.5, -5 0 no 10.0 0 up to 500 no 20.4 0 up to 500 PIGS after 400V run 32.4 0 up to 500 PIGS after 200V run 62.5 0 up to 500 200V run 20.4 -5 up to 500 400V run → PIN DIODES UNDER HEAVY IONS Built-in diodes tested separately revealed the sensitivity of this area of the power MOSFET to heavy ions while HV is applied. Damage of the PIN occurs for reverse voltages slightly higher than for Schottky of previous studies. Results: DUT LET Vrev Step (V) Failure at PiN1 10.0 100 abrupt failure @500V PiN2 20.4 100 abrupt failure @500V PiN3 32.4 100 degradation @400V PiN4 62.5 100 degradation @400V PiN7 20.4 25 degradation @400V PiN8 20.4 20 degradation @420V PiN9 32.4 25 degradation @400V PiN11 32.4 20 degradation @400V →CONCLUSIONS - SEE testing of the lateral MOS revealed no sensitivity of the devices to heavy ions. A possible explanation for this could be that damage in vertical DMOS is mainly located in the JFET area between p-wells which is submitted to higher electric fields. No important differences could be - SEE testing of the L-DMOS: In vertical power devices, the weak area is the JFET zone located below the gate between the p-wells. In the LDMOS, there is no JFET area as the top cell is not symmetrical. In these structures, the high peak of electric field is usually at the end of the gate metallization where probably was located the breakdown point during our campaign. While in vertical power MOSFETs, the breakdown is taking place in the bulk, either in the P-well junction or in the termination junction. Modelling of the electric field distribution in the LDMOS at 500V clearly shows the peak electric field located at the end of the gate metal. A clear improvement of this device could be then to increase the oxide below the metal in the gate end. For the L-DMOS under test, the damage is located in a different area than in the vertical DMOS. This explains degradation happening during irradiation steps, while in a vertical structure, the damage is usually revealed during PIGS. detected comparing oxidation processes and gate geometries. However, slightly better behaviour under gamma radiation was observed for the devices with boron doped devices. - SEE testing of 1200V PIN diodes revealed sensitivity to ions but better behavior than 1200 Schottky diodes. The dependence of the damage with LET is also lower for PIN diodes. Thermographic analysis of damaged devices shows different failure modes for different devices, observing both uniform damage in the junction area and local hot spots probably located in already defective spots of the crystal depending on the sample analyzed.
Transcript of ASSESSING RADIATION HARDNESS OF SIC MOS STRUCTURES · 2018. 9. 26. · MOS5 24 150 30 →GATE...
ASSESSING RADIATION
HARDNESS OF SIC MOS
STRUCTURES
Juan Moreno - Alter Technology
Philippe Godignon - IMB-CNM - CSIC
Enrique Maset - University of Valencia
Silvia Massetti - European Space Agency
→ MOTIVATION AND STUDY STRATEGYThis study aims to support the development of discrete European radiationhardened SiC power MOSFET for use in space applications by means of studyingthe gate oxide in terms of SEE and TID as one of the key parameters in the futuredevelopment of these devices. The resistance of the P/N junctions present inthese devices was also studied as well taking into account the problems seenin Schottky junctions under heavy ions radiation combined with high voltage.
The following approach to better understand SiC Power MOSFET sensitivitywas followed:
▪ Gate Oxide oxidation process and gate geometry study: 3 oxidationprocesses + 5 gate geometries tested under gamma and heavy ions
▪ Heavy Ions test of 600V HV L-DMOS with experimental boron-doped gateoxide that could improve radiation hardness
▪ Heavy ions onto 1200V PIN diodes fully representative of the built-in onespresent in power MOSFETs
→ HV L-DMOS UNDER HEAVY IONSCatastrophic damage of the devices for bias values as low as VDS=200V for LETvalues of 32.4 and VDS=400V for 20.4 MeV/cm2/mg(Si). The damage occursduring radiation while biasing or during intermediate PIGS after a step.
Results:
→ACKNOWLEDGMENTSProject funded by European Space Agency, AO/1-8081/14/NL/KML “Prototyping and Characterization of Radiation Hardened SiC MOS Structures”
DUT Gate
Width (µm)
Gate Length (µm)
Channel Rotation Vs
flat (11-20) (°)MOS1 2 150 0MOS2 4 150 0MOS3 24 150 0MOS4 4 300 0MOS5 24 150 30
→GATE OXIDATION PROCESSES & GEOMETRIESDUTs description: SiC Lateral MOS
Results:▪ No failures under heavy ions
beams up to LET=62.5MeV/mg/cm2
▪ Total recovery after annealing forgamma (300Krad)
▪ Small differences among oxidetypes and no difference amonggate geometries
• Ox1: Thermally grown gate thin SiO2 oxide inN2O ambient + TEOS deposition 400 Å
• Ox2: Thermally grown gate SiO2 oxide + Borondoped 1 + TEOS 400 Å
• Ox3: Thermally grown gate thin SiO2 oxide inN2O ambient + TEOS deposition 400 Å withoxidation process optimization
LET VGS (V) VDS (V) Damage10.0 0, 2.5, -5 0 no20.4 0, 2.5, -5 0 no32.4 0, 2.5, -5 0 no10.0 0 up to 500 no
20.4 0 up to 500PIGS after 400V run
32.4 0 up to 500PIGS after 200V run
62.5 0 up to 500 200V run20.4 -5 up to 500 400V run
→ PIN DIODES UNDER HEAVY IONSBuilt-in diodes tested separately revealed the sensitivity of this area of thepower MOSFET to heavy ions while HV is applied. Damage of the PIN occurs forreverse voltages slightly higher than for Schottky of previous studies.
Results:DUT LET
VrevStep(V)
Failure at
PiN1 10.0 100 abrupt failure @500VPiN2 20.4 100 abrupt failure @500VPiN3 32.4 100 degradation @400VPiN4 62.5 100 degradation @400VPiN7 20.4 25 degradation @400VPiN8 20.4 20 degradation @420VPiN9 32.4 25 degradation @400V
PiN11 32.4 20 degradation @400V
→CONCLUSIONS- SEE testing of the lateral MOS revealed nosensitivity of the devices to heavy ions. A possibleexplanation for this could be that damage invertical DMOS is mainly located in the JFET areabetween p-wells which is submitted to higherelectric fields. No important differences could be
- SEE testing of the L-DMOS: In vertical power devices, the weak area is theJFET zone located below the gate between the p-wells. In the LDMOS, there isno JFET area as the top cell is not symmetrical. In these structures, the highpeak of electric field is usually at the end of the gate metallization whereprobably was located the breakdown point during our campaign. While invertical power MOSFETs, the breakdown is taking place in the bulk, either inthe P-well junction or in the termination junction.
Modelling of the electric field distribution inthe LDMOS at 500V clearly shows the peakelectric field located at the end of the gatemetal. A clear improvement of this devicecould be then to increase the oxide belowthe metal in the gate end. For the L-DMOSunder test, the damage is located in a different area than in the vertical DMOS.This explains degradation happening during irradiation steps, while in a verticalstructure, the damage is usually revealed during PIGS.
detected comparing oxidation processes and gate geometries. However,slightly better behaviour under gamma radiation was observed for the deviceswith boron doped devices.
- SEE testing of 1200V PIN diodes revealed sensitivity toions but better behavior than 1200 Schottky diodes. Thedependence of the damage with LET is also lower for PINdiodes. Thermographic analysis of damaged devicesshows different failure modes for different devices,observing both uniform damage in the junction areaand local hot spots probably located in already defectivespots of the crystal depending on the sample analyzed.
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